1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <drm/drmP.h>
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "soc15.h"
28 #include "soc15d.h"
29
30 #include "vega10/soc15ip.h"
31 #include "vega10/GC/gc_9_0_offset.h"
32 #include "vega10/GC/gc_9_0_sh_mask.h"
33 #include "vega10/vega10_enum.h"
34 #include "vega10/HDP/hdp_4_0_offset.h"
35
36 #include "soc15_common.h"
37 #include "clearstate_gfx9.h"
38 #include "v9_structs.h"
39
40 #define GFX9_NUM_GFX_RINGS 1
41 #define GFX9_MEC_HPD_SIZE 2048
42 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
45
46 #define mmPWR_MISC_CNTL_STATUS 0x0183
47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52
53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
60 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62 MODULE_FIRMWARE("amdgpu/raven_me.bin");
63 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
67 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68 {
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
101 };
102
103 static const u32 golden_settings_gc_9_0[] =
104 {
105 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
106 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
107 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
108 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
109 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
110 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
112 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
113 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
114 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
115 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
116 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
117 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
118 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
119 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
120 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
121 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
122 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
123 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
124 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
125 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
126 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
127 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
128 };
129
130 static const u32 golden_settings_gc_9_0_vg10[] =
131 {
132 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
133 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
134 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
135 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
136 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
137 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
138 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
139 };
140
141 static const u32 golden_settings_gc_9_1[] =
142 {
143 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
144 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
145 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
146 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
148 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
149 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
151 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
152 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
153 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
154 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
155 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
156 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
157 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
158 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
159 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
160 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
161 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
162 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
163 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
164 };
165
166 static const u32 golden_settings_gc_9_1_rv1[] =
167 {
168 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
169 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
170 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
171 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
172 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
173 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
174 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
175 };
176
177 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
178 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
179
180 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
181 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
182 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
183 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
184 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
185 struct amdgpu_cu_info *cu_info);
186 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
187 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
188 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
189
gfx_v9_0_init_golden_registers(struct amdgpu_device * adev)190 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
191 {
192 switch (adev->asic_type) {
193 case CHIP_VEGA10:
194 amdgpu_program_register_sequence(adev,
195 golden_settings_gc_9_0,
196 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
197 amdgpu_program_register_sequence(adev,
198 golden_settings_gc_9_0_vg10,
199 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
200 break;
201 case CHIP_RAVEN:
202 amdgpu_program_register_sequence(adev,
203 golden_settings_gc_9_1,
204 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
205 amdgpu_program_register_sequence(adev,
206 golden_settings_gc_9_1_rv1,
207 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
208 break;
209 default:
210 break;
211 }
212 }
213
gfx_v9_0_scratch_init(struct amdgpu_device * adev)214 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
215 {
216 adev->gfx.scratch.num_reg = 8;
217 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
218 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
219 }
220
gfx_v9_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)221 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
222 bool wc, uint32_t reg, uint32_t val)
223 {
224 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
225 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
226 WRITE_DATA_DST_SEL(0) |
227 (wc ? WR_CONFIRM : 0));
228 amdgpu_ring_write(ring, reg);
229 amdgpu_ring_write(ring, 0);
230 amdgpu_ring_write(ring, val);
231 }
232
gfx_v9_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)233 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
234 int mem_space, int opt, uint32_t addr0,
235 uint32_t addr1, uint32_t ref, uint32_t mask,
236 uint32_t inv)
237 {
238 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
239 amdgpu_ring_write(ring,
240 /* memory (1) or register (0) */
241 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
242 WAIT_REG_MEM_OPERATION(opt) | /* wait */
243 WAIT_REG_MEM_FUNCTION(3) | /* equal */
244 WAIT_REG_MEM_ENGINE(eng_sel)));
245
246 if (mem_space)
247 BUG_ON(addr0 & 0x3); /* Dword align */
248 amdgpu_ring_write(ring, addr0);
249 amdgpu_ring_write(ring, addr1);
250 amdgpu_ring_write(ring, ref);
251 amdgpu_ring_write(ring, mask);
252 amdgpu_ring_write(ring, inv); /* poll interval */
253 }
254
gfx_v9_0_ring_test_ring(struct amdgpu_ring * ring)255 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
256 {
257 struct amdgpu_device *adev = ring->adev;
258 uint32_t scratch;
259 uint32_t tmp = 0;
260 unsigned i;
261 int r;
262
263 r = amdgpu_gfx_scratch_get(adev, &scratch);
264 if (r) {
265 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
266 return r;
267 }
268 WREG32(scratch, 0xCAFEDEAD);
269 r = amdgpu_ring_alloc(ring, 3);
270 if (r) {
271 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
272 ring->idx, r);
273 amdgpu_gfx_scratch_free(adev, scratch);
274 return r;
275 }
276 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
277 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
278 amdgpu_ring_write(ring, 0xDEADBEEF);
279 amdgpu_ring_commit(ring);
280
281 for (i = 0; i < adev->usec_timeout; i++) {
282 tmp = RREG32(scratch);
283 if (tmp == 0xDEADBEEF)
284 break;
285 DRM_UDELAY(1);
286 }
287 if (i < adev->usec_timeout) {
288 DRM_INFO("ring test on %d succeeded in %d usecs\n",
289 ring->idx, i);
290 } else {
291 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
292 ring->idx, scratch, tmp);
293 r = -EINVAL;
294 }
295 amdgpu_gfx_scratch_free(adev, scratch);
296 return r;
297 }
298
gfx_v9_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)299 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
300 {
301 struct amdgpu_device *adev = ring->adev;
302 struct amdgpu_ib ib;
303 struct dma_fence *f = NULL;
304 uint32_t scratch;
305 uint32_t tmp = 0;
306 long r;
307
308 r = amdgpu_gfx_scratch_get(adev, &scratch);
309 if (r) {
310 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
311 return r;
312 }
313 WREG32(scratch, 0xCAFEDEAD);
314 memset(&ib, 0, sizeof(ib));
315 r = amdgpu_ib_get(adev, NULL, 256, &ib);
316 if (r) {
317 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
318 goto err1;
319 }
320 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
321 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
322 ib.ptr[2] = 0xDEADBEEF;
323 ib.length_dw = 3;
324
325 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
326 if (r)
327 goto err2;
328
329 r = dma_fence_wait_timeout(f, false, timeout);
330 if (r == 0) {
331 DRM_ERROR("amdgpu: IB test timed out.\n");
332 r = -ETIMEDOUT;
333 goto err2;
334 } else if (r < 0) {
335 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
336 goto err2;
337 }
338 tmp = RREG32(scratch);
339 if (tmp == 0xDEADBEEF) {
340 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
341 r = 0;
342 } else {
343 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
344 scratch, tmp);
345 r = -EINVAL;
346 }
347 err2:
348 amdgpu_ib_free(adev, &ib, NULL);
349 dma_fence_put(f);
350 err1:
351 amdgpu_gfx_scratch_free(adev, scratch);
352 return r;
353 }
354
gfx_v9_0_init_microcode(struct amdgpu_device * adev)355 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
356 {
357 const char *chip_name;
358 char fw_name[30];
359 int err;
360 struct amdgpu_firmware_info *info = NULL;
361 const struct common_firmware_header *header = NULL;
362 const struct gfx_firmware_header_v1_0 *cp_hdr;
363 const struct rlc_firmware_header_v2_0 *rlc_hdr;
364 unsigned int *tmp = NULL;
365 unsigned int i = 0;
366
367 DRM_DEBUG("\n");
368
369 switch (adev->asic_type) {
370 case CHIP_VEGA10:
371 chip_name = "vega10";
372 break;
373 case CHIP_RAVEN:
374 chip_name = "raven";
375 break;
376 default:
377 BUG();
378 }
379
380 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
381 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
382 if (err)
383 goto out;
384 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
385 if (err)
386 goto out;
387 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
388 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
389 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
390
391 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
392 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
393 if (err)
394 goto out;
395 err = amdgpu_ucode_validate(adev->gfx.me_fw);
396 if (err)
397 goto out;
398 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
399 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
400 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
401
402 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
403 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
404 if (err)
405 goto out;
406 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
407 if (err)
408 goto out;
409 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
410 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
411 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
412
413 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
414 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
415 if (err)
416 goto out;
417 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
418 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
419 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
420 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
421 adev->gfx.rlc.save_and_restore_offset =
422 le32_to_cpu(rlc_hdr->save_and_restore_offset);
423 adev->gfx.rlc.clear_state_descriptor_offset =
424 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
425 adev->gfx.rlc.avail_scratch_ram_locations =
426 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
427 adev->gfx.rlc.reg_restore_list_size =
428 le32_to_cpu(rlc_hdr->reg_restore_list_size);
429 adev->gfx.rlc.reg_list_format_start =
430 le32_to_cpu(rlc_hdr->reg_list_format_start);
431 adev->gfx.rlc.reg_list_format_separate_start =
432 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
433 adev->gfx.rlc.starting_offsets_start =
434 le32_to_cpu(rlc_hdr->starting_offsets_start);
435 adev->gfx.rlc.reg_list_format_size_bytes =
436 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
437 adev->gfx.rlc.reg_list_size_bytes =
438 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
439 adev->gfx.rlc.register_list_format =
440 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
441 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
442 if (!adev->gfx.rlc.register_list_format) {
443 err = -ENOMEM;
444 goto out;
445 }
446
447 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
448 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
449 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
450 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
451
452 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
453
454 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
455 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
456 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
457 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
458
459 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
460 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
461 if (err)
462 goto out;
463 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
464 if (err)
465 goto out;
466 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
467 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
468 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
469
470
471 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
472 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
473 if (!err) {
474 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
475 if (err)
476 goto out;
477 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
478 adev->gfx.mec2_fw->data;
479 adev->gfx.mec2_fw_version =
480 le32_to_cpu(cp_hdr->header.ucode_version);
481 adev->gfx.mec2_feature_version =
482 le32_to_cpu(cp_hdr->ucode_feature_version);
483 } else {
484 err = 0;
485 adev->gfx.mec2_fw = NULL;
486 }
487
488 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
489 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
490 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
491 info->fw = adev->gfx.pfp_fw;
492 header = (const struct common_firmware_header *)info->fw->data;
493 adev->firmware.fw_size +=
494 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
495
496 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
497 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
498 info->fw = adev->gfx.me_fw;
499 header = (const struct common_firmware_header *)info->fw->data;
500 adev->firmware.fw_size +=
501 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
502
503 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
504 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
505 info->fw = adev->gfx.ce_fw;
506 header = (const struct common_firmware_header *)info->fw->data;
507 adev->firmware.fw_size +=
508 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
509
510 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
511 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
512 info->fw = adev->gfx.rlc_fw;
513 header = (const struct common_firmware_header *)info->fw->data;
514 adev->firmware.fw_size +=
515 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
516
517 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
518 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
519 info->fw = adev->gfx.mec_fw;
520 header = (const struct common_firmware_header *)info->fw->data;
521 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
522 adev->firmware.fw_size +=
523 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
524
525 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
526 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
527 info->fw = adev->gfx.mec_fw;
528 adev->firmware.fw_size +=
529 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
530
531 if (adev->gfx.mec2_fw) {
532 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
533 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
534 info->fw = adev->gfx.mec2_fw;
535 header = (const struct common_firmware_header *)info->fw->data;
536 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
537 adev->firmware.fw_size +=
538 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
539 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
540 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
541 info->fw = adev->gfx.mec2_fw;
542 adev->firmware.fw_size +=
543 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
544 }
545
546 }
547
548 out:
549 if (err) {
550 dev_err(adev->dev,
551 "gfx9: Failed to load firmware \"%s\"\n",
552 fw_name);
553 release_firmware(adev->gfx.pfp_fw);
554 adev->gfx.pfp_fw = NULL;
555 release_firmware(adev->gfx.me_fw);
556 adev->gfx.me_fw = NULL;
557 release_firmware(adev->gfx.ce_fw);
558 adev->gfx.ce_fw = NULL;
559 release_firmware(adev->gfx.rlc_fw);
560 adev->gfx.rlc_fw = NULL;
561 release_firmware(adev->gfx.mec_fw);
562 adev->gfx.mec_fw = NULL;
563 release_firmware(adev->gfx.mec2_fw);
564 adev->gfx.mec2_fw = NULL;
565 }
566 return err;
567 }
568
gfx_v9_0_get_csb_size(struct amdgpu_device * adev)569 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
570 {
571 u32 count = 0;
572 const struct cs_section_def *sect = NULL;
573 const struct cs_extent_def *ext = NULL;
574
575 /* begin clear state */
576 count += 2;
577 /* context control state */
578 count += 3;
579
580 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
581 for (ext = sect->section; ext->extent != NULL; ++ext) {
582 if (sect->id == SECT_CONTEXT)
583 count += 2 + ext->reg_count;
584 else
585 return 0;
586 }
587 }
588
589 /* end clear state */
590 count += 2;
591 /* clear state */
592 count += 2;
593
594 return count;
595 }
596
gfx_v9_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)597 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
598 volatile u32 *buffer)
599 {
600 u32 count = 0, i;
601 const struct cs_section_def *sect = NULL;
602 const struct cs_extent_def *ext = NULL;
603
604 if (adev->gfx.rlc.cs_data == NULL)
605 return;
606 if (buffer == NULL)
607 return;
608
609 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
610 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
611
612 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
613 buffer[count++] = cpu_to_le32(0x80000000);
614 buffer[count++] = cpu_to_le32(0x80000000);
615
616 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
617 for (ext = sect->section; ext->extent != NULL; ++ext) {
618 if (sect->id == SECT_CONTEXT) {
619 buffer[count++] =
620 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
621 buffer[count++] = cpu_to_le32(ext->reg_index -
622 PACKET3_SET_CONTEXT_REG_START);
623 for (i = 0; i < ext->reg_count; i++)
624 buffer[count++] = cpu_to_le32(ext->extent[i]);
625 } else {
626 return;
627 }
628 }
629 }
630
631 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
632 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
633
634 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
635 buffer[count++] = cpu_to_le32(0);
636 }
637
gfx_v9_0_init_lbpw(struct amdgpu_device * adev)638 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
639 {
640 uint32_t data;
641
642 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
643 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
645 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
646 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
647
648 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
649 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
650
651 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
652 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
653
654 mutex_lock(&adev->grbm_idx_mutex);
655 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
656 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
657 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
658
659 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
660 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
661 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
662 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
663 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
664
665 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
666 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
667 data &= 0x0000FFFF;
668 data |= 0x00C00000;
669 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
670
671 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
672 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
673
674 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
675 * but used for RLC_LB_CNTL configuration */
676 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
677 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
678 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
679 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
680 mutex_unlock(&adev->grbm_idx_mutex);
681 }
682
gfx_v9_0_enable_lbpw(struct amdgpu_device * adev,bool enable)683 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
684 {
685 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
686 }
687
rv_init_cp_jump_table(struct amdgpu_device * adev)688 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
689 {
690 const __le32 *fw_data;
691 volatile u32 *dst_ptr;
692 int me, i, max_me = 5;
693 u32 bo_offset = 0;
694 u32 table_offset, table_size;
695
696 /* write the cp table buffer */
697 dst_ptr = adev->gfx.rlc.cp_table_ptr;
698 for (me = 0; me < max_me; me++) {
699 if (me == 0) {
700 const struct gfx_firmware_header_v1_0 *hdr =
701 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
702 fw_data = (const __le32 *)
703 (adev->gfx.ce_fw->data +
704 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
705 table_offset = le32_to_cpu(hdr->jt_offset);
706 table_size = le32_to_cpu(hdr->jt_size);
707 } else if (me == 1) {
708 const struct gfx_firmware_header_v1_0 *hdr =
709 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
710 fw_data = (const __le32 *)
711 (adev->gfx.pfp_fw->data +
712 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
713 table_offset = le32_to_cpu(hdr->jt_offset);
714 table_size = le32_to_cpu(hdr->jt_size);
715 } else if (me == 2) {
716 const struct gfx_firmware_header_v1_0 *hdr =
717 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
718 fw_data = (const __le32 *)
719 (adev->gfx.me_fw->data +
720 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
721 table_offset = le32_to_cpu(hdr->jt_offset);
722 table_size = le32_to_cpu(hdr->jt_size);
723 } else if (me == 3) {
724 const struct gfx_firmware_header_v1_0 *hdr =
725 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
726 fw_data = (const __le32 *)
727 (adev->gfx.mec_fw->data +
728 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
729 table_offset = le32_to_cpu(hdr->jt_offset);
730 table_size = le32_to_cpu(hdr->jt_size);
731 } else if (me == 4) {
732 const struct gfx_firmware_header_v1_0 *hdr =
733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
734 fw_data = (const __le32 *)
735 (adev->gfx.mec2_fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 table_offset = le32_to_cpu(hdr->jt_offset);
738 table_size = le32_to_cpu(hdr->jt_size);
739 }
740
741 for (i = 0; i < table_size; i ++) {
742 dst_ptr[bo_offset + i] =
743 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
744 }
745
746 bo_offset += table_size;
747 }
748 }
749
gfx_v9_0_rlc_fini(struct amdgpu_device * adev)750 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
751 {
752 /* clear state block */
753 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
754 &adev->gfx.rlc.clear_state_gpu_addr,
755 (void **)&adev->gfx.rlc.cs_ptr);
756
757 /* jump table block */
758 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
759 &adev->gfx.rlc.cp_table_gpu_addr,
760 (void **)&adev->gfx.rlc.cp_table_ptr);
761 }
762
gfx_v9_0_rlc_init(struct amdgpu_device * adev)763 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
764 {
765 volatile u32 *dst_ptr;
766 u32 dws;
767 const struct cs_section_def *cs_data;
768 int r;
769
770 adev->gfx.rlc.cs_data = gfx9_cs_data;
771
772 cs_data = adev->gfx.rlc.cs_data;
773
774 if (cs_data) {
775 /* clear state block */
776 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
777 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
778 AMDGPU_GEM_DOMAIN_VRAM,
779 &adev->gfx.rlc.clear_state_obj,
780 &adev->gfx.rlc.clear_state_gpu_addr,
781 (void **)&adev->gfx.rlc.cs_ptr);
782 if (r) {
783 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
784 r);
785 gfx_v9_0_rlc_fini(adev);
786 return r;
787 }
788 /* set up the cs buffer */
789 dst_ptr = adev->gfx.rlc.cs_ptr;
790 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
791 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
792 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
793 }
794
795 if (adev->asic_type == CHIP_RAVEN) {
796 /* TODO: double check the cp_table_size for RV */
797 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
798 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
799 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
800 &adev->gfx.rlc.cp_table_obj,
801 &adev->gfx.rlc.cp_table_gpu_addr,
802 (void **)&adev->gfx.rlc.cp_table_ptr);
803 if (r) {
804 dev_err(adev->dev,
805 "(%d) failed to create cp table bo\n", r);
806 gfx_v9_0_rlc_fini(adev);
807 return r;
808 }
809
810 rv_init_cp_jump_table(adev);
811 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
812 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
813
814 gfx_v9_0_init_lbpw(adev);
815 }
816
817 return 0;
818 }
819
gfx_v9_0_mec_fini(struct amdgpu_device * adev)820 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
821 {
822 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
823 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
824 }
825
gfx_v9_0_mec_init(struct amdgpu_device * adev)826 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
827 {
828 int r;
829 u32 *hpd;
830 const __le32 *fw_data;
831 unsigned fw_size;
832 u32 *fw;
833 size_t mec_hpd_size;
834
835 const struct gfx_firmware_header_v1_0 *mec_hdr;
836
837 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
838
839 /* take ownership of the relevant compute queues */
840 amdgpu_gfx_compute_queue_acquire(adev);
841 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
842
843 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
844 AMDGPU_GEM_DOMAIN_GTT,
845 &adev->gfx.mec.hpd_eop_obj,
846 &adev->gfx.mec.hpd_eop_gpu_addr,
847 (void **)&hpd);
848 if (r) {
849 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
850 gfx_v9_0_mec_fini(adev);
851 return r;
852 }
853
854 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
855
856 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
857 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
858
859 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
860
861 fw_data = (const __le32 *)
862 (adev->gfx.mec_fw->data +
863 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
864 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
865
866 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
867 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
868 &adev->gfx.mec.mec_fw_obj,
869 &adev->gfx.mec.mec_fw_gpu_addr,
870 (void **)&fw);
871 if (r) {
872 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
873 gfx_v9_0_mec_fini(adev);
874 return r;
875 }
876
877 memcpy(fw, fw_data, fw_size);
878
879 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
880 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
881
882 return 0;
883 }
884
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)885 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
886 {
887 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
888 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
889 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
890 (address << SQ_IND_INDEX__INDEX__SHIFT) |
891 (SQ_IND_INDEX__FORCE_READ_MASK));
892 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
893 }
894
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)895 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
896 uint32_t wave, uint32_t thread,
897 uint32_t regno, uint32_t num, uint32_t *out)
898 {
899 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
900 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
901 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
902 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
903 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
904 (SQ_IND_INDEX__FORCE_READ_MASK) |
905 (SQ_IND_INDEX__AUTO_INCR_MASK));
906 while (num--)
907 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
908 }
909
gfx_v9_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)910 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
911 {
912 /* type 1 wave data */
913 dst[(*no_fields)++] = 1;
914 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
915 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
916 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
917 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
918 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
919 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
920 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
921 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
922 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
923 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
924 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
925 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
926 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
927 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
928 }
929
gfx_v9_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)930 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
931 uint32_t wave, uint32_t start,
932 uint32_t size, uint32_t *dst)
933 {
934 wave_read_regs(
935 adev, simd, wave, 0,
936 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
937 }
938
939
940 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
941 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
942 .select_se_sh = &gfx_v9_0_select_se_sh,
943 .read_wave_data = &gfx_v9_0_read_wave_data,
944 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
945 };
946
gfx_v9_0_gpu_early_init(struct amdgpu_device * adev)947 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
948 {
949 u32 gb_addr_config;
950
951 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
952
953 switch (adev->asic_type) {
954 case CHIP_VEGA10:
955 adev->gfx.config.max_hw_contexts = 8;
956 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
957 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
958 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
959 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
960 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
961 break;
962 case CHIP_RAVEN:
963 adev->gfx.config.max_hw_contexts = 8;
964 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
965 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
966 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
967 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
968 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
969 break;
970 default:
971 BUG();
972 break;
973 }
974
975 adev->gfx.config.gb_addr_config = gb_addr_config;
976
977 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
978 REG_GET_FIELD(
979 adev->gfx.config.gb_addr_config,
980 GB_ADDR_CONFIG,
981 NUM_PIPES);
982
983 adev->gfx.config.max_tile_pipes =
984 adev->gfx.config.gb_addr_config_fields.num_pipes;
985
986 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
987 REG_GET_FIELD(
988 adev->gfx.config.gb_addr_config,
989 GB_ADDR_CONFIG,
990 NUM_BANKS);
991 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
992 REG_GET_FIELD(
993 adev->gfx.config.gb_addr_config,
994 GB_ADDR_CONFIG,
995 MAX_COMPRESSED_FRAGS);
996 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
997 REG_GET_FIELD(
998 adev->gfx.config.gb_addr_config,
999 GB_ADDR_CONFIG,
1000 NUM_RB_PER_SE);
1001 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1002 REG_GET_FIELD(
1003 adev->gfx.config.gb_addr_config,
1004 GB_ADDR_CONFIG,
1005 NUM_SHADER_ENGINES);
1006 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1007 REG_GET_FIELD(
1008 adev->gfx.config.gb_addr_config,
1009 GB_ADDR_CONFIG,
1010 PIPE_INTERLEAVE_SIZE));
1011 }
1012
gfx_v9_0_ngg_create_buf(struct amdgpu_device * adev,struct amdgpu_ngg_buf * ngg_buf,int size_se,int default_size_se)1013 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1014 struct amdgpu_ngg_buf *ngg_buf,
1015 int size_se,
1016 int default_size_se)
1017 {
1018 int r;
1019
1020 if (size_se < 0) {
1021 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1022 return -EINVAL;
1023 }
1024 size_se = size_se ? size_se : default_size_se;
1025
1026 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1027 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1028 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1029 &ngg_buf->bo,
1030 &ngg_buf->gpu_addr,
1031 NULL);
1032 if (r) {
1033 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1034 return r;
1035 }
1036 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1037
1038 return r;
1039 }
1040
gfx_v9_0_ngg_fini(struct amdgpu_device * adev)1041 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1042 {
1043 int i;
1044
1045 for (i = 0; i < NGG_BUF_MAX; i++)
1046 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1047 &adev->gfx.ngg.buf[i].gpu_addr,
1048 NULL);
1049
1050 memset(&adev->gfx.ngg.buf[0], 0,
1051 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1052
1053 adev->gfx.ngg.init = false;
1054
1055 return 0;
1056 }
1057
gfx_v9_0_ngg_init(struct amdgpu_device * adev)1058 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1059 {
1060 int r;
1061
1062 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1063 return 0;
1064
1065 /* GDS reserve memory: 64 bytes alignment */
1066 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1067 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1068 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1069 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1070 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1071
1072 /* Primitive Buffer */
1073 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1074 amdgpu_prim_buf_per_se,
1075 64 * 1024);
1076 if (r) {
1077 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1078 goto err;
1079 }
1080
1081 /* Position Buffer */
1082 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1083 amdgpu_pos_buf_per_se,
1084 256 * 1024);
1085 if (r) {
1086 dev_err(adev->dev, "Failed to create Position Buffer\n");
1087 goto err;
1088 }
1089
1090 /* Control Sideband */
1091 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1092 amdgpu_cntl_sb_buf_per_se,
1093 256);
1094 if (r) {
1095 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1096 goto err;
1097 }
1098
1099 /* Parameter Cache, not created by default */
1100 if (amdgpu_param_buf_per_se <= 0)
1101 goto out;
1102
1103 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1104 amdgpu_param_buf_per_se,
1105 512 * 1024);
1106 if (r) {
1107 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1108 goto err;
1109 }
1110
1111 out:
1112 adev->gfx.ngg.init = true;
1113 return 0;
1114 err:
1115 gfx_v9_0_ngg_fini(adev);
1116 return r;
1117 }
1118
gfx_v9_0_ngg_en(struct amdgpu_device * adev)1119 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1120 {
1121 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1122 int r;
1123 u32 data;
1124 u32 size;
1125 u32 base;
1126
1127 if (!amdgpu_ngg)
1128 return 0;
1129
1130 /* Program buffer size */
1131 data = 0;
1132 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
1133 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1134
1135 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
1136 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1137
1138 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1139
1140 data = 0;
1141 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
1142 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1143
1144 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
1145 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1146
1147 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1148
1149 /* Program buffer base address */
1150 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1151 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1152 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1153
1154 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1155 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1156 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1157
1158 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1159 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1160 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1161
1162 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1163 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1164 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1165
1166 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1167 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1168 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1169
1170 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1171 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1172 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1173
1174 /* Clear GDS reserved memory */
1175 r = amdgpu_ring_alloc(ring, 17);
1176 if (r) {
1177 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1178 ring->idx, r);
1179 return r;
1180 }
1181
1182 gfx_v9_0_write_data_to_reg(ring, 0, false,
1183 amdgpu_gds_reg_offset[0].mem_size,
1184 (adev->gds.mem.total_size +
1185 adev->gfx.ngg.gds_reserve_size) >>
1186 AMDGPU_GDS_SHIFT);
1187
1188 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1189 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1190 PACKET3_DMA_DATA_SRC_SEL(2)));
1191 amdgpu_ring_write(ring, 0);
1192 amdgpu_ring_write(ring, 0);
1193 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1194 amdgpu_ring_write(ring, 0);
1195 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1196
1197
1198 gfx_v9_0_write_data_to_reg(ring, 0, false,
1199 amdgpu_gds_reg_offset[0].mem_size, 0);
1200
1201 amdgpu_ring_commit(ring);
1202
1203 return 0;
1204 }
1205
gfx_v9_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)1206 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1207 int mec, int pipe, int queue)
1208 {
1209 int r;
1210 unsigned irq_type;
1211 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1212
1213 ring = &adev->gfx.compute_ring[ring_id];
1214
1215 /* mec0 is me1 */
1216 ring->me = mec + 1;
1217 ring->pipe = pipe;
1218 ring->queue = queue;
1219
1220 ring->ring_obj = NULL;
1221 ring->use_doorbell = true;
1222 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1223 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1224 + (ring_id * GFX9_MEC_HPD_SIZE);
1225 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1226
1227 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1228 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1229 + ring->pipe;
1230
1231 /* type-2 packets are deprecated on MEC, use type-3 instead */
1232 r = amdgpu_ring_init(adev, ring, 1024,
1233 &adev->gfx.eop_irq, irq_type);
1234 if (r)
1235 return r;
1236
1237
1238 return 0;
1239 }
1240
gfx_v9_0_sw_init(void * handle)1241 static int gfx_v9_0_sw_init(void *handle)
1242 {
1243 int i, j, k, r, ring_id;
1244 struct amdgpu_ring *ring;
1245 struct amdgpu_kiq *kiq;
1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248 switch (adev->asic_type) {
1249 case CHIP_VEGA10:
1250 case CHIP_RAVEN:
1251 adev->gfx.mec.num_mec = 2;
1252 break;
1253 default:
1254 adev->gfx.mec.num_mec = 1;
1255 break;
1256 }
1257
1258 adev->gfx.mec.num_pipe_per_mec = 4;
1259 adev->gfx.mec.num_queue_per_pipe = 8;
1260
1261 /* KIQ event */
1262 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1263 if (r)
1264 return r;
1265
1266 /* EOP Event */
1267 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1268 if (r)
1269 return r;
1270
1271 /* Privileged reg */
1272 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1273 &adev->gfx.priv_reg_irq);
1274 if (r)
1275 return r;
1276
1277 /* Privileged inst */
1278 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1279 &adev->gfx.priv_inst_irq);
1280 if (r)
1281 return r;
1282
1283 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1284
1285 gfx_v9_0_scratch_init(adev);
1286
1287 r = gfx_v9_0_init_microcode(adev);
1288 if (r) {
1289 DRM_ERROR("Failed to load gfx firmware!\n");
1290 return r;
1291 }
1292
1293 r = gfx_v9_0_rlc_init(adev);
1294 if (r) {
1295 DRM_ERROR("Failed to init rlc BOs!\n");
1296 return r;
1297 }
1298
1299 r = gfx_v9_0_mec_init(adev);
1300 if (r) {
1301 DRM_ERROR("Failed to init MEC BOs!\n");
1302 return r;
1303 }
1304
1305 /* set up the gfx ring */
1306 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1307 ring = &adev->gfx.gfx_ring[i];
1308 ring->ring_obj = NULL;
1309 sprintf(ring->name, "gfx");
1310 ring->use_doorbell = true;
1311 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1312 r = amdgpu_ring_init(adev, ring, 1024,
1313 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1314 if (r)
1315 return r;
1316 }
1317
1318 /* set up the compute queues - allocate horizontally across pipes */
1319 ring_id = 0;
1320 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1321 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1322 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1323 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1324 continue;
1325
1326 r = gfx_v9_0_compute_ring_init(adev,
1327 ring_id,
1328 i, k, j);
1329 if (r)
1330 return r;
1331
1332 ring_id++;
1333 }
1334 }
1335 }
1336
1337 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1338 if (r) {
1339 DRM_ERROR("Failed to init KIQ BOs!\n");
1340 return r;
1341 }
1342
1343 kiq = &adev->gfx.kiq;
1344 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1345 if (r)
1346 return r;
1347
1348 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1349 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
1350 if (r)
1351 return r;
1352
1353 /* reserve GDS, GWS and OA resource for gfx */
1354 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1355 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1356 &adev->gds.gds_gfx_bo, NULL, NULL);
1357 if (r)
1358 return r;
1359
1360 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1361 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1362 &adev->gds.gws_gfx_bo, NULL, NULL);
1363 if (r)
1364 return r;
1365
1366 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1367 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1368 &adev->gds.oa_gfx_bo, NULL, NULL);
1369 if (r)
1370 return r;
1371
1372 adev->gfx.ce_ram_size = 0x8000;
1373
1374 gfx_v9_0_gpu_early_init(adev);
1375
1376 r = gfx_v9_0_ngg_init(adev);
1377 if (r)
1378 return r;
1379
1380 return 0;
1381 }
1382
1383
gfx_v9_0_sw_fini(void * handle)1384 static int gfx_v9_0_sw_fini(void *handle)
1385 {
1386 int i;
1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1388
1389 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1390 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1391 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1392
1393 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1394 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1395 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1396 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1397
1398 amdgpu_gfx_compute_mqd_sw_fini(adev);
1399 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1400 amdgpu_gfx_kiq_fini(adev);
1401
1402 gfx_v9_0_mec_fini(adev);
1403 gfx_v9_0_ngg_fini(adev);
1404
1405 return 0;
1406 }
1407
1408
gfx_v9_0_tiling_mode_table_init(struct amdgpu_device * adev)1409 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1410 {
1411 /* TODO */
1412 }
1413
gfx_v9_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)1414 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1415 {
1416 u32 data;
1417
1418 if (instance == 0xffffffff)
1419 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1420 else
1421 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1422
1423 if (se_num == 0xffffffff)
1424 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1425 else
1426 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1427
1428 if (sh_num == 0xffffffff)
1429 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1430 else
1431 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1432
1433 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1434 }
1435
gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device * adev)1436 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1437 {
1438 u32 data, mask;
1439
1440 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1441 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1442
1443 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1444 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1445
1446 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1447 adev->gfx.config.max_sh_per_se);
1448
1449 return (~data) & mask;
1450 }
1451
gfx_v9_0_setup_rb(struct amdgpu_device * adev)1452 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1453 {
1454 int i, j;
1455 u32 data;
1456 u32 active_rbs = 0;
1457 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1458 adev->gfx.config.max_sh_per_se;
1459
1460 mutex_lock(&adev->grbm_idx_mutex);
1461 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1462 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1463 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1464 data = gfx_v9_0_get_rb_active_bitmap(adev);
1465 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1466 rb_bitmap_width_per_sh);
1467 }
1468 }
1469 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1470 mutex_unlock(&adev->grbm_idx_mutex);
1471
1472 adev->gfx.config.backend_enable_mask = active_rbs;
1473 adev->gfx.config.num_rbs = hweight32(active_rbs);
1474 }
1475
1476 #define DEFAULT_SH_MEM_BASES (0x6000)
1477 #define FIRST_COMPUTE_VMID (8)
1478 #define LAST_COMPUTE_VMID (16)
gfx_v9_0_init_compute_vmid(struct amdgpu_device * adev)1479 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1480 {
1481 int i;
1482 uint32_t sh_mem_config;
1483 uint32_t sh_mem_bases;
1484
1485 /*
1486 * Configure apertures:
1487 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1488 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1489 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1490 */
1491 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1492
1493 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1494 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1495 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1496
1497 mutex_lock(&adev->srbm_mutex);
1498 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1499 soc15_grbm_select(adev, 0, 0, 0, i);
1500 /* CP and shaders */
1501 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1502 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1503 }
1504 soc15_grbm_select(adev, 0, 0, 0, 0);
1505 mutex_unlock(&adev->srbm_mutex);
1506 }
1507
gfx_v9_0_gpu_init(struct amdgpu_device * adev)1508 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1509 {
1510 u32 tmp;
1511 int i;
1512
1513 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1514
1515 gfx_v9_0_tiling_mode_table_init(adev);
1516
1517 gfx_v9_0_setup_rb(adev);
1518 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1519
1520 /* XXX SH_MEM regs */
1521 /* where to put LDS, scratch, GPUVM in FSA64 space */
1522 mutex_lock(&adev->srbm_mutex);
1523 for (i = 0; i < 16; i++) {
1524 soc15_grbm_select(adev, 0, 0, 0, i);
1525 /* CP and shaders */
1526 tmp = 0;
1527 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1528 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1529 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1530 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1531 }
1532 soc15_grbm_select(adev, 0, 0, 0, 0);
1533
1534 mutex_unlock(&adev->srbm_mutex);
1535
1536 gfx_v9_0_init_compute_vmid(adev);
1537 }
1538
gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device * adev)1539 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1540 {
1541 u32 i, j, k;
1542 u32 mask;
1543
1544 mutex_lock(&adev->grbm_idx_mutex);
1545 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1546 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1547 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1548 for (k = 0; k < adev->usec_timeout; k++) {
1549 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1550 break;
1551 udelay(1);
1552 }
1553 }
1554 }
1555 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1556 mutex_unlock(&adev->grbm_idx_mutex);
1557
1558 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1559 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1560 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1561 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1562 for (k = 0; k < adev->usec_timeout; k++) {
1563 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1564 break;
1565 udelay(1);
1566 }
1567 }
1568
gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1569 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1570 bool enable)
1571 {
1572 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1573
1574 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1575 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1576 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1577 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1578
1579 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1580 }
1581
gfx_v9_0_init_csb(struct amdgpu_device * adev)1582 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1583 {
1584 /* csib */
1585 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1586 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1587 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1588 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1589 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1590 adev->gfx.rlc.clear_state_size);
1591 }
1592
gfx_v9_0_parse_ind_reg_list(int * register_list_format,int indirect_offset,int list_size,int * unique_indirect_regs,int * unique_indirect_reg_count,int max_indirect_reg_count,int * indirect_start_offsets,int * indirect_start_offsets_count,int max_indirect_start_offsets_count)1593 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1594 int indirect_offset,
1595 int list_size,
1596 int *unique_indirect_regs,
1597 int *unique_indirect_reg_count,
1598 int max_indirect_reg_count,
1599 int *indirect_start_offsets,
1600 int *indirect_start_offsets_count,
1601 int max_indirect_start_offsets_count)
1602 {
1603 int idx;
1604 bool new_entry = true;
1605
1606 for (; indirect_offset < list_size; indirect_offset++) {
1607
1608 if (new_entry) {
1609 new_entry = false;
1610 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1611 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1612 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1613 }
1614
1615 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1616 new_entry = true;
1617 continue;
1618 }
1619
1620 indirect_offset += 2;
1621
1622 /* look for the matching indice */
1623 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1624 if (unique_indirect_regs[idx] ==
1625 register_list_format[indirect_offset])
1626 break;
1627 }
1628
1629 if (idx >= *unique_indirect_reg_count) {
1630 unique_indirect_regs[*unique_indirect_reg_count] =
1631 register_list_format[indirect_offset];
1632 idx = *unique_indirect_reg_count;
1633 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1634 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1635 }
1636
1637 register_list_format[indirect_offset] = idx;
1638 }
1639 }
1640
gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device * adev)1641 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1642 {
1643 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1644 int unique_indirect_reg_count = 0;
1645
1646 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1647 int indirect_start_offsets_count = 0;
1648
1649 int list_size = 0;
1650 int i = 0;
1651 u32 tmp = 0;
1652
1653 u32 *register_list_format =
1654 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1655 if (!register_list_format)
1656 return -ENOMEM;
1657 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1658 adev->gfx.rlc.reg_list_format_size_bytes);
1659
1660 /* setup unique_indirect_regs array and indirect_start_offsets array */
1661 gfx_v9_0_parse_ind_reg_list(register_list_format,
1662 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1663 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1664 unique_indirect_regs,
1665 &unique_indirect_reg_count,
1666 sizeof(unique_indirect_regs)/sizeof(int),
1667 indirect_start_offsets,
1668 &indirect_start_offsets_count,
1669 sizeof(indirect_start_offsets)/sizeof(int));
1670
1671 /* enable auto inc in case it is disabled */
1672 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1673 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1674 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1675
1676 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1677 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1678 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1679 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1680 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1681 adev->gfx.rlc.register_restore[i]);
1682
1683 /* load direct register */
1684 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1685 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1686 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1687 adev->gfx.rlc.register_restore[i]);
1688
1689 /* load indirect register */
1690 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1691 adev->gfx.rlc.reg_list_format_start);
1692 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1693 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1694 register_list_format[i]);
1695
1696 /* set save/restore list size */
1697 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1698 list_size = list_size >> 1;
1699 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1700 adev->gfx.rlc.reg_restore_list_size);
1701 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1702
1703 /* write the starting offsets to RLC scratch ram */
1704 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1705 adev->gfx.rlc.starting_offsets_start);
1706 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1707 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1708 indirect_start_offsets[i]);
1709
1710 /* load unique indirect regs*/
1711 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1712 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1713 unique_indirect_regs[i] & 0x3FFFF);
1714 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1715 unique_indirect_regs[i] >> 20);
1716 }
1717
1718 kfree(register_list_format);
1719 return 0;
1720 }
1721
gfx_v9_0_enable_save_restore_machine(struct amdgpu_device * adev)1722 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1723 {
1724 u32 tmp = 0;
1725
1726 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1727 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1728 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1729 }
1730
pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device * adev,bool enable)1731 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1732 bool enable)
1733 {
1734 uint32_t data = 0;
1735 uint32_t default_data = 0;
1736
1737 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1738 if (enable == true) {
1739 /* enable GFXIP control over CGPG */
1740 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1741 if(default_data != data)
1742 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1743
1744 /* update status */
1745 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1746 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1747 if(default_data != data)
1748 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1749 } else {
1750 /* restore GFXIP control over GCPG */
1751 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1752 if(default_data != data)
1753 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1754 }
1755 }
1756
gfx_v9_0_init_gfx_power_gating(struct amdgpu_device * adev)1757 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1758 {
1759 uint32_t data = 0;
1760
1761 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1762 AMD_PG_SUPPORT_GFX_SMG |
1763 AMD_PG_SUPPORT_GFX_DMG)) {
1764 /* init IDLE_POLL_COUNT = 60 */
1765 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1766 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1767 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1768 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1769
1770 /* init RLC PG Delay */
1771 data = 0;
1772 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1773 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1774 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1775 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1776 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1777
1778 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1779 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1780 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1782
1783 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1784 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1785 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1786 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1787
1788 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1789 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1790
1791 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1792 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1794
1795 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1796 }
1797 }
1798
gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device * adev,bool enable)1799 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1800 bool enable)
1801 {
1802 uint32_t data = 0;
1803 uint32_t default_data = 0;
1804
1805 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1806
1807 if (enable == true) {
1808 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1809 if (default_data != data)
1810 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1811 } else {
1812 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1813 if(default_data != data)
1814 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1815 }
1816 }
1817
gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device * adev,bool enable)1818 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1819 bool enable)
1820 {
1821 uint32_t data = 0;
1822 uint32_t default_data = 0;
1823
1824 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1825
1826 if (enable == true) {
1827 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1828 if(default_data != data)
1829 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1830 } else {
1831 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1832 if(default_data != data)
1833 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1834 }
1835 }
1836
gfx_v9_0_enable_cp_power_gating(struct amdgpu_device * adev,bool enable)1837 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1838 bool enable)
1839 {
1840 uint32_t data = 0;
1841 uint32_t default_data = 0;
1842
1843 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1844
1845 if (enable == true) {
1846 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1847 if(default_data != data)
1848 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1849 } else {
1850 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1851 if(default_data != data)
1852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1853 }
1854 }
1855
gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)1856 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1857 bool enable)
1858 {
1859 uint32_t data, default_data;
1860
1861 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1862 if (enable == true)
1863 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1864 else
1865 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1866 if(default_data != data)
1867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1868 }
1869
gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device * adev,bool enable)1870 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1871 bool enable)
1872 {
1873 uint32_t data, default_data;
1874
1875 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1876 if (enable == true)
1877 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1878 else
1879 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1880 if(default_data != data)
1881 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1882
1883 if (!enable)
1884 /* read any GFX register to wake up GFX */
1885 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1886 }
1887
gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device * adev,bool enable)1888 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1889 bool enable)
1890 {
1891 uint32_t data, default_data;
1892
1893 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1894 if (enable == true)
1895 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1896 else
1897 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1898 if(default_data != data)
1899 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1900 }
1901
gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device * adev,bool enable)1902 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
1903 bool enable)
1904 {
1905 uint32_t data, default_data;
1906
1907 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1908 if (enable == true)
1909 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1910 else
1911 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1912 if(default_data != data)
1913 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1914 }
1915
gfx_v9_0_init_pg(struct amdgpu_device * adev)1916 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1917 {
1918 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1919 AMD_PG_SUPPORT_GFX_SMG |
1920 AMD_PG_SUPPORT_GFX_DMG |
1921 AMD_PG_SUPPORT_CP |
1922 AMD_PG_SUPPORT_GDS |
1923 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1924 gfx_v9_0_init_csb(adev);
1925 gfx_v9_0_init_rlc_save_restore_list(adev);
1926 gfx_v9_0_enable_save_restore_machine(adev);
1927
1928 if (adev->asic_type == CHIP_RAVEN) {
1929 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1930 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1931 gfx_v9_0_init_gfx_power_gating(adev);
1932
1933 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1934 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1935 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1936 } else {
1937 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1938 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1939 }
1940
1941 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1942 gfx_v9_0_enable_cp_power_gating(adev, true);
1943 else
1944 gfx_v9_0_enable_cp_power_gating(adev, false);
1945 }
1946 }
1947 }
1948
gfx_v9_0_rlc_stop(struct amdgpu_device * adev)1949 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1950 {
1951 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1952
1953 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1954 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1955
1956 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1957
1958 gfx_v9_0_wait_for_rlc_serdes(adev);
1959 }
1960
gfx_v9_0_rlc_reset(struct amdgpu_device * adev)1961 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1962 {
1963 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1964 udelay(50);
1965 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1966 udelay(50);
1967 }
1968
gfx_v9_0_rlc_start(struct amdgpu_device * adev)1969 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1970 {
1971 #ifdef AMDGPU_RLC_DEBUG_RETRY
1972 u32 rlc_ucode_ver;
1973 #endif
1974
1975 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1976 udelay(50);
1977
1978 /* carrizo do enable cp interrupt after cp inited */
1979 if (!(adev->flags & AMD_IS_APU)) {
1980 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1981 udelay(50);
1982 }
1983
1984 #ifdef AMDGPU_RLC_DEBUG_RETRY
1985 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1986 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
1987 if(rlc_ucode_ver == 0x108) {
1988 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1989 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1990 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1991 * default is 0x9C4 to create a 100us interval */
1992 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
1993 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1994 * to disable the page fault retry interrupts, default is
1995 * 0x100 (256) */
1996 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
1997 }
1998 #endif
1999 }
2000
gfx_v9_0_rlc_load_microcode(struct amdgpu_device * adev)2001 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2002 {
2003 const struct rlc_firmware_header_v2_0 *hdr;
2004 const __le32 *fw_data;
2005 unsigned i, fw_size;
2006
2007 if (!adev->gfx.rlc_fw)
2008 return -EINVAL;
2009
2010 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2011 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2012
2013 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2014 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2015 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2016
2017 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2018 RLCG_UCODE_LOADING_START_ADDRESS);
2019 for (i = 0; i < fw_size; i++)
2020 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2021 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2022
2023 return 0;
2024 }
2025
gfx_v9_0_rlc_resume(struct amdgpu_device * adev)2026 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2027 {
2028 int r;
2029
2030 if (amdgpu_sriov_vf(adev))
2031 return 0;
2032
2033 gfx_v9_0_rlc_stop(adev);
2034
2035 /* disable CG */
2036 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2037
2038 /* disable PG */
2039 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2040
2041 gfx_v9_0_rlc_reset(adev);
2042
2043 gfx_v9_0_init_pg(adev);
2044
2045 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2046 /* legacy rlc firmware loading */
2047 r = gfx_v9_0_rlc_load_microcode(adev);
2048 if (r)
2049 return r;
2050 }
2051
2052 if (adev->asic_type == CHIP_RAVEN) {
2053 if (amdgpu_lbpw != 0)
2054 gfx_v9_0_enable_lbpw(adev, true);
2055 else
2056 gfx_v9_0_enable_lbpw(adev, false);
2057 }
2058
2059 gfx_v9_0_rlc_start(adev);
2060
2061 return 0;
2062 }
2063
gfx_v9_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2064 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2065 {
2066 int i;
2067 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2068
2069 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2070 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2071 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2072 if (!enable) {
2073 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2074 adev->gfx.gfx_ring[i].ready = false;
2075 }
2076 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2077 udelay(50);
2078 }
2079
gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2080 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2081 {
2082 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2083 const struct gfx_firmware_header_v1_0 *ce_hdr;
2084 const struct gfx_firmware_header_v1_0 *me_hdr;
2085 const __le32 *fw_data;
2086 unsigned i, fw_size;
2087
2088 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2089 return -EINVAL;
2090
2091 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2092 adev->gfx.pfp_fw->data;
2093 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2094 adev->gfx.ce_fw->data;
2095 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2096 adev->gfx.me_fw->data;
2097
2098 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2099 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2100 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2101
2102 gfx_v9_0_cp_gfx_enable(adev, false);
2103
2104 /* PFP */
2105 fw_data = (const __le32 *)
2106 (adev->gfx.pfp_fw->data +
2107 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2108 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2109 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2110 for (i = 0; i < fw_size; i++)
2111 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2112 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2113
2114 /* CE */
2115 fw_data = (const __le32 *)
2116 (adev->gfx.ce_fw->data +
2117 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2118 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2119 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2120 for (i = 0; i < fw_size; i++)
2121 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2122 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2123
2124 /* ME */
2125 fw_data = (const __le32 *)
2126 (adev->gfx.me_fw->data +
2127 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2128 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2129 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2130 for (i = 0; i < fw_size; i++)
2131 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2132 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2133
2134 return 0;
2135 }
2136
gfx_v9_0_cp_gfx_start(struct amdgpu_device * adev)2137 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2138 {
2139 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2140 const struct cs_section_def *sect = NULL;
2141 const struct cs_extent_def *ext = NULL;
2142 int r, i, tmp;
2143
2144 /* init the CP */
2145 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2146 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2147
2148 gfx_v9_0_cp_gfx_enable(adev, true);
2149
2150 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2151 if (r) {
2152 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2153 return r;
2154 }
2155
2156 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2157 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2158
2159 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2160 amdgpu_ring_write(ring, 0x80000000);
2161 amdgpu_ring_write(ring, 0x80000000);
2162
2163 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2164 for (ext = sect->section; ext->extent != NULL; ++ext) {
2165 if (sect->id == SECT_CONTEXT) {
2166 amdgpu_ring_write(ring,
2167 PACKET3(PACKET3_SET_CONTEXT_REG,
2168 ext->reg_count));
2169 amdgpu_ring_write(ring,
2170 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2171 for (i = 0; i < ext->reg_count; i++)
2172 amdgpu_ring_write(ring, ext->extent[i]);
2173 }
2174 }
2175 }
2176
2177 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2178 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2179
2180 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2181 amdgpu_ring_write(ring, 0);
2182
2183 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2184 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2185 amdgpu_ring_write(ring, 0x8000);
2186 amdgpu_ring_write(ring, 0x8000);
2187
2188 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2189 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2190 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2191 amdgpu_ring_write(ring, tmp);
2192 amdgpu_ring_write(ring, 0);
2193
2194 amdgpu_ring_commit(ring);
2195
2196 return 0;
2197 }
2198
gfx_v9_0_cp_gfx_resume(struct amdgpu_device * adev)2199 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2200 {
2201 struct amdgpu_ring *ring;
2202 u32 tmp;
2203 u32 rb_bufsz;
2204 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2205
2206 /* Set the write pointer delay */
2207 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2208
2209 /* set the RB to use vmid 0 */
2210 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2211
2212 /* Set ring buffer size */
2213 ring = &adev->gfx.gfx_ring[0];
2214 rb_bufsz = order_base_2(ring->ring_size / 8);
2215 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2216 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2217 #ifdef __BIG_ENDIAN
2218 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2219 #endif
2220 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2221
2222 /* Initialize the ring buffer's write pointers */
2223 ring->wptr = 0;
2224 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2225 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2226
2227 /* set the wb address wether it's enabled or not */
2228 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2229 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2230 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2231
2232 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2233 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2234 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2235
2236 mdelay(1);
2237 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2238
2239 rb_addr = ring->gpu_addr >> 8;
2240 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2241 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2242
2243 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2244 if (ring->use_doorbell) {
2245 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2246 DOORBELL_OFFSET, ring->doorbell_index);
2247 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2248 DOORBELL_EN, 1);
2249 } else {
2250 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2251 }
2252 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2253
2254 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2255 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2256 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2257
2258 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2259 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2260
2261
2262 /* start the ring */
2263 gfx_v9_0_cp_gfx_start(adev);
2264 ring->ready = true;
2265
2266 return 0;
2267 }
2268
gfx_v9_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2269 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2270 {
2271 int i;
2272
2273 if (enable) {
2274 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2275 } else {
2276 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2277 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2278 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2279 adev->gfx.compute_ring[i].ready = false;
2280 adev->gfx.kiq.ring.ready = false;
2281 }
2282 udelay(50);
2283 }
2284
gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device * adev)2285 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2286 {
2287 const struct gfx_firmware_header_v1_0 *mec_hdr;
2288 const __le32 *fw_data;
2289 unsigned i;
2290 u32 tmp;
2291
2292 if (!adev->gfx.mec_fw)
2293 return -EINVAL;
2294
2295 gfx_v9_0_cp_compute_enable(adev, false);
2296
2297 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2298 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2299
2300 fw_data = (const __le32 *)
2301 (adev->gfx.mec_fw->data +
2302 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2303 tmp = 0;
2304 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2305 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2306 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2307
2308 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2309 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2310 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2311 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2312
2313 /* MEC1 */
2314 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2315 mec_hdr->jt_offset);
2316 for (i = 0; i < mec_hdr->jt_size; i++)
2317 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2318 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2319
2320 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2321 adev->gfx.mec_fw_version);
2322 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2323
2324 return 0;
2325 }
2326
2327 /* KIQ functions */
gfx_v9_0_kiq_setting(struct amdgpu_ring * ring)2328 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2329 {
2330 uint32_t tmp;
2331 struct amdgpu_device *adev = ring->adev;
2332
2333 /* tell RLC which is KIQ queue */
2334 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2335 tmp &= 0xffffff00;
2336 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2337 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2338 tmp |= 0x80;
2339 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2340 }
2341
gfx_v9_0_kiq_kcq_enable(struct amdgpu_device * adev)2342 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2343 {
2344 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2345 uint32_t scratch, tmp = 0;
2346 uint64_t queue_mask = 0;
2347 int r, i;
2348
2349 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2350 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2351 continue;
2352
2353 /* This situation may be hit in the future if a new HW
2354 * generation exposes more than 64 queues. If so, the
2355 * definition of queue_mask needs updating */
2356 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2357 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2358 break;
2359 }
2360
2361 queue_mask |= (1ull << i);
2362 }
2363
2364 r = amdgpu_gfx_scratch_get(adev, &scratch);
2365 if (r) {
2366 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2367 return r;
2368 }
2369 WREG32(scratch, 0xCAFEDEAD);
2370
2371 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2372 if (r) {
2373 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2374 amdgpu_gfx_scratch_free(adev, scratch);
2375 return r;
2376 }
2377
2378 /* set resources */
2379 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2380 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2381 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2382 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2383 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2384 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2385 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2386 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2387 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2388 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2389 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2390 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2391 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2392
2393 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2394 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2395 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2396 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2397 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2398 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2399 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2400 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2401 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2402 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2403 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2404 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2405 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2406 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2407 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2408 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2409 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2410 }
2411 /* write to scratch for completion */
2412 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2413 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2414 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2415 amdgpu_ring_commit(kiq_ring);
2416
2417 for (i = 0; i < adev->usec_timeout; i++) {
2418 tmp = RREG32(scratch);
2419 if (tmp == 0xDEADBEEF)
2420 break;
2421 DRM_UDELAY(1);
2422 }
2423 if (i >= adev->usec_timeout) {
2424 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2425 scratch, tmp);
2426 r = -EINVAL;
2427 }
2428 amdgpu_gfx_scratch_free(adev, scratch);
2429
2430 return r;
2431 }
2432
gfx_v9_0_mqd_init(struct amdgpu_ring * ring)2433 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2434 {
2435 struct amdgpu_device *adev = ring->adev;
2436 struct v9_mqd *mqd = ring->mqd_ptr;
2437 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2438 uint32_t tmp;
2439
2440 mqd->header = 0xC0310800;
2441 mqd->compute_pipelinestat_enable = 0x00000001;
2442 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2443 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2444 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2445 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2446 mqd->compute_misc_reserved = 0x00000003;
2447
2448 eop_base_addr = ring->eop_gpu_addr >> 8;
2449 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2450 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2451
2452 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2453 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2454 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2455 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2456
2457 mqd->cp_hqd_eop_control = tmp;
2458
2459 /* enable doorbell? */
2460 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2461
2462 if (ring->use_doorbell) {
2463 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2464 DOORBELL_OFFSET, ring->doorbell_index);
2465 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2466 DOORBELL_EN, 1);
2467 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2468 DOORBELL_SOURCE, 0);
2469 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2470 DOORBELL_HIT, 0);
2471 }
2472 else
2473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2474 DOORBELL_EN, 0);
2475
2476 mqd->cp_hqd_pq_doorbell_control = tmp;
2477
2478 /* disable the queue if it's active */
2479 ring->wptr = 0;
2480 mqd->cp_hqd_dequeue_request = 0;
2481 mqd->cp_hqd_pq_rptr = 0;
2482 mqd->cp_hqd_pq_wptr_lo = 0;
2483 mqd->cp_hqd_pq_wptr_hi = 0;
2484
2485 /* set the pointer to the MQD */
2486 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2487 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2488
2489 /* set MQD vmid to 0 */
2490 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2491 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2492 mqd->cp_mqd_control = tmp;
2493
2494 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2495 hqd_gpu_addr = ring->gpu_addr >> 8;
2496 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2497 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2498
2499 /* set up the HQD, this is similar to CP_RB0_CNTL */
2500 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2502 (order_base_2(ring->ring_size / 4) - 1));
2503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2504 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2505 #ifdef __BIG_ENDIAN
2506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2507 #endif
2508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2509 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2512 mqd->cp_hqd_pq_control = tmp;
2513
2514 /* set the wb address whether it's enabled or not */
2515 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2516 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2517 mqd->cp_hqd_pq_rptr_report_addr_hi =
2518 upper_32_bits(wb_gpu_addr) & 0xffff;
2519
2520 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2521 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2522 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2523 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2524
2525 tmp = 0;
2526 /* enable the doorbell if requested */
2527 if (ring->use_doorbell) {
2528 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2530 DOORBELL_OFFSET, ring->doorbell_index);
2531
2532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2533 DOORBELL_EN, 1);
2534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2535 DOORBELL_SOURCE, 0);
2536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2537 DOORBELL_HIT, 0);
2538 }
2539
2540 mqd->cp_hqd_pq_doorbell_control = tmp;
2541
2542 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2543 ring->wptr = 0;
2544 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2545
2546 /* set the vmid for the queue */
2547 mqd->cp_hqd_vmid = 0;
2548
2549 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2550 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2551 mqd->cp_hqd_persistent_state = tmp;
2552
2553 /* set MIN_IB_AVAIL_SIZE */
2554 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2555 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2556 mqd->cp_hqd_ib_control = tmp;
2557
2558 /* activate the queue */
2559 mqd->cp_hqd_active = 1;
2560
2561 return 0;
2562 }
2563
gfx_v9_0_kiq_init_register(struct amdgpu_ring * ring)2564 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2565 {
2566 struct amdgpu_device *adev = ring->adev;
2567 struct v9_mqd *mqd = ring->mqd_ptr;
2568 int j;
2569
2570 /* disable wptr polling */
2571 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2572
2573 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2574 mqd->cp_hqd_eop_base_addr_lo);
2575 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2576 mqd->cp_hqd_eop_base_addr_hi);
2577
2578 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2579 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2580 mqd->cp_hqd_eop_control);
2581
2582 /* enable doorbell? */
2583 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2584 mqd->cp_hqd_pq_doorbell_control);
2585
2586 /* disable the queue if it's active */
2587 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2588 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2589 for (j = 0; j < adev->usec_timeout; j++) {
2590 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2591 break;
2592 udelay(1);
2593 }
2594 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2595 mqd->cp_hqd_dequeue_request);
2596 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2597 mqd->cp_hqd_pq_rptr);
2598 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2599 mqd->cp_hqd_pq_wptr_lo);
2600 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2601 mqd->cp_hqd_pq_wptr_hi);
2602 }
2603
2604 /* set the pointer to the MQD */
2605 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2606 mqd->cp_mqd_base_addr_lo);
2607 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2608 mqd->cp_mqd_base_addr_hi);
2609
2610 /* set MQD vmid to 0 */
2611 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2612 mqd->cp_mqd_control);
2613
2614 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2615 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2616 mqd->cp_hqd_pq_base_lo);
2617 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2618 mqd->cp_hqd_pq_base_hi);
2619
2620 /* set up the HQD, this is similar to CP_RB0_CNTL */
2621 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2622 mqd->cp_hqd_pq_control);
2623
2624 /* set the wb address whether it's enabled or not */
2625 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2626 mqd->cp_hqd_pq_rptr_report_addr_lo);
2627 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2628 mqd->cp_hqd_pq_rptr_report_addr_hi);
2629
2630 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2631 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2632 mqd->cp_hqd_pq_wptr_poll_addr_lo);
2633 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2634 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2635
2636 /* enable the doorbell if requested */
2637 if (ring->use_doorbell) {
2638 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2639 (AMDGPU_DOORBELL64_KIQ *2) << 2);
2640 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2641 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2642 }
2643
2644 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2645 mqd->cp_hqd_pq_doorbell_control);
2646
2647 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2648 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2649 mqd->cp_hqd_pq_wptr_lo);
2650 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2651 mqd->cp_hqd_pq_wptr_hi);
2652
2653 /* set the vmid for the queue */
2654 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2655
2656 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2657 mqd->cp_hqd_persistent_state);
2658
2659 /* activate the queue */
2660 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2661 mqd->cp_hqd_active);
2662
2663 if (ring->use_doorbell)
2664 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2665
2666 return 0;
2667 }
2668
gfx_v9_0_kiq_init_queue(struct amdgpu_ring * ring)2669 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2670 {
2671 struct amdgpu_device *adev = ring->adev;
2672 struct v9_mqd *mqd = ring->mqd_ptr;
2673 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2674
2675 gfx_v9_0_kiq_setting(ring);
2676
2677 if (adev->gfx.in_reset) { /* for GPU_RESET case */
2678 /* reset MQD to a clean status */
2679 if (adev->gfx.mec.mqd_backup[mqd_idx])
2680 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2681
2682 /* reset ring buffer */
2683 ring->wptr = 0;
2684 amdgpu_ring_clear_ring(ring);
2685
2686 mutex_lock(&adev->srbm_mutex);
2687 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2688 gfx_v9_0_kiq_init_register(ring);
2689 soc15_grbm_select(adev, 0, 0, 0, 0);
2690 mutex_unlock(&adev->srbm_mutex);
2691 } else {
2692 memset((void *)mqd, 0, sizeof(*mqd));
2693 mutex_lock(&adev->srbm_mutex);
2694 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2695 gfx_v9_0_mqd_init(ring);
2696 gfx_v9_0_kiq_init_register(ring);
2697 soc15_grbm_select(adev, 0, 0, 0, 0);
2698 mutex_unlock(&adev->srbm_mutex);
2699
2700 if (adev->gfx.mec.mqd_backup[mqd_idx])
2701 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
2702 }
2703
2704 return 0;
2705 }
2706
gfx_v9_0_kcq_init_queue(struct amdgpu_ring * ring)2707 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2708 {
2709 struct amdgpu_device *adev = ring->adev;
2710 struct v9_mqd *mqd = ring->mqd_ptr;
2711 int mqd_idx = ring - &adev->gfx.compute_ring[0];
2712
2713 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
2714 memset((void *)mqd, 0, sizeof(*mqd));
2715 mutex_lock(&adev->srbm_mutex);
2716 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2717 gfx_v9_0_mqd_init(ring);
2718 soc15_grbm_select(adev, 0, 0, 0, 0);
2719 mutex_unlock(&adev->srbm_mutex);
2720
2721 if (adev->gfx.mec.mqd_backup[mqd_idx])
2722 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
2723 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
2724 /* reset MQD to a clean status */
2725 if (adev->gfx.mec.mqd_backup[mqd_idx])
2726 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2727
2728 /* reset ring buffer */
2729 ring->wptr = 0;
2730 amdgpu_ring_clear_ring(ring);
2731 } else {
2732 amdgpu_ring_clear_ring(ring);
2733 }
2734
2735 return 0;
2736 }
2737
gfx_v9_0_kiq_resume(struct amdgpu_device * adev)2738 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2739 {
2740 struct amdgpu_ring *ring = NULL;
2741 int r = 0, i;
2742
2743 gfx_v9_0_cp_compute_enable(adev, true);
2744
2745 ring = &adev->gfx.kiq.ring;
2746
2747 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2748 if (unlikely(r != 0))
2749 goto done;
2750
2751 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2752 if (!r) {
2753 r = gfx_v9_0_kiq_init_queue(ring);
2754 amdgpu_bo_kunmap(ring->mqd_obj);
2755 ring->mqd_ptr = NULL;
2756 }
2757 amdgpu_bo_unreserve(ring->mqd_obj);
2758 if (r)
2759 goto done;
2760
2761 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2762 ring = &adev->gfx.compute_ring[i];
2763
2764 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2765 if (unlikely(r != 0))
2766 goto done;
2767 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2768 if (!r) {
2769 r = gfx_v9_0_kcq_init_queue(ring);
2770 amdgpu_bo_kunmap(ring->mqd_obj);
2771 ring->mqd_ptr = NULL;
2772 }
2773 amdgpu_bo_unreserve(ring->mqd_obj);
2774 if (r)
2775 goto done;
2776 }
2777
2778 r = gfx_v9_0_kiq_kcq_enable(adev);
2779 done:
2780 return r;
2781 }
2782
gfx_v9_0_cp_resume(struct amdgpu_device * adev)2783 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2784 {
2785 int r, i;
2786 struct amdgpu_ring *ring;
2787
2788 if (!(adev->flags & AMD_IS_APU))
2789 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2790
2791 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2792 /* legacy firmware loading */
2793 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2794 if (r)
2795 return r;
2796
2797 r = gfx_v9_0_cp_compute_load_microcode(adev);
2798 if (r)
2799 return r;
2800 }
2801
2802 r = gfx_v9_0_cp_gfx_resume(adev);
2803 if (r)
2804 return r;
2805
2806 r = gfx_v9_0_kiq_resume(adev);
2807 if (r)
2808 return r;
2809
2810 ring = &adev->gfx.gfx_ring[0];
2811 r = amdgpu_ring_test_ring(ring);
2812 if (r) {
2813 ring->ready = false;
2814 return r;
2815 }
2816
2817 ring = &adev->gfx.kiq.ring;
2818 ring->ready = true;
2819 r = amdgpu_ring_test_ring(ring);
2820 if (r)
2821 ring->ready = false;
2822
2823 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2824 ring = &adev->gfx.compute_ring[i];
2825
2826 ring->ready = true;
2827 r = amdgpu_ring_test_ring(ring);
2828 if (r)
2829 ring->ready = false;
2830 }
2831
2832 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2833
2834 return 0;
2835 }
2836
gfx_v9_0_cp_enable(struct amdgpu_device * adev,bool enable)2837 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2838 {
2839 gfx_v9_0_cp_gfx_enable(adev, enable);
2840 gfx_v9_0_cp_compute_enable(adev, enable);
2841 }
2842
gfx_v9_0_hw_init(void * handle)2843 static int gfx_v9_0_hw_init(void *handle)
2844 {
2845 int r;
2846 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2847
2848 gfx_v9_0_init_golden_registers(adev);
2849
2850 gfx_v9_0_gpu_init(adev);
2851
2852 r = gfx_v9_0_rlc_resume(adev);
2853 if (r)
2854 return r;
2855
2856 r = gfx_v9_0_cp_resume(adev);
2857 if (r)
2858 return r;
2859
2860 r = gfx_v9_0_ngg_en(adev);
2861 if (r)
2862 return r;
2863
2864 return r;
2865 }
2866
gfx_v9_0_hw_fini(void * handle)2867 static int gfx_v9_0_hw_fini(void *handle)
2868 {
2869 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2870
2871 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2872 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2873 if (amdgpu_sriov_vf(adev)) {
2874 gfx_v9_0_cp_gfx_enable(adev, false);
2875 /* must disable polling for SRIOV when hw finished, otherwise
2876 * CPC engine may still keep fetching WB address which is already
2877 * invalid after sw finished and trigger DMAR reading error in
2878 * hypervisor side.
2879 */
2880 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2881 return 0;
2882 }
2883 gfx_v9_0_cp_enable(adev, false);
2884 gfx_v9_0_rlc_stop(adev);
2885
2886 return 0;
2887 }
2888
gfx_v9_0_suspend(void * handle)2889 static int gfx_v9_0_suspend(void *handle)
2890 {
2891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2892
2893 adev->gfx.in_suspend = true;
2894 return gfx_v9_0_hw_fini(adev);
2895 }
2896
gfx_v9_0_resume(void * handle)2897 static int gfx_v9_0_resume(void *handle)
2898 {
2899 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2900 int r;
2901
2902 r = gfx_v9_0_hw_init(adev);
2903 adev->gfx.in_suspend = false;
2904 return r;
2905 }
2906
gfx_v9_0_is_idle(void * handle)2907 static bool gfx_v9_0_is_idle(void *handle)
2908 {
2909 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2910
2911 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
2912 GRBM_STATUS, GUI_ACTIVE))
2913 return false;
2914 else
2915 return true;
2916 }
2917
gfx_v9_0_wait_for_idle(void * handle)2918 static int gfx_v9_0_wait_for_idle(void *handle)
2919 {
2920 unsigned i;
2921 u32 tmp;
2922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2923
2924 for (i = 0; i < adev->usec_timeout; i++) {
2925 /* read MC_STATUS */
2926 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
2927 GRBM_STATUS__GUI_ACTIVE_MASK;
2928
2929 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2930 return 0;
2931 udelay(1);
2932 }
2933 return -ETIMEDOUT;
2934 }
2935
gfx_v9_0_soft_reset(void * handle)2936 static int gfx_v9_0_soft_reset(void *handle)
2937 {
2938 u32 grbm_soft_reset = 0;
2939 u32 tmp;
2940 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2941
2942 /* GRBM_STATUS */
2943 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
2944 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2945 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2946 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2947 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2948 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2949 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2950 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2951 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2952 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2953 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2954 }
2955
2956 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2957 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2958 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2959 }
2960
2961 /* GRBM_STATUS2 */
2962 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
2963 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2964 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2965 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2966
2967
2968 if (grbm_soft_reset) {
2969 /* stop the rlc */
2970 gfx_v9_0_rlc_stop(adev);
2971
2972 /* Disable GFX parsing/prefetching */
2973 gfx_v9_0_cp_gfx_enable(adev, false);
2974
2975 /* Disable MEC parsing/prefetching */
2976 gfx_v9_0_cp_compute_enable(adev, false);
2977
2978 if (grbm_soft_reset) {
2979 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2980 tmp |= grbm_soft_reset;
2981 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2982 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2983 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2984
2985 udelay(50);
2986
2987 tmp &= ~grbm_soft_reset;
2988 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2989 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
2990 }
2991
2992 /* Wait a little for things to settle down */
2993 udelay(50);
2994 }
2995 return 0;
2996 }
2997
gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device * adev)2998 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2999 {
3000 uint64_t clock;
3001
3002 mutex_lock(&adev->gfx.gpu_clock_mutex);
3003 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3004 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3005 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3006 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3007 return clock;
3008 }
3009
gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)3010 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3011 uint32_t vmid,
3012 uint32_t gds_base, uint32_t gds_size,
3013 uint32_t gws_base, uint32_t gws_size,
3014 uint32_t oa_base, uint32_t oa_size)
3015 {
3016 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3017 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3018
3019 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3020 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3021
3022 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3023 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3024
3025 /* GDS Base */
3026 gfx_v9_0_write_data_to_reg(ring, 0, false,
3027 amdgpu_gds_reg_offset[vmid].mem_base,
3028 gds_base);
3029
3030 /* GDS Size */
3031 gfx_v9_0_write_data_to_reg(ring, 0, false,
3032 amdgpu_gds_reg_offset[vmid].mem_size,
3033 gds_size);
3034
3035 /* GWS */
3036 gfx_v9_0_write_data_to_reg(ring, 0, false,
3037 amdgpu_gds_reg_offset[vmid].gws,
3038 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3039
3040 /* OA */
3041 gfx_v9_0_write_data_to_reg(ring, 0, false,
3042 amdgpu_gds_reg_offset[vmid].oa,
3043 (1 << (oa_size + oa_base)) - (1 << oa_base));
3044 }
3045
gfx_v9_0_early_init(void * handle)3046 static int gfx_v9_0_early_init(void *handle)
3047 {
3048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3049
3050 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3051 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3052 gfx_v9_0_set_ring_funcs(adev);
3053 gfx_v9_0_set_irq_funcs(adev);
3054 gfx_v9_0_set_gds_init(adev);
3055 gfx_v9_0_set_rlc_funcs(adev);
3056
3057 return 0;
3058 }
3059
gfx_v9_0_late_init(void * handle)3060 static int gfx_v9_0_late_init(void *handle)
3061 {
3062 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063 int r;
3064
3065 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3066 if (r)
3067 return r;
3068
3069 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3070 if (r)
3071 return r;
3072
3073 return 0;
3074 }
3075
gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device * adev)3076 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3077 {
3078 uint32_t rlc_setting, data;
3079 unsigned i;
3080
3081 if (adev->gfx.rlc.in_safe_mode)
3082 return;
3083
3084 /* if RLC is not enabled, do nothing */
3085 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3086 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3087 return;
3088
3089 if (adev->cg_flags &
3090 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3091 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3092 data = RLC_SAFE_MODE__CMD_MASK;
3093 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3094 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3095
3096 /* wait for RLC_SAFE_MODE */
3097 for (i = 0; i < adev->usec_timeout; i++) {
3098 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3099 break;
3100 udelay(1);
3101 }
3102 adev->gfx.rlc.in_safe_mode = true;
3103 }
3104 }
3105
gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device * adev)3106 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3107 {
3108 uint32_t rlc_setting, data;
3109
3110 if (!adev->gfx.rlc.in_safe_mode)
3111 return;
3112
3113 /* if RLC is not enabled, do nothing */
3114 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3115 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3116 return;
3117
3118 if (adev->cg_flags &
3119 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3120 /*
3121 * Try to exit safe mode only if it is already in safe
3122 * mode.
3123 */
3124 data = RLC_SAFE_MODE__CMD_MASK;
3125 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3126 adev->gfx.rlc.in_safe_mode = false;
3127 }
3128 }
3129
gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)3130 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3131 bool enable)
3132 {
3133 /* TODO: double check if we need to perform under safe mdoe */
3134 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3135
3136 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3137 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3138 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3139 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3140 } else {
3141 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3142 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3143 }
3144
3145 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3146 }
3147
gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device * adev,bool enable)3148 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3149 bool enable)
3150 {
3151 /* TODO: double check if we need to perform under safe mode */
3152 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3153
3154 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3155 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3156 else
3157 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3158
3159 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3160 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3161 else
3162 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3163
3164 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3165 }
3166
gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)3167 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3168 bool enable)
3169 {
3170 uint32_t data, def;
3171
3172 /* It is disabled by HW by default */
3173 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3174 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3175 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3176 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3177 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3178 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3179 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3180
3181 /* only for Vega10 & Raven1 */
3182 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3183
3184 if (def != data)
3185 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3186
3187 /* MGLS is a global flag to control all MGLS in GFX */
3188 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3189 /* 2 - RLC memory Light sleep */
3190 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3191 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3192 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3193 if (def != data)
3194 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3195 }
3196 /* 3 - CP memory Light sleep */
3197 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3198 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3199 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3200 if (def != data)
3201 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3202 }
3203 }
3204 } else {
3205 /* 1 - MGCG_OVERRIDE */
3206 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3207 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3208 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3209 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3210 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3211 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3212 if (def != data)
3213 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3214
3215 /* 2 - disable MGLS in RLC */
3216 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3217 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3218 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3219 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3220 }
3221
3222 /* 3 - disable MGLS in CP */
3223 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3224 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3225 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3226 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3227 }
3228 }
3229 }
3230
gfx_v9_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)3231 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3232 bool enable)
3233 {
3234 uint32_t data, def;
3235
3236 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3237
3238 /* Enable 3D CGCG/CGLS */
3239 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3240 /* write cmd to clear cgcg/cgls ov */
3241 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3242 /* unset CGCG override */
3243 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3244 /* update CGCG and CGLS override bits */
3245 if (def != data)
3246 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3247 /* enable 3Dcgcg FSM(0x0020003f) */
3248 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3249 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3250 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3251 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3252 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3253 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3254 if (def != data)
3255 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3256
3257 /* set IDLE_POLL_COUNT(0x00900100) */
3258 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3259 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3260 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3261 if (def != data)
3262 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3263 } else {
3264 /* Disable CGCG/CGLS */
3265 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3266 /* disable cgcg, cgls should be disabled */
3267 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3268 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3269 /* disable cgcg and cgls in FSM */
3270 if (def != data)
3271 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3272 }
3273
3274 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3275 }
3276
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)3277 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3278 bool enable)
3279 {
3280 uint32_t def, data;
3281
3282 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3283
3284 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3285 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3286 /* unset CGCG override */
3287 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3288 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3289 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3290 else
3291 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3292 /* update CGCG and CGLS override bits */
3293 if (def != data)
3294 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3295
3296 /* enable cgcg FSM(0x0020003F) */
3297 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3298 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3299 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3300 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3301 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3302 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3303 if (def != data)
3304 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3305
3306 /* set IDLE_POLL_COUNT(0x00900100) */
3307 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3308 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3309 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3310 if (def != data)
3311 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3312 } else {
3313 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3314 /* reset CGCG/CGLS bits */
3315 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3316 /* disable cgcg and cgls in FSM */
3317 if (def != data)
3318 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3319 }
3320
3321 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3322 }
3323
gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)3324 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3325 bool enable)
3326 {
3327 if (enable) {
3328 /* CGCG/CGLS should be enabled after MGCG/MGLS
3329 * === MGCG + MGLS ===
3330 */
3331 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3332 /* === CGCG /CGLS for GFX 3D Only === */
3333 gfx_v9_0_update_3d_clock_gating(adev, enable);
3334 /* === CGCG + CGLS === */
3335 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3336 } else {
3337 /* CGCG/CGLS should be disabled before MGCG/MGLS
3338 * === CGCG + CGLS ===
3339 */
3340 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3341 /* === CGCG /CGLS for GFX 3D Only === */
3342 gfx_v9_0_update_3d_clock_gating(adev, enable);
3343 /* === MGCG + MGLS === */
3344 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3345 }
3346 return 0;
3347 }
3348
3349 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3350 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3351 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3352 };
3353
gfx_v9_0_set_powergating_state(void * handle,enum amd_powergating_state state)3354 static int gfx_v9_0_set_powergating_state(void *handle,
3355 enum amd_powergating_state state)
3356 {
3357 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3358 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3359
3360 switch (adev->asic_type) {
3361 case CHIP_RAVEN:
3362 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3363 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3364 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3365 } else {
3366 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3367 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3368 }
3369
3370 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3371 gfx_v9_0_enable_cp_power_gating(adev, true);
3372 else
3373 gfx_v9_0_enable_cp_power_gating(adev, false);
3374
3375 /* update gfx cgpg state */
3376 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3377
3378 /* update mgcg state */
3379 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3380 break;
3381 default:
3382 break;
3383 }
3384
3385 return 0;
3386 }
3387
gfx_v9_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3388 static int gfx_v9_0_set_clockgating_state(void *handle,
3389 enum amd_clockgating_state state)
3390 {
3391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3392
3393 if (amdgpu_sriov_vf(adev))
3394 return 0;
3395
3396 switch (adev->asic_type) {
3397 case CHIP_VEGA10:
3398 case CHIP_RAVEN:
3399 gfx_v9_0_update_gfx_clock_gating(adev,
3400 state == AMD_CG_STATE_GATE ? true : false);
3401 break;
3402 default:
3403 break;
3404 }
3405 return 0;
3406 }
3407
gfx_v9_0_get_clockgating_state(void * handle,u32 * flags)3408 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3409 {
3410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3411 int data;
3412
3413 if (amdgpu_sriov_vf(adev))
3414 *flags = 0;
3415
3416 /* AMD_CG_SUPPORT_GFX_MGCG */
3417 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3418 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3419 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3420
3421 /* AMD_CG_SUPPORT_GFX_CGCG */
3422 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3423 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3424 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3425
3426 /* AMD_CG_SUPPORT_GFX_CGLS */
3427 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3428 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3429
3430 /* AMD_CG_SUPPORT_GFX_RLC_LS */
3431 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3432 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3433 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3434
3435 /* AMD_CG_SUPPORT_GFX_CP_LS */
3436 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3437 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3438 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3439
3440 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3441 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3442 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3443 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3444
3445 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3446 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3447 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3448 }
3449
gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)3450 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3451 {
3452 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3453 }
3454
gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)3455 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3456 {
3457 struct amdgpu_device *adev = ring->adev;
3458 u64 wptr;
3459
3460 /* XXX check if swapping is necessary on BE */
3461 if (ring->use_doorbell) {
3462 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3463 } else {
3464 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3465 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3466 }
3467
3468 return wptr;
3469 }
3470
gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)3471 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3472 {
3473 struct amdgpu_device *adev = ring->adev;
3474
3475 if (ring->use_doorbell) {
3476 /* XXX check if swapping is necessary on BE */
3477 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3478 WDOORBELL64(ring->doorbell_index, ring->wptr);
3479 } else {
3480 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3481 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3482 }
3483 }
3484
gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)3485 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3486 {
3487 u32 ref_and_mask, reg_mem_engine;
3488 struct nbio_hdp_flush_reg *nbio_hf_reg;
3489
3490 if (ring->adev->asic_type == CHIP_VEGA10)
3491 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3492
3493 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3494 switch (ring->me) {
3495 case 1:
3496 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3497 break;
3498 case 2:
3499 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3500 break;
3501 default:
3502 return;
3503 }
3504 reg_mem_engine = 0;
3505 } else {
3506 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3507 reg_mem_engine = 1; /* pfp */
3508 }
3509
3510 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3511 nbio_hf_reg->hdp_flush_req_offset,
3512 nbio_hf_reg->hdp_flush_done_offset,
3513 ref_and_mask, ref_and_mask, 0x20);
3514 }
3515
gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring * ring)3516 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3517 {
3518 gfx_v9_0_write_data_to_reg(ring, 0, true,
3519 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3520 }
3521
gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned vm_id,bool ctx_switch)3522 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3523 struct amdgpu_ib *ib,
3524 unsigned vm_id, bool ctx_switch)
3525 {
3526 u32 header, control = 0;
3527
3528 if (ib->flags & AMDGPU_IB_FLAG_CE)
3529 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3530 else
3531 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3532
3533 control |= ib->length_dw | (vm_id << 24);
3534
3535 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3536 control |= INDIRECT_BUFFER_PRE_ENB(1);
3537
3538 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3539 gfx_v9_0_ring_emit_de_meta(ring);
3540 }
3541
3542 amdgpu_ring_write(ring, header);
3543 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3544 amdgpu_ring_write(ring,
3545 #ifdef __BIG_ENDIAN
3546 (2 << 0) |
3547 #endif
3548 lower_32_bits(ib->gpu_addr));
3549 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3550 amdgpu_ring_write(ring, control);
3551 }
3552
gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned vm_id,bool ctx_switch)3553 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3554 struct amdgpu_ib *ib,
3555 unsigned vm_id, bool ctx_switch)
3556 {
3557 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3558
3559 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3560 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3561 amdgpu_ring_write(ring,
3562 #ifdef __BIG_ENDIAN
3563 (2 << 0) |
3564 #endif
3565 lower_32_bits(ib->gpu_addr));
3566 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3567 amdgpu_ring_write(ring, control);
3568 }
3569
gfx_v9_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)3570 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3571 u64 seq, unsigned flags)
3572 {
3573 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3574 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3575
3576 /* RELEASE_MEM - flush caches, send int */
3577 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3578 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3579 EOP_TC_ACTION_EN |
3580 EOP_TC_WB_ACTION_EN |
3581 EOP_TC_MD_ACTION_EN |
3582 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3583 EVENT_INDEX(5)));
3584 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3585
3586 /*
3587 * the address should be Qword aligned if 64bit write, Dword
3588 * aligned if only send 32bit data low (discard data high)
3589 */
3590 if (write64bit)
3591 BUG_ON(addr & 0x7);
3592 else
3593 BUG_ON(addr & 0x3);
3594 amdgpu_ring_write(ring, lower_32_bits(addr));
3595 amdgpu_ring_write(ring, upper_32_bits(addr));
3596 amdgpu_ring_write(ring, lower_32_bits(seq));
3597 amdgpu_ring_write(ring, upper_32_bits(seq));
3598 amdgpu_ring_write(ring, 0);
3599 }
3600
gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)3601 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3602 {
3603 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3604 uint32_t seq = ring->fence_drv.sync_seq;
3605 uint64_t addr = ring->fence_drv.gpu_addr;
3606
3607 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3608 lower_32_bits(addr), upper_32_bits(addr),
3609 seq, 0xffffffff, 4);
3610 }
3611
gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vm_id,uint64_t pd_addr)3612 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3613 unsigned vm_id, uint64_t pd_addr)
3614 {
3615 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
3616 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3617 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
3618 unsigned eng = ring->vm_inv_eng;
3619
3620 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3621 pd_addr |= AMDGPU_PTE_VALID;
3622
3623 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3624 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3625 lower_32_bits(pd_addr));
3626
3627 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3628 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3629 upper_32_bits(pd_addr));
3630
3631 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3632 hub->vm_inv_eng0_req + eng, req);
3633
3634 /* wait for the invalidate to complete */
3635 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3636 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
3637
3638 /* compute doesn't have PFP */
3639 if (usepfp) {
3640 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3641 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3642 amdgpu_ring_write(ring, 0x0);
3643 }
3644 }
3645
gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring * ring)3646 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3647 {
3648 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3649 }
3650
gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring * ring)3651 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3652 {
3653 u64 wptr;
3654
3655 /* XXX check if swapping is necessary on BE */
3656 if (ring->use_doorbell)
3657 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3658 else
3659 BUG();
3660 return wptr;
3661 }
3662
gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring * ring)3663 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3664 {
3665 struct amdgpu_device *adev = ring->adev;
3666
3667 /* XXX check if swapping is necessary on BE */
3668 if (ring->use_doorbell) {
3669 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3670 WDOORBELL64(ring->doorbell_index, ring->wptr);
3671 } else{
3672 BUG(); /* only DOORBELL method supported on gfx9 now */
3673 }
3674 }
3675
gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)3676 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3677 u64 seq, unsigned int flags)
3678 {
3679 /* we only allocate 32bit for each seq wb address */
3680 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3681
3682 /* write fence seq to the "addr" */
3683 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3684 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3685 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3686 amdgpu_ring_write(ring, lower_32_bits(addr));
3687 amdgpu_ring_write(ring, upper_32_bits(addr));
3688 amdgpu_ring_write(ring, lower_32_bits(seq));
3689
3690 if (flags & AMDGPU_FENCE_FLAG_INT) {
3691 /* set register to trigger INT */
3692 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3693 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3694 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3695 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3696 amdgpu_ring_write(ring, 0);
3697 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3698 }
3699 }
3700
gfx_v9_ring_emit_sb(struct amdgpu_ring * ring)3701 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3702 {
3703 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3704 amdgpu_ring_write(ring, 0);
3705 }
3706
gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring * ring)3707 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3708 {
3709 static struct v9_ce_ib_state ce_payload = {0};
3710 uint64_t csa_addr;
3711 int cnt;
3712
3713 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3714 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3715
3716 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3717 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3718 WRITE_DATA_DST_SEL(8) |
3719 WR_CONFIRM) |
3720 WRITE_DATA_CACHE_POLICY(0));
3721 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3722 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3723 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3724 }
3725
gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring * ring)3726 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3727 {
3728 static struct v9_de_ib_state de_payload = {0};
3729 uint64_t csa_addr, gds_addr;
3730 int cnt;
3731
3732 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3733 gds_addr = csa_addr + 4096;
3734 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3735 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3736
3737 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3738 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3739 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3740 WRITE_DATA_DST_SEL(8) |
3741 WR_CONFIRM) |
3742 WRITE_DATA_CACHE_POLICY(0));
3743 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3744 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3745 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3746 }
3747
gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)3748 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3749 {
3750 uint32_t dw2 = 0;
3751
3752 if (amdgpu_sriov_vf(ring->adev))
3753 gfx_v9_0_ring_emit_ce_meta(ring);
3754
3755 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3756 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3757 /* set load_global_config & load_global_uconfig */
3758 dw2 |= 0x8001;
3759 /* set load_cs_sh_regs */
3760 dw2 |= 0x01000000;
3761 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3762 dw2 |= 0x10002;
3763
3764 /* set load_ce_ram if preamble presented */
3765 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3766 dw2 |= 0x10000000;
3767 } else {
3768 /* still load_ce_ram if this is the first time preamble presented
3769 * although there is no context switch happens.
3770 */
3771 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3772 dw2 |= 0x10000000;
3773 }
3774
3775 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3776 amdgpu_ring_write(ring, dw2);
3777 amdgpu_ring_write(ring, 0);
3778 }
3779
gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)3780 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3781 {
3782 unsigned ret;
3783 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3784 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3785 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3786 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3787 ret = ring->wptr & ring->buf_mask;
3788 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3789 return ret;
3790 }
3791
gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)3792 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3793 {
3794 unsigned cur;
3795 BUG_ON(offset > ring->buf_mask);
3796 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3797
3798 cur = (ring->wptr & ring->buf_mask) - 1;
3799 if (likely(cur > offset))
3800 ring->ring[offset] = cur - offset;
3801 else
3802 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3803 }
3804
gfx_v9_0_ring_emit_tmz(struct amdgpu_ring * ring,bool start)3805 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3806 {
3807 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3808 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3809 }
3810
gfx_v9_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg)3811 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3812 {
3813 struct amdgpu_device *adev = ring->adev;
3814
3815 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3816 amdgpu_ring_write(ring, 0 | /* src: register*/
3817 (5 << 8) | /* dst: memory */
3818 (1 << 20)); /* write confirm */
3819 amdgpu_ring_write(ring, reg);
3820 amdgpu_ring_write(ring, 0);
3821 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3822 adev->virt.reg_val_offs * 4));
3823 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3824 adev->virt.reg_val_offs * 4));
3825 }
3826
gfx_v9_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)3827 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3828 uint32_t val)
3829 {
3830 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3831 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3832 amdgpu_ring_write(ring, reg);
3833 amdgpu_ring_write(ring, 0);
3834 amdgpu_ring_write(ring, val);
3835 }
3836
gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)3837 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3838 enum amdgpu_interrupt_state state)
3839 {
3840 switch (state) {
3841 case AMDGPU_IRQ_STATE_DISABLE:
3842 case AMDGPU_IRQ_STATE_ENABLE:
3843 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3844 TIME_STAMP_INT_ENABLE,
3845 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3846 break;
3847 default:
3848 break;
3849 }
3850 }
3851
gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)3852 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3853 int me, int pipe,
3854 enum amdgpu_interrupt_state state)
3855 {
3856 u32 mec_int_cntl, mec_int_cntl_reg;
3857
3858 /*
3859 * amdgpu controls only the first MEC. That's why this function only
3860 * handles the setting of interrupts for this specific MEC. All other
3861 * pipes' interrupts are set by amdkfd.
3862 */
3863
3864 if (me == 1) {
3865 switch (pipe) {
3866 case 0:
3867 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3868 break;
3869 case 1:
3870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3871 break;
3872 case 2:
3873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3874 break;
3875 case 3:
3876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3877 break;
3878 default:
3879 DRM_DEBUG("invalid pipe %d\n", pipe);
3880 return;
3881 }
3882 } else {
3883 DRM_DEBUG("invalid me %d\n", me);
3884 return;
3885 }
3886
3887 switch (state) {
3888 case AMDGPU_IRQ_STATE_DISABLE:
3889 mec_int_cntl = RREG32(mec_int_cntl_reg);
3890 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3891 TIME_STAMP_INT_ENABLE, 0);
3892 WREG32(mec_int_cntl_reg, mec_int_cntl);
3893 break;
3894 case AMDGPU_IRQ_STATE_ENABLE:
3895 mec_int_cntl = RREG32(mec_int_cntl_reg);
3896 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3897 TIME_STAMP_INT_ENABLE, 1);
3898 WREG32(mec_int_cntl_reg, mec_int_cntl);
3899 break;
3900 default:
3901 break;
3902 }
3903 }
3904
gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)3905 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3906 struct amdgpu_irq_src *source,
3907 unsigned type,
3908 enum amdgpu_interrupt_state state)
3909 {
3910 switch (state) {
3911 case AMDGPU_IRQ_STATE_DISABLE:
3912 case AMDGPU_IRQ_STATE_ENABLE:
3913 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3914 PRIV_REG_INT_ENABLE,
3915 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3916 break;
3917 default:
3918 break;
3919 }
3920
3921 return 0;
3922 }
3923
gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)3924 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3925 struct amdgpu_irq_src *source,
3926 unsigned type,
3927 enum amdgpu_interrupt_state state)
3928 {
3929 switch (state) {
3930 case AMDGPU_IRQ_STATE_DISABLE:
3931 case AMDGPU_IRQ_STATE_ENABLE:
3932 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3933 PRIV_INSTR_INT_ENABLE,
3934 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
3935 default:
3936 break;
3937 }
3938
3939 return 0;
3940 }
3941
gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3942 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3943 struct amdgpu_irq_src *src,
3944 unsigned type,
3945 enum amdgpu_interrupt_state state)
3946 {
3947 switch (type) {
3948 case AMDGPU_CP_IRQ_GFX_EOP:
3949 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3950 break;
3951 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3952 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3953 break;
3954 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3955 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3956 break;
3957 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3958 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3959 break;
3960 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3961 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3962 break;
3963 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3964 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3965 break;
3966 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3967 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3968 break;
3969 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3970 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3971 break;
3972 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3973 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3974 break;
3975 default:
3976 break;
3977 }
3978 return 0;
3979 }
3980
gfx_v9_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3981 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3982 struct amdgpu_irq_src *source,
3983 struct amdgpu_iv_entry *entry)
3984 {
3985 int i;
3986 u8 me_id, pipe_id, queue_id;
3987 struct amdgpu_ring *ring;
3988
3989 DRM_DEBUG("IH: CP EOP\n");
3990 me_id = (entry->ring_id & 0x0c) >> 2;
3991 pipe_id = (entry->ring_id & 0x03) >> 0;
3992 queue_id = (entry->ring_id & 0x70) >> 4;
3993
3994 switch (me_id) {
3995 case 0:
3996 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3997 break;
3998 case 1:
3999 case 2:
4000 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4001 ring = &adev->gfx.compute_ring[i];
4002 /* Per-queue interrupt is supported for MEC starting from VI.
4003 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4004 */
4005 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4006 amdgpu_fence_process(ring);
4007 }
4008 break;
4009 }
4010 return 0;
4011 }
4012
gfx_v9_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4013 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4014 struct amdgpu_irq_src *source,
4015 struct amdgpu_iv_entry *entry)
4016 {
4017 DRM_ERROR("Illegal register access in command stream\n");
4018 schedule_work(&adev->reset_work);
4019 return 0;
4020 }
4021
gfx_v9_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4022 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4023 struct amdgpu_irq_src *source,
4024 struct amdgpu_iv_entry *entry)
4025 {
4026 DRM_ERROR("Illegal instruction in command stream\n");
4027 schedule_work(&adev->reset_work);
4028 return 0;
4029 }
4030
gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)4031 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4032 struct amdgpu_irq_src *src,
4033 unsigned int type,
4034 enum amdgpu_interrupt_state state)
4035 {
4036 uint32_t tmp, target;
4037 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4038
4039 if (ring->me == 1)
4040 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4041 else
4042 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4043 target += ring->pipe;
4044
4045 switch (type) {
4046 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4047 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4048 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4049 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4050 GENERIC2_INT_ENABLE, 0);
4051 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4052
4053 tmp = RREG32(target);
4054 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4055 GENERIC2_INT_ENABLE, 0);
4056 WREG32(target, tmp);
4057 } else {
4058 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4059 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4060 GENERIC2_INT_ENABLE, 1);
4061 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4062
4063 tmp = RREG32(target);
4064 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4065 GENERIC2_INT_ENABLE, 1);
4066 WREG32(target, tmp);
4067 }
4068 break;
4069 default:
4070 BUG(); /* kiq only support GENERIC2_INT now */
4071 break;
4072 }
4073 return 0;
4074 }
4075
gfx_v9_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4076 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4077 struct amdgpu_irq_src *source,
4078 struct amdgpu_iv_entry *entry)
4079 {
4080 u8 me_id, pipe_id, queue_id;
4081 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4082
4083 me_id = (entry->ring_id & 0x0c) >> 2;
4084 pipe_id = (entry->ring_id & 0x03) >> 0;
4085 queue_id = (entry->ring_id & 0x70) >> 4;
4086 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4087 me_id, pipe_id, queue_id);
4088
4089 amdgpu_fence_process(ring);
4090 return 0;
4091 }
4092
4093 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4094 .name = "gfx_v9_0",
4095 .early_init = gfx_v9_0_early_init,
4096 .late_init = gfx_v9_0_late_init,
4097 .sw_init = gfx_v9_0_sw_init,
4098 .sw_fini = gfx_v9_0_sw_fini,
4099 .hw_init = gfx_v9_0_hw_init,
4100 .hw_fini = gfx_v9_0_hw_fini,
4101 .suspend = gfx_v9_0_suspend,
4102 .resume = gfx_v9_0_resume,
4103 .is_idle = gfx_v9_0_is_idle,
4104 .wait_for_idle = gfx_v9_0_wait_for_idle,
4105 .soft_reset = gfx_v9_0_soft_reset,
4106 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4107 .set_powergating_state = gfx_v9_0_set_powergating_state,
4108 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4109 };
4110
4111 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4112 .type = AMDGPU_RING_TYPE_GFX,
4113 .align_mask = 0xff,
4114 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4115 .support_64bit_ptrs = true,
4116 .vmhub = AMDGPU_GFXHUB,
4117 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4118 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4119 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4120 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4121 5 + /* COND_EXEC */
4122 7 + /* PIPELINE_SYNC */
4123 24 + /* VM_FLUSH */
4124 8 + /* FENCE for VM_FLUSH */
4125 20 + /* GDS switch */
4126 4 + /* double SWITCH_BUFFER,
4127 the first COND_EXEC jump to the place just
4128 prior to this double SWITCH_BUFFER */
4129 5 + /* COND_EXEC */
4130 7 + /* HDP_flush */
4131 4 + /* VGT_flush */
4132 14 + /* CE_META */
4133 31 + /* DE_META */
4134 3 + /* CNTX_CTRL */
4135 5 + /* HDP_INVL */
4136 8 + 8 + /* FENCE x2 */
4137 2, /* SWITCH_BUFFER */
4138 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4139 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4140 .emit_fence = gfx_v9_0_ring_emit_fence,
4141 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4142 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4143 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4144 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4145 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4146 .test_ring = gfx_v9_0_ring_test_ring,
4147 .test_ib = gfx_v9_0_ring_test_ib,
4148 .insert_nop = amdgpu_ring_insert_nop,
4149 .pad_ib = amdgpu_ring_generic_pad_ib,
4150 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4151 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4152 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4153 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4154 .emit_tmz = gfx_v9_0_ring_emit_tmz,
4155 };
4156
4157 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4158 .type = AMDGPU_RING_TYPE_COMPUTE,
4159 .align_mask = 0xff,
4160 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4161 .support_64bit_ptrs = true,
4162 .vmhub = AMDGPU_GFXHUB,
4163 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4164 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4165 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4166 .emit_frame_size =
4167 20 + /* gfx_v9_0_ring_emit_gds_switch */
4168 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4169 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4170 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4171 24 + /* gfx_v9_0_ring_emit_vm_flush */
4172 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4173 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4174 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4175 .emit_fence = gfx_v9_0_ring_emit_fence,
4176 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4177 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4178 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4179 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4180 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4181 .test_ring = gfx_v9_0_ring_test_ring,
4182 .test_ib = gfx_v9_0_ring_test_ib,
4183 .insert_nop = amdgpu_ring_insert_nop,
4184 .pad_ib = amdgpu_ring_generic_pad_ib,
4185 };
4186
4187 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4188 .type = AMDGPU_RING_TYPE_KIQ,
4189 .align_mask = 0xff,
4190 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4191 .support_64bit_ptrs = true,
4192 .vmhub = AMDGPU_GFXHUB,
4193 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4194 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4195 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4196 .emit_frame_size =
4197 20 + /* gfx_v9_0_ring_emit_gds_switch */
4198 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4199 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4200 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4201 24 + /* gfx_v9_0_ring_emit_vm_flush */
4202 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4203 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4204 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4205 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4206 .test_ring = gfx_v9_0_ring_test_ring,
4207 .test_ib = gfx_v9_0_ring_test_ib,
4208 .insert_nop = amdgpu_ring_insert_nop,
4209 .pad_ib = amdgpu_ring_generic_pad_ib,
4210 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4211 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4212 };
4213
gfx_v9_0_set_ring_funcs(struct amdgpu_device * adev)4214 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4215 {
4216 int i;
4217
4218 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4219
4220 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4221 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4222
4223 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4224 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4225 }
4226
4227 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4228 .set = gfx_v9_0_kiq_set_interrupt_state,
4229 .process = gfx_v9_0_kiq_irq,
4230 };
4231
4232 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4233 .set = gfx_v9_0_set_eop_interrupt_state,
4234 .process = gfx_v9_0_eop_irq,
4235 };
4236
4237 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4238 .set = gfx_v9_0_set_priv_reg_fault_state,
4239 .process = gfx_v9_0_priv_reg_irq,
4240 };
4241
4242 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4243 .set = gfx_v9_0_set_priv_inst_fault_state,
4244 .process = gfx_v9_0_priv_inst_irq,
4245 };
4246
gfx_v9_0_set_irq_funcs(struct amdgpu_device * adev)4247 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4248 {
4249 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4250 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4251
4252 adev->gfx.priv_reg_irq.num_types = 1;
4253 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4254
4255 adev->gfx.priv_inst_irq.num_types = 1;
4256 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4257
4258 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4259 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4260 }
4261
gfx_v9_0_set_rlc_funcs(struct amdgpu_device * adev)4262 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4263 {
4264 switch (adev->asic_type) {
4265 case CHIP_VEGA10:
4266 case CHIP_RAVEN:
4267 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4268 break;
4269 default:
4270 break;
4271 }
4272 }
4273
gfx_v9_0_set_gds_init(struct amdgpu_device * adev)4274 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4275 {
4276 /* init asci gds info */
4277 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4278 adev->gds.gws.total_size = 64;
4279 adev->gds.oa.total_size = 16;
4280
4281 if (adev->gds.mem.total_size == 64 * 1024) {
4282 adev->gds.mem.gfx_partition_size = 4096;
4283 adev->gds.mem.cs_partition_size = 4096;
4284
4285 adev->gds.gws.gfx_partition_size = 4;
4286 adev->gds.gws.cs_partition_size = 4;
4287
4288 adev->gds.oa.gfx_partition_size = 4;
4289 adev->gds.oa.cs_partition_size = 1;
4290 } else {
4291 adev->gds.mem.gfx_partition_size = 1024;
4292 adev->gds.mem.cs_partition_size = 1024;
4293
4294 adev->gds.gws.gfx_partition_size = 16;
4295 adev->gds.gws.cs_partition_size = 16;
4296
4297 adev->gds.oa.gfx_partition_size = 4;
4298 adev->gds.oa.cs_partition_size = 4;
4299 }
4300 }
4301
gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)4302 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4303 u32 bitmap)
4304 {
4305 u32 data;
4306
4307 if (!bitmap)
4308 return;
4309
4310 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4311 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4312
4313 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4314 }
4315
gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device * adev)4316 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4317 {
4318 u32 data, mask;
4319
4320 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4321 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4322
4323 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4324 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4325
4326 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4327
4328 return (~data) & mask;
4329 }
4330
gfx_v9_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)4331 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4332 struct amdgpu_cu_info *cu_info)
4333 {
4334 int i, j, k, counter, active_cu_number = 0;
4335 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4336 unsigned disable_masks[4 * 2];
4337
4338 if (!adev || !cu_info)
4339 return -EINVAL;
4340
4341 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4342
4343 mutex_lock(&adev->grbm_idx_mutex);
4344 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4345 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4346 mask = 1;
4347 ao_bitmap = 0;
4348 counter = 0;
4349 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4350 if (i < 4 && j < 2)
4351 gfx_v9_0_set_user_cu_inactive_bitmap(
4352 adev, disable_masks[i * 2 + j]);
4353 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4354 cu_info->bitmap[i][j] = bitmap;
4355
4356 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4357 if (bitmap & mask) {
4358 if (counter < adev->gfx.config.max_cu_per_sh)
4359 ao_bitmap |= mask;
4360 counter ++;
4361 }
4362 mask <<= 1;
4363 }
4364 active_cu_number += counter;
4365 if (i < 2 && j < 2)
4366 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4367 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4368 }
4369 }
4370 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4371 mutex_unlock(&adev->grbm_idx_mutex);
4372
4373 cu_info->number = active_cu_number;
4374 cu_info->ao_cu_mask = ao_cu_mask;
4375
4376 return 0;
4377 }
4378
4379 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4380 {
4381 .type = AMD_IP_BLOCK_TYPE_GFX,
4382 .major = 9,
4383 .minor = 0,
4384 .rev = 0,
4385 .funcs = &gfx_v9_0_ip_funcs,
4386 };
4387