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Searched refs:INT_SEL (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsoc15d.h171 #define INT_SEL(x) ((x) << 24) macro
Dvid.h256 #define INT_SEL(x) ((x) << 24) macro
Dcikd.h376 #define INT_SEL(x) ((x) << 24) macro
Dsid.h1832 #define INT_SEL(x) ((x) << 24) macro
Dgfx_v7_0.c2176 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()
2188 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2215 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
Dgfx_v8_0.c6238 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6336 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
Dgfx_v9_0.c3584 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
/drivers/staging/emxx_udc/
Demxx_udc.h102 #define INT_SEL BIT10 macro
Demxx_udc.c2277 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); in _nbu2ss_enable_controller()
/drivers/gpu/drm/radeon/
Dnid.h1255 #define INT_SEL(x) ((x) << 24) macro
Dsid.h1769 #define INT_SEL(x) ((x) << 24) macro
Dcikd.h1844 #define INT_SEL(x) ((x) << 24) macro
Dr600d.h1680 #define INT_SEL(x) ((x) << 24) macro
Dni.c1416 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
Dcik.c3581 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()
3592 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3618 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
Dr600.c2882 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
Dsi.c3392 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()