Home
last modified time | relevance | path

Searched refs:MAX_PHASE (Results 1 – 6 of 6) sorted by relevance

/drivers/mmc/host/
Drtsx_usb_sdmmc.c624 idx &= MAX_PHASE; in get_phase_point()
632 for (i = 0; i < MAX_PHASE + 1; i++) { in get_phase_len()
636 return MAX_PHASE + 1; in get_phase_len()
650 while (start < MAX_PHASE + 1) { in sd_search_final_phase()
659 final_phase = (start_final + len_final / 2) & MAX_PHASE; in sd_search_final_phase()
709 for (i = MAX_PHASE; i >= 0; i--) { in sd_tuning_phase()
/drivers/usb/host/
Duhci-q.c615 for (phase += period; phase < MAX_PHASE; phase += period) in uhci_highest_load()
634 int max_phase = min_t(int, MAX_PHASE, qh->period); in uhci_check_bandwidth()
666 for (i = qh->phase; i < MAX_PHASE; i += qh->period) { in uhci_reserve_bandwidth()
671 uhci->total_load / MAX_PHASE; in uhci_reserve_bandwidth()
699 for (i = qh->phase; i < MAX_PHASE; i += qh->period) { in uhci_release_bandwidth()
704 uhci->total_load / MAX_PHASE; in uhci_release_bandwidth()
1103 qh->phase = (qh->period / 2) & (MAX_PHASE - 1); in uhci_submit_interrupt()
Duhci-hcd.h94 #define MAX_PHASE 32 /* Periodic scheduling length */ macro
448 short load[MAX_PHASE]; /* Periodic allocations */
Duhci-debug.c399 for (i = 0; i < MAX_PHASE; ++i) { in uhci_sprint_schedule()
/drivers/staging/rts5208/
Dsd.h227 #define MAX_PHASE 31 macro
Dsd.c1804 struct timing_phase_path path[MAX_PHASE + 1];
1822 for (i = 0; i < MAX_PHASE + 1; i++) {
1856 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1857 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1861 path[0].mid += MAX_PHASE + 1;
1894 MAX_PHASE + 1);
1907 MAX_PHASE + 1);
1945 for (j = MAX_PHASE; j >= 0; j--) {
1996 for (i = MAX_PHASE; i >= 0; i--) {
2071 for (j = MAX_PHASE; j >= 0; j--) {