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Searched refs:RCS (Results 1 – 25 of 33) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
Drender.c49 {RCS, _MMIO(0x229c), 0xffff, false},
50 {RCS, _MMIO(0x2248), 0x0, false},
51 {RCS, _MMIO(0x2098), 0x0, false},
52 {RCS, _MMIO(0x20c0), 0xffff, true},
53 {RCS, _MMIO(0x24d0), 0, false},
54 {RCS, _MMIO(0x24d4), 0, false},
55 {RCS, _MMIO(0x24d8), 0, false},
56 {RCS, _MMIO(0x24dc), 0, false},
57 {RCS, _MMIO(0x24e0), 0, false},
58 {RCS, _MMIO(0x24e4), 0, false},
[all …]
Dscheduler.c76 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) in populate_shadow_context()
108 if (ring_id == RCS) { in populate_shadow_context()
249 if ((workload->ring_id == RCS) && in intel_gvt_scan_and_shadow_workload()
397 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) in update_guest_context()
679 vgpu->shadow_ctx->engine[RCS].initialised = true; in intel_vgpu_init_gvt_context()
Dexeclist.c52 [RCS] = RCS_AS_CONTEXT_SWITCH,
61 if (WARN_ON(ring_id < RCS || in ring_id_to_context_switch_event()
691 if (ring_id == RCS) { in submit_context()
Dcmd_parser.c393 #define R_RCS (1 << RCS)
559 [RCS] = {
891 (s->ring_id != RCS)) { in cmd_handler_lri()
979 [RCS] = {
/drivers/gpu/drm/i915/
Di915_gem_context.c470 dev_priv->engine[RCS]->context_size ? "logical" : in i915_gem_contexts_init()
620 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags; in mi_set_context()
692 if (!to->engine[RCS].initialised) in skip_rcs_switch()
718 if (engine->id != RCS) in needs_pd_load_pre()
753 GEM_BUG_ON(engine->id != RCS); in do_rcs_switch()
769 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) in do_rcs_switch()
817 if (!to->engine[RCS].initialised) { in do_rcs_switch()
823 to->engine[RCS].initialised = true; in do_rcs_switch()
951 if (!dev_priv->engine[RCS]->context_size) in i915_gem_context_create_ioctl()
Dintel_engine_cs.c84 [RCS] = {
272 if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) { in intel_engines_init_mmio()
602 if (engine->id != RCS) in intel_engine_get_instdone()
618 if (engine->id != RCS) in intel_engine_get_instdone()
631 if (engine->id == RCS) in intel_engine_get_instdone()
1181 WARN_ON(engine->id != RCS); in init_workarounds_ring()
Di915_gem_render_state.c183 if (engine->id != RCS) in i915_gem_render_state_init()
Di915_guc_submission.c1068 dev_priv->engine[RCS]->status_page.ggtt_offset; in guc_ads_create()
1313 data[2] = guc_ggtt_offset(ctx->engine[RCS].state); in intel_guc_suspend()
1339 data[2] = guc_ggtt_offset(ctx->engine[RCS].state); in intel_guc_resume()
Dintel_mocs.c210 case RCS: in mocs_register()
Dintel_hangcheck.c205 if (engine->id != RCS) in subunits_stuck()
Di915_perf.c1219 struct intel_engine_cs *engine = dev_priv->engine[RCS]; in oa_get_render_ctx_id()
1265 struct intel_engine_cs *engine = dev_priv->engine[RCS]; in oa_put_render_ctx_id()
1692 struct intel_engine_cs *engine = dev_priv->engine[RCS]; in gen8_switch_to_updated_kernel_context()
1788 struct intel_context *ce = &ctx->engine[RCS]; in gen8_configure_all_contexts()
2161 if (engine->id != RCS) in i915_oa_init_reg_state()
Dintel_ringbuffer.c405 case RCS: in intel_ring_setup_status_page()
877 if (ppgtt && req->engine->id != RCS) in gen8_ring_sync_to()
1272 GEM_BUG_ON(engine->id != RCS); in init_phys_status_page()
1438 struct i915_vma *vma = ctx->engine[RCS].state; in context_pin()
Di915_gem_execbuffer.c1896 if (!IS_GEN7(req->i915) || req->engine->id != RCS) { in i915_reset_gen7_sol_offsets()
2065 [I915_EXEC_DEFAULT] = RCS,
2066 [I915_EXEC_RENDER] = RCS,
2308 if (eb.engine->id != RCS) { in i915_gem_do_execbuffer()
Dintel_lrc.c1198 if (WARN_ON(engine->id != RCS || !engine->scratch)) in intel_init_workaround_bb()
1249 [RCS] = 0,
1951 bool rcs = engine->id == RCS; in execlists_init_reg_state()
Di915_irq.c1281 notify_ring(dev_priv->engine[RCS]); in ilk_gt_irq_handler()
1290 notify_ring(dev_priv->engine[RCS]); in snb_gt_irq_handler()
1378 gen8_cs_irq_handler(dev_priv->engine[RCS], in gen8_gt_irq_handler()
3688 notify_ring(dev_priv->engine[RCS]); in i8xx_irq_handler()
3850 notify_ring(dev_priv->engine[RCS]); in i915_irq_handler()
4078 notify_ring(dev_priv->engine[RCS]); in i965_irq_handler()
Dintel_ringbuffer.h174 RCS = 0, enumerator
Di915_gpu_error.c38 case RCS: return "render"; in engine_str()
353 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) in error_print_instdone()
1214 case RCS: in error_record_engine_registers()
Di915_drv.c368 value = dev_priv->engine[RCS] && in i915_getparam()
369 dev_priv->engine[RCS]->schedule; in i915_getparam()
Di915_cmd_parser.c945 case RCS: in intel_engine_init_cmd_parser()
/drivers/gpu/drm/i915/selftests/
Dmock_gem_device.c229 i915->engine[RCS] = mock_engine(i915, "mock", RCS); in mock_gem_device()
230 if (!i915->engine[RCS]) in mock_gem_device()
Di915_gem_request.c41 request = mock_request(i915->engine[RCS], in igt_add_request()
65 request = mock_request(i915->engine[RCS], i915->kernel_context, T); in igt_wait_request()
135 request = mock_request(i915->engine[RCS], i915->kernel_context, T); in igt_fence_wait()
194 request = mock_request(i915->engine[RCS], ctx[0], 2 * HZ); in igt_request_rewind()
204 vip = mock_request(i915->engine[RCS], ctx[1], 0); in igt_request_rewind()
224 vip->global_seqno, intel_engine_get_seqno(i915->engine[RCS])); in igt_request_rewind()
Dintel_hangcheck.c602 if (!intel_engine_can_store_dword(i915->engine[RCS])) in igt_wait_reset()
614 rq = hang_create_request(&h, i915->engine[RCS], i915->kernel_context); in igt_wait_reset()
779 struct intel_engine_cs *engine = i915->engine[RCS]; in igt_handle_error()
790 if (!intel_engine_can_store_dword(i915->engine[RCS])) in igt_handle_error()
Di915_gem_coherency.c194 rq = i915_gem_request_alloc(i915->engine[RCS], i915->kernel_context); in gpu_set()
244 return intel_engine_can_store_dword(i915->engine[RCS]); in needs_mi_store_dword()
Dintel_breadcrumbs.c477 err = i915_subtests(tests, i915->engine[RCS]); in intel_breadcrumbs_mock_selftests()
Di915_gem_object.c451 rq = i915_gem_request_alloc(i915->engine[RCS], i915->kernel_context); in make_obj_busy()

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