| /drivers/net/wireless/ath/ath5k/ |
| D | caps.c | 35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_cfg.c | 29 .caps = MDP_CAP_SMP |
49 .caps = MDP_PIPE_CAP_HFLIP |
58 .caps = MDP_PIPE_CAP_HFLIP |
66 .caps = MDP_PIPE_CAP_HFLIP |
75 .caps = MDP_LM_CAP_DISPLAY, },
77 .caps = MDP_LM_CAP_DISPLAY, },
79 .caps = MDP_LM_CAP_DISPLAY, },
81 .caps = MDP_LM_CAP_WB },
83 .caps = MDP_LM_CAP_WB },
113 .caps = MDP_CAP_SMP |
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| D | mdp5_pipe.c | 21 struct drm_plane *plane, uint32_t caps, uint32_t blkcfg) in mdp5_pipe_assign() argument
53 if (caps & ~cur->caps) in mdp5_pipe_assign()
60 if (cur->caps & MDP_PIPE_CAP_CURSOR && in mdp5_pipe_assign()
67 if (!hwpipe || (hweight_long(cur->caps & ~caps) < in mdp5_pipe_assign()
68 hweight_long(hwpipe->caps & ~caps))) in mdp5_pipe_assign()
88 hwpipe->name, plane->name, caps); in mdp5_pipe_assign()
124 uint32_t reg_offset, uint32_t caps) in mdp5_pipe_init() argument
135 hwpipe->caps = caps; in mdp5_pipe_init()
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| D | mdp5_mixer.c | 50 uint32_t caps, struct mdp5_hw_mixer **mixer, in mdp5_mixer_assign() argument
79 if (caps & ~cur->caps) in mdp5_mixer_assign()
108 if (!(*mixer) || cur->caps & MDP_LM_CAP_PAIR) in mdp5_mixer_assign()
166 mixer->caps = lm->caps; in mdp5_mixer_init()
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | main.c | 186 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
198 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
199 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
207 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
208 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
221 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
222 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
234 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
250 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
286 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
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| D | pd.c | 122 return mlx4_bitmap_init(&priv->pd_bitmap, dev->caps.num_pds, in mlx4_init_pd_table()
124 dev->caps.reserved_pds, 0); in mlx4_init_pd_table()
137 (1 << 16) - 1, dev->caps.reserved_xrcds + 1, 0); in mlx4_init_xrcd_table()
156 dev->caps.uar_page_size); in mlx4_uar_alloc()
223 bf->buf_size = dev->caps.bf_reg_size / 2; in mlx4_bf_alloc()
224 bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size; in mlx4_bf_alloc()
225 if (uar->free_bf_bmap == (1 << dev->caps.bf_regs_per_page) - 1) in mlx4_bf_alloc()
255 idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size; in mlx4_bf_free()
277 mlx4_dbg(dev, "Effective reserved_uars=%d", dev->caps.reserved_uars); in mlx4_init_uar_table()
279 if (dev->caps.num_uars <= num_reserved_uar) { in mlx4_init_uar_table()
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| D | qp.c | 172 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) in __mlx4_qp_modify()
256 flags &= dev->caps.alloc_res_qp_mask; in mlx4_qp_reserve_range()
421 (dev->caps.num_qps - 1), qp); in mlx4_qp_alloc()
463 if (!(dev->caps.flags2 in mlx4_update_qp()
491 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) { in mlx4_update_qp()
519 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); in mlx4_qp_remove()
570 err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps, in mlx4_create_zones()
590 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_create_zones()
607 last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_create_zones()
770 u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base + in mlx4_init_qp_table()
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| D | profile.c | 183 dev->caps.num_qps = profile[i].num; in mlx4_make_profile()
192 dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift; in mlx4_make_profile()
204 dev->caps.num_srqs = profile[i].num; in mlx4_make_profile()
209 dev->caps.num_cqs = profile[i].num; in mlx4_make_profile()
219 dev->caps.num_eqs = roundup_pow_of_two( in mlx4_make_profile()
224 init_hca->log_num_eqs = ilog2(dev->caps.num_eqs); in mlx4_make_profile()
228 dev->caps.num_mpts = profile[i].num; in mlx4_make_profile()
237 dev->caps.num_mtts = profile[i].num; in mlx4_make_profile()
246 if (dev->caps.steering_mode == in mlx4_make_profile()
248 dev->caps.num_mgms = profile[i].num; in mlx4_make_profile()
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| D | fw.c | 404 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
432 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], in mlx4_QUERY_FUNC_CAP_wrapper()
441 if (dev->caps.phv_bit[port]) in mlx4_QUERY_FUNC_CAP_wrapper()
462 bitmap_weight(actv_ports.ports, dev->caps.num_ports), in mlx4_QUERY_FUNC_CAP_wrapper()
463 dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
466 size = dev->caps.function_caps; /* set PF behaviours */ in mlx4_QUERY_FUNC_CAP_wrapper()
474 size = dev->caps.num_qps; in mlx4_QUERY_FUNC_CAP_wrapper()
479 size = dev->caps.num_srqs; in mlx4_QUERY_FUNC_CAP_wrapper()
484 size = dev->caps.num_cqs; in mlx4_QUERY_FUNC_CAP_wrapper()
487 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || in mlx4_QUERY_FUNC_CAP_wrapper()
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| D | eq.c | 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) in get_async_ev_mask()
91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) in get_async_ev_mask()
229 slave == dev->caps.function || in mlx4_slave_event()
317 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_get_slave_port_state()
334 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_set_slave_port_state()
380 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in set_and_calc_slave_port_state()
510 int eqe_size = dev->caps.eqe_size; in mlx4_eq_int()
512 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { in mlx4_eq_int()
547 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
582 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
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| D | sense.c | 72 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_do_sense_ports()
75 dev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { in mlx4_do_sense_ports()
86 for (i = 0; i < dev->caps.num_ports; i++) in mlx4_do_sense_ports()
101 mlx4_do_sense_ports(dev, stype, &dev->caps.port_type[1]); in mlx4_sense_port()
120 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) in mlx4_start_sense()
139 for (port = 1; port <= dev->caps.num_ports; port++) in mlx4_sense_init()
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| /drivers/infiniband/hw/vmw_pvrdma/ |
| D | pvrdma_verbs.c | 75 props->fw_ver = dev->dsr->caps.fw_ver; in pvrdma_query_device()
76 props->sys_image_guid = dev->dsr->caps.sys_image_guid; in pvrdma_query_device()
77 props->max_mr_size = dev->dsr->caps.max_mr_size; in pvrdma_query_device()
78 props->page_size_cap = dev->dsr->caps.page_size_cap; in pvrdma_query_device()
79 props->vendor_id = dev->dsr->caps.vendor_id; in pvrdma_query_device()
81 props->hw_ver = dev->dsr->caps.hw_ver; in pvrdma_query_device()
82 props->max_qp = dev->dsr->caps.max_qp; in pvrdma_query_device()
83 props->max_qp_wr = dev->dsr->caps.max_qp_wr; in pvrdma_query_device()
84 props->device_cap_flags = dev->dsr->caps.device_cap_flags; in pvrdma_query_device()
85 props->max_sge = dev->dsr->caps.max_sge; in pvrdma_query_device()
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| /drivers/mmc/core/ |
| D | host.c | 204 host->caps |= MMC_CAP_8_BIT_DATA; in mmc_of_parse()
207 host->caps |= MMC_CAP_4_BIT_DATA; in mmc_of_parse()
234 host->caps |= MMC_CAP_NONREMOVABLE; in mmc_of_parse()
239 host->caps |= MMC_CAP_NEEDS_POLL; in mmc_of_parse()
280 host->caps |= MMC_CAP_SD_HIGHSPEED; in mmc_of_parse()
282 host->caps |= MMC_CAP_MMC_HIGHSPEED; in mmc_of_parse()
284 host->caps |= MMC_CAP_UHS_SDR12; in mmc_of_parse()
286 host->caps |= MMC_CAP_UHS_SDR25; in mmc_of_parse()
288 host->caps |= MMC_CAP_UHS_SDR50; in mmc_of_parse()
290 host->caps |= MMC_CAP_UHS_SDR104; in mmc_of_parse()
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| /drivers/infiniband/hw/hns/ |
| D | hns_roce_main.c | 58 return gid_index * hr_dev->caps.num_ports + port; in hns_get_gid_index()
84 if (port >= hr_dev->caps.num_ports) in hns_roce_add_gid()
104 if (port >= hr_dev->caps.num_ports) in hns_roce_del_gid()
160 for (port = 0; port < hr_dev->caps.num_ports; port++) { in hns_roce_netdev_event()
176 for (i = 0; i < hr_dev->caps.num_ports; i++) { in hns_roce_setup_mtu_mac()
178 hr_dev->caps.max_mtu); in hns_roce_setup_mtu_mac()
195 props->page_size_cap = hr_dev->caps.page_size_cap; in hns_roce_query_device()
199 props->max_qp = hr_dev->caps.num_qps; in hns_roce_query_device()
200 props->max_qp_wr = hr_dev->caps.max_wqes; in hns_roce_query_device()
203 props->max_sge = hr_dev->caps.max_sq_sg; in hns_roce_query_device()
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| D | hns_roce_pd.c | 48 return hns_roce_bitmap_init(&hr_dev->pd_bitmap, hr_dev->caps.num_pds, in hns_roce_init_pd_table()
49 hr_dev->caps.num_pds - 1, in hns_roce_init_pd_table()
50 hr_dev->caps.reserved_pds, 0); in hns_roce_init_pd_table()
110 (hr_dev->caps.phy_num_uars - 1) + 1; in hns_roce_uar_alloc()
131 hr_dev->caps.num_uars, in hns_roce_init_uar_table()
132 hr_dev->caps.num_uars - 1, in hns_roce_init_uar_table()
133 hr_dev->caps.reserved_uars, 0); in hns_roce_init_uar_table()
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| /drivers/video/fbdev/ |
| D | amba-clcd.c | 141 u32 caps; in clcdfb_set_bitfields() local
144 if (fb->panel->caps && fb->board->caps) in clcdfb_set_bitfields()
145 caps = fb->panel->caps & fb->board->caps; in clcdfb_set_bitfields()
148 caps = fb->panel->cntl & CNTL_BGR ? in clcdfb_set_bitfields()
151 caps &= ~CLCD_CAP_444; in clcdfb_set_bitfields()
156 caps &= ~CLCD_CAP_888; in clcdfb_set_bitfields()
170 caps &= CLCD_CAP_5551; in clcdfb_set_bitfields()
171 if (!caps) { in clcdfb_set_bitfields()
186 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { in clcdfb_set_bitfields()
195 if (var->green.length == 4 && caps & CLCD_CAP_444) in clcdfb_set_bitfields()
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| /drivers/crypto/marvell/ |
| D | cesa.c | 204 for (i = 0; i < cesa->caps->ncipher_algs; i++) { in mv_cesa_add_algs()
205 ret = crypto_register_alg(cesa->caps->cipher_algs[i]); in mv_cesa_add_algs()
210 for (i = 0; i < cesa->caps->nahash_algs; i++) { in mv_cesa_add_algs()
211 ret = crypto_register_ahash(cesa->caps->ahash_algs[i]); in mv_cesa_add_algs()
220 crypto_unregister_ahash(cesa->caps->ahash_algs[j]); in mv_cesa_add_algs()
221 i = cesa->caps->ncipher_algs; in mv_cesa_add_algs()
225 crypto_unregister_alg(cesa->caps->cipher_algs[j]); in mv_cesa_add_algs()
234 for (i = 0; i < cesa->caps->nahash_algs; i++) in mv_cesa_remove_algs()
235 crypto_unregister_ahash(cesa->caps->ahash_algs[i]); in mv_cesa_remove_algs()
237 for (i = 0; i < cesa->caps->ncipher_algs; i++) in mv_cesa_remove_algs()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_virt.h | 51 uint32_t caps; member
68 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
71 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
74 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
77 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
80 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
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| /drivers/clk/ingenic/ |
| D | cgu.c | 518 unsigned caps, i, num_possible; in ingenic_register_clock() local
560 caps = clk_info->type; in ingenic_register_clock()
562 if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { in ingenic_register_clock()
565 if (caps & CGU_CLK_MUX) in ingenic_register_clock()
589 if (caps & CGU_CLK_CUSTOM) { in ingenic_register_clock()
592 caps &= ~CGU_CLK_CUSTOM; in ingenic_register_clock()
594 if (caps) { in ingenic_register_clock()
596 __func__, caps); in ingenic_register_clock()
599 } else if (caps & CGU_CLK_PLL) { in ingenic_register_clock()
602 caps &= ~CGU_CLK_PLL; in ingenic_register_clock()
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| /drivers/infiniband/hw/mlx4/ |
| D | main.c | 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; in check_flow_steering_support()
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && in check_flow_steering_support()
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); in check_flow_steering_support()
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) in mlx4_ib_update_gids()
480 props->fw_ver = dev->dev->caps.fw_ver; in mlx4_ib_query_device()
486 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) in mlx4_ib_query_device()
488 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) in mlx4_ib_query_device()
490 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) in mlx4_ib_query_device()
492 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) in mlx4_ib_query_device()
494 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) in mlx4_ib_query_device()
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| /drivers/ptp/ |
| D | ptp_chardev.c | 124 struct ptp_clock_caps caps; in ptp_ioctl() local
140 memset(&caps, 0, sizeof(caps)); in ptp_ioctl()
141 caps.max_adj = ptp->info->max_adj; in ptp_ioctl()
142 caps.n_alarm = ptp->info->n_alarm; in ptp_ioctl()
143 caps.n_ext_ts = ptp->info->n_ext_ts; in ptp_ioctl()
144 caps.n_per_out = ptp->info->n_per_out; in ptp_ioctl()
145 caps.pps = ptp->info->pps; in ptp_ioctl()
146 caps.n_pins = ptp->info->n_pins; in ptp_ioctl()
147 caps.cross_timestamping = ptp->info->getcrosststamp != NULL; in ptp_ioctl()
148 if (copy_to_user((void __user *)arg, &caps, sizeof(caps))) in ptp_ioctl()
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| /drivers/mtd/nand/ |
| D | mtk_ecc.c | 70 const struct mtk_ecc_caps *caps; member
146 for (i = 0; i < ecc->caps->num_ecc_strength; i++) { in mtk_ecc_config()
147 if (ecc->caps->ecc_strength[i] == config->strength) in mtk_ecc_config()
151 if (i == ecc->caps->num_ecc_strength) { in mtk_ecc_config()
201 err &= ecc->caps->err_mask; in mtk_ecc_get_stats()
202 if (err == ecc->caps->err_mask) { in mtk_ecc_get_stats()
292 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) in mtk_ecc_enable()
374 ecc->regs + ecc->caps->encode_parity_reg0, in mtk_ecc_encode()
390 const u8 *ecc_strength = ecc->caps->ecc_strength; in mtk_ecc_adjust_strength()
393 for (i = 0; i < ecc->caps->num_ecc_strength; i++) { in mtk_ecc_adjust_strength()
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| D | denali_dt.c | 34 unsigned int caps; member
41 .caps = DENALI_CAP_HW_ECC_FIXUP,
48 .caps = DENALI_CAP_HW_ECC_FIXUP |
57 .caps = DENALI_CAP_HW_ECC_FIXUP |
95 denali->caps = data->caps; in denali_dt_probe()
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| /drivers/mmc/host/ |
| D | atmel-mci.c | 349 struct atmel_mci_caps caps; member
537 if (host->caps.has_odd_clk_div) in atmci_regs_show()
551 if (host->caps.has_cstor_reg) in atmci_regs_show()
559 if (host->caps.has_dma_conf_reg) { in atmci_regs_show()
569 if (host->caps.has_cfg_reg) { in atmci_regs_show()
900 if (!host->caps.has_rwproof) { in atmci_pdc_set_single_buf()
964 if ((!host->caps.has_rwproof) in atmci_pdc_complete()
966 if (host->caps.has_bad_data_ordering) in atmci_pdc_complete()
1000 if (host->caps.has_dma_conf_reg) in atmci_dma_complete()
1114 if ((!host->caps.has_rwproof) in atmci_prepare_data_pdc()
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| /drivers/hwmon/ |
| D | acpi_power_meter.c | 93 struct acpi_power_meter_capabilities caps; member
169 if (temp > resource->caps.max_avg_interval || in set_avg_interval()
170 temp < resource->caps.min_avg_interval) in set_avg_interval()
241 if (temp > resource->caps.max_cap || temp < resource->caps.min_cap) in set_cap()
331 msecs_to_jiffies(resource->caps.sampling_time)) && in update_meter()
403 val = resource->caps.min_avg_interval; in show_val()
406 val = resource->caps.max_avg_interval; in show_val()
409 val = resource->caps.min_cap * 1000; in show_val()
412 val = resource->caps.max_cap * 1000; in show_val()
415 if (resource->caps.hysteresis == UNKNOWN_HYSTERESIS) in show_val()
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