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Searched refs:clksrc (Results 1 – 12 of 12) sorted by relevance

/drivers/clocksource/
Dmmio.c15 struct clocksource clksrc; member
20 return container_of(c, struct clocksource_mmio, clksrc); in to_mmio_clksrc()
66 cs->clksrc.name = name; in clocksource_mmio_init()
67 cs->clksrc.rating = rating; in clocksource_mmio_init()
68 cs->clksrc.read = read; in clocksource_mmio_init()
69 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); in clocksource_mmio_init()
70 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in clocksource_mmio_init()
72 return clocksource_register_hz(&cs->clksrc, hz); in clocksource_mmio_init()
Dtimer-atmel-pit.c43 struct clocksource clksrc; member
52 static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc) in clksrc_to_pit_data() argument
54 return container_of(clksrc, struct pit_data, clksrc); in clksrc_to_pit_data()
224 data->clksrc.mask = CLOCKSOURCE_MASK(bits); in at91sam926x_pit_dt_init()
225 data->clksrc.name = "pit"; in at91sam926x_pit_dt_init()
226 data->clksrc.rating = 175; in at91sam926x_pit_dt_init()
227 data->clksrc.read = read_pit_clk; in at91sam926x_pit_dt_init()
228 data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in at91sam926x_pit_dt_init()
230 ret = clocksource_register_hz(&data->clksrc, pit_rate); in at91sam926x_pit_dt_init()
242 clocksource_unregister(&data->clksrc); in at91sam926x_pit_dt_init()
Dtimer-sun5i.c53 struct clocksource clksrc; member
57 container_of(x, struct sun5i_timer_clksrc, clksrc)
156 static u64 sun5i_clksrc_read(struct clocksource *clksrc) in sun5i_clksrc_read() argument
158 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc); in sun5i_clksrc_read()
172 clocksource_unregister(&cs->clksrc); in sun5i_rate_cb_clksrc()
176 clocksource_register_hz(&cs->clksrc, ndata->new_rate); in sun5i_rate_cb_clksrc()
226 cs->clksrc.name = node->name; in sun5i_setup_clocksource()
227 cs->clksrc.rating = 340; in sun5i_setup_clocksource()
228 cs->clksrc.read = sun5i_clksrc_read; in sun5i_setup_clocksource()
229 cs->clksrc.mask = CLOCKSOURCE_MASK(32); in sun5i_setup_clocksource()
[all …]
Dtcb_clksrc.c114 static struct clocksource clksrc = { variable
385 printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK, in tcb_clksrc_init()
391 clksrc.read = tc_get_cycles32; in tcb_clksrc_init()
408 ret = clocksource_register_hz(&clksrc, divided_rate); in tcb_clksrc_init()
420 clocksource_unregister(&clksrc); in tcb_clksrc_init()
Dtimer-nps.c80 static u64 nps_clksrc_read(struct clocksource *clksrc) in nps_clksrc_read() argument
DMakefile24 obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
/drivers/staging/irda/drivers/
Dvlsi_ir.c85 static int clksrc = 0; /* default is 0(auto) */ variable
86 module_param(clksrc, int, 0);
87 MODULE_PARM_DESC(clksrc, "clock input source selection");
341 (clksrc>=2) ? ((clksrc==3)?"40MHz XCLK":"48MHz XCLK") in vlsi_seq_show()
342 : ((clksrc==1)?"48MHz PLL":"autodetect")); in vlsi_seq_show()
768 nphyctl = PHYCTL_MIR(clksrc==3); in vlsi_set_baud()
785 nphyctl = PHYCTL_SIR(baudrate,sirpulse,clksrc==3); in vlsi_set_baud()
1146 if (clksrc < 2) { /* auto or PLL: try PLL */ in vlsi_start_clock()
1165 if (clksrc == 1) { /* explicitly asked for PLL hence bail out */ in vlsi_start_clock()
1173 clksrc = 3; /* fallback to 40MHz XCLK (OB800) */ in vlsi_start_clock()
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/drivers/gpu/drm/shmobile/
Dshmob_drm_drv.c70 enum shmob_drm_clk_source clksrc) in shmob_drm_setup_clocks() argument
75 switch (clksrc) { in shmob_drm_setup_clocks()
/drivers/mfd/
Dsm501.c510 int clksrc, in sm501_set_clock() argument
527 switch (clksrc) { in sm501_set_clock()
591 clock = clock & ~(0xFF << clksrc); in sm501_set_clock()
592 clock |= reg<<clksrc; in sm501_set_clock()
641 int clksrc, in sm501_find_clock() argument
648 switch (clksrc) { in sm501_find_clock()
/drivers/mmc/host/
Dsdhci-s3c.c182 struct clk *clksrc = ourhost->clk_bus[src]; in sdhci_s3c_consider_clock() local
185 if (IS_ERR(clksrc)) in sdhci_s3c_consider_clock()
193 rate = clk_round_rate(clksrc, wanted); in sdhci_s3c_consider_clock()
/drivers/tty/serial/
Dmax310x.c551 unsigned int div, clksrc, pllcfg = 0; in max310x_set_ref_clk() local
593 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); in max310x_set_ref_clk()
597 clksrc |= MAX310X_CLKSRC_PLL_BIT; in max310x_set_ref_clk()
600 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; in max310x_set_ref_clk()
602 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
/drivers/spi/
Dspi-rspi.c300 unsigned long clksrc; in rspi_rz_set_config_register() local
305 clksrc = clk_get_rate(rspi->clk); in rspi_rz_set_config_register()
307 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ in rspi_rz_set_config_register()
310 clksrc /= 2; in rspi_rz_set_config_register()
314 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; in rspi_rz_set_config_register()