1 /*
2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
3 *
4 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/regmap.h>
25 #include <linux/serial_core.h>
26 #include <linux/serial.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/spi/spi.h>
30 #include <linux/uaccess.h>
31
32 #define MAX310X_NAME "max310x"
33 #define MAX310X_MAJOR 204
34 #define MAX310X_MINOR 209
35 #define MAX310X_UART_NRMAX 16
36
37 /* MAX310X register definitions */
38 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
39 #define MAX310X_THR_REG (0x00) /* TX FIFO */
40 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
41 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
42 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
43 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
44 #define MAX310X_REG_05 (0x05)
45 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
46 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
47 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
48 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
49 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
50 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
51 #define MAX310X_LCR_REG (0x0b) /* LCR */
52 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
53 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
54 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
55 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
56 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
57 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
58 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
59 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
60 #define MAX310X_XON1_REG (0x14) /* XON1 character */
61 #define MAX310X_XON2_REG (0x15) /* XON2 character */
62 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
63 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
64 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
65 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
66 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
67 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
68 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
69 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
70 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
71 #define MAX310X_REG_1F (0x1f)
72
73 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
74
75 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
76 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
77
78 /* Extended registers */
79 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
80
81 /* IRQ register bits */
82 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
83 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
84 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
85 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
86 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
87 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
88 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
89 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
90
91 /* LSR register bits */
92 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
93 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
94 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
95 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
96 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
97 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
98 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
99
100 /* Special character register bits */
101 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
102 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
103 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
104 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
105 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
106 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
107
108 /* Status register bits */
109 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
110 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
111 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
112 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
113 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
114 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
115
116 /* MODE1 register bits */
117 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
118 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
119 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
120 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
121 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
122 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
123 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
124 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
125
126 /* MODE2 register bits */
127 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
128 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
129 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
130 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
131 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
132 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
133 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
134 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
135
136 /* LCR register bits */
137 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
138 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
139 *
140 * Word length bits table:
141 * 00 -> 5 bit words
142 * 01 -> 6 bit words
143 * 10 -> 7 bit words
144 * 11 -> 8 bit words
145 */
146 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
147 *
148 * STOP length bit table:
149 * 0 -> 1 stop bit
150 * 1 -> 1-1.5 stop bits if
151 * word length is 5,
152 * 2 stop bits otherwise
153 */
154 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
155 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
156 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
157 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
158 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
159
160 /* IRDA register bits */
161 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
162 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
163
164 /* Flow control trigger level register masks */
165 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
166 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
167 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
168 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
169
170 /* FIFO interrupt trigger level register masks */
171 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
172 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
173 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
174 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
175
176 /* Flow control register bits */
177 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
178 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
179 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
180 * are used in conjunction with
181 * XOFF2 for definition of
182 * special character */
183 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
184 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
185 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
186 *
187 * SWFLOW bits 1 & 0 table:
188 * 00 -> no transmitter flow
189 * control
190 * 01 -> receiver compares
191 * XON2 and XOFF2
192 * and controls
193 * transmitter
194 * 10 -> receiver compares
195 * XON1 and XOFF1
196 * and controls
197 * transmitter
198 * 11 -> receiver compares
199 * XON1, XON2, XOFF1 and
200 * XOFF2 and controls
201 * transmitter
202 */
203 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
204 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
205 *
206 * SWFLOW bits 3 & 2 table:
207 * 00 -> no received flow
208 * control
209 * 01 -> transmitter generates
210 * XON2 and XOFF2
211 * 10 -> transmitter generates
212 * XON1 and XOFF1
213 * 11 -> transmitter generates
214 * XON1, XON2, XOFF1 and
215 * XOFF2
216 */
217
218 /* PLL configuration register masks */
219 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
220 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
221
222 /* Baud rate generator configuration register bits */
223 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
224 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
225
226 /* Clock source register bits */
227 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
228 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
229 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
230 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
231 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
232
233 /* Global commands */
234 #define MAX310X_EXTREG_ENBL (0xce)
235 #define MAX310X_EXTREG_DSBL (0xcd)
236
237 /* Misc definitions */
238 #define MAX310X_FIFO_SIZE (128)
239 #define MAX310x_REV_MASK (0xf8)
240
241 /* MAX3107 specific */
242 #define MAX3107_REV_ID (0xa0)
243
244 /* MAX3109 specific */
245 #define MAX3109_REV_ID (0xc0)
246
247 /* MAX14830 specific */
248 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
249 #define MAX14830_REV_ID (0xb0)
250
251 struct max310x_devtype {
252 char name[9];
253 int nr;
254 int (*detect)(struct device *);
255 void (*power)(struct uart_port *, int);
256 };
257
258 struct max310x_one {
259 struct uart_port port;
260 struct work_struct tx_work;
261 struct work_struct md_work;
262 struct work_struct rs_work;
263 };
264
265 struct max310x_port {
266 struct max310x_devtype *devtype;
267 struct regmap *regmap;
268 struct mutex mutex;
269 struct clk *clk;
270 #ifdef CONFIG_GPIOLIB
271 struct gpio_chip gpio;
272 #endif
273 struct max310x_one p[0];
274 };
275
276 static struct uart_driver max310x_uart = {
277 .owner = THIS_MODULE,
278 .driver_name = MAX310X_NAME,
279 .dev_name = "ttyMAX",
280 .major = MAX310X_MAJOR,
281 .minor = MAX310X_MINOR,
282 .nr = MAX310X_UART_NRMAX,
283 };
284
285 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
286
max310x_port_read(struct uart_port * port,u8 reg)287 static u8 max310x_port_read(struct uart_port *port, u8 reg)
288 {
289 struct max310x_port *s = dev_get_drvdata(port->dev);
290 unsigned int val = 0;
291
292 regmap_read(s->regmap, port->iobase + reg, &val);
293
294 return val;
295 }
296
max310x_port_write(struct uart_port * port,u8 reg,u8 val)297 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
298 {
299 struct max310x_port *s = dev_get_drvdata(port->dev);
300
301 regmap_write(s->regmap, port->iobase + reg, val);
302 }
303
max310x_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)304 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
305 {
306 struct max310x_port *s = dev_get_drvdata(port->dev);
307
308 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
309 }
310
max3107_detect(struct device * dev)311 static int max3107_detect(struct device *dev)
312 {
313 struct max310x_port *s = dev_get_drvdata(dev);
314 unsigned int val = 0;
315 int ret;
316
317 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
318 if (ret)
319 return ret;
320
321 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
322 dev_err(dev,
323 "%s ID 0x%02x does not match\n", s->devtype->name, val);
324 return -ENODEV;
325 }
326
327 return 0;
328 }
329
max3108_detect(struct device * dev)330 static int max3108_detect(struct device *dev)
331 {
332 struct max310x_port *s = dev_get_drvdata(dev);
333 unsigned int val = 0;
334 int ret;
335
336 /* MAX3108 have not REV ID register, we just check default value
337 * from clocksource register to make sure everything works.
338 */
339 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
340 if (ret)
341 return ret;
342
343 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
344 dev_err(dev, "%s not present\n", s->devtype->name);
345 return -ENODEV;
346 }
347
348 return 0;
349 }
350
max3109_detect(struct device * dev)351 static int max3109_detect(struct device *dev)
352 {
353 struct max310x_port *s = dev_get_drvdata(dev);
354 unsigned int val = 0;
355 int ret;
356
357 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
358 MAX310X_EXTREG_ENBL);
359 if (ret)
360 return ret;
361
362 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
363 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
364 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
365 dev_err(dev,
366 "%s ID 0x%02x does not match\n", s->devtype->name, val);
367 return -ENODEV;
368 }
369
370 return 0;
371 }
372
max310x_power(struct uart_port * port,int on)373 static void max310x_power(struct uart_port *port, int on)
374 {
375 max310x_port_update(port, MAX310X_MODE1_REG,
376 MAX310X_MODE1_FORCESLEEP_BIT,
377 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
378 if (on)
379 msleep(50);
380 }
381
max14830_detect(struct device * dev)382 static int max14830_detect(struct device *dev)
383 {
384 struct max310x_port *s = dev_get_drvdata(dev);
385 unsigned int val = 0;
386 int ret;
387
388 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
389 MAX310X_EXTREG_ENBL);
390 if (ret)
391 return ret;
392
393 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
394 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
395 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
396 dev_err(dev,
397 "%s ID 0x%02x does not match\n", s->devtype->name, val);
398 return -ENODEV;
399 }
400
401 return 0;
402 }
403
max14830_power(struct uart_port * port,int on)404 static void max14830_power(struct uart_port *port, int on)
405 {
406 max310x_port_update(port, MAX310X_BRGCFG_REG,
407 MAX14830_BRGCFG_CLKDIS_BIT,
408 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
409 if (on)
410 msleep(50);
411 }
412
413 static const struct max310x_devtype max3107_devtype = {
414 .name = "MAX3107",
415 .nr = 1,
416 .detect = max3107_detect,
417 .power = max310x_power,
418 };
419
420 static const struct max310x_devtype max3108_devtype = {
421 .name = "MAX3108",
422 .nr = 1,
423 .detect = max3108_detect,
424 .power = max310x_power,
425 };
426
427 static const struct max310x_devtype max3109_devtype = {
428 .name = "MAX3109",
429 .nr = 2,
430 .detect = max3109_detect,
431 .power = max310x_power,
432 };
433
434 static const struct max310x_devtype max14830_devtype = {
435 .name = "MAX14830",
436 .nr = 4,
437 .detect = max14830_detect,
438 .power = max14830_power,
439 };
440
max310x_reg_writeable(struct device * dev,unsigned int reg)441 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
442 {
443 switch (reg & 0x1f) {
444 case MAX310X_IRQSTS_REG:
445 case MAX310X_LSR_IRQSTS_REG:
446 case MAX310X_SPCHR_IRQSTS_REG:
447 case MAX310X_STS_IRQSTS_REG:
448 case MAX310X_TXFIFOLVL_REG:
449 case MAX310X_RXFIFOLVL_REG:
450 return false;
451 default:
452 break;
453 }
454
455 return true;
456 }
457
max310x_reg_volatile(struct device * dev,unsigned int reg)458 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
459 {
460 switch (reg & 0x1f) {
461 case MAX310X_RHR_REG:
462 case MAX310X_IRQSTS_REG:
463 case MAX310X_LSR_IRQSTS_REG:
464 case MAX310X_SPCHR_IRQSTS_REG:
465 case MAX310X_STS_IRQSTS_REG:
466 case MAX310X_TXFIFOLVL_REG:
467 case MAX310X_RXFIFOLVL_REG:
468 case MAX310X_GPIODATA_REG:
469 case MAX310X_BRGDIVLSB_REG:
470 case MAX310X_REG_05:
471 case MAX310X_REG_1F:
472 return true;
473 default:
474 break;
475 }
476
477 return false;
478 }
479
max310x_reg_precious(struct device * dev,unsigned int reg)480 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
481 {
482 switch (reg & 0x1f) {
483 case MAX310X_RHR_REG:
484 case MAX310X_IRQSTS_REG:
485 case MAX310X_SPCHR_IRQSTS_REG:
486 case MAX310X_STS_IRQSTS_REG:
487 return true;
488 default:
489 break;
490 }
491
492 return false;
493 }
494
max310x_set_baud(struct uart_port * port,int baud)495 static int max310x_set_baud(struct uart_port *port, int baud)
496 {
497 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
498
499 /*
500 * Calculate the integer divisor first. Select a proper mode
501 * in case if the requested baud is too high for the pre-defined
502 * clocks frequency.
503 */
504 div = port->uartclk / baud;
505 if (div < 8) {
506 /* Mode x4 */
507 c = 4;
508 mode = MAX310X_BRGCFG_4XMODE_BIT;
509 } else if (div < 16) {
510 /* Mode x2 */
511 c = 8;
512 mode = MAX310X_BRGCFG_2XMODE_BIT;
513 } else {
514 c = 16;
515 }
516
517 /* Calculate the divisor in accordance with the fraction coefficient */
518 div /= c;
519 F = c*baud;
520
521 /* Calculate the baud rate fraction */
522 if (div > 0)
523 frac = (16*(port->uartclk % F)) / F;
524 else
525 div = 1;
526
527 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
528 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
529 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
530
531 /* Return the actual baud rate we just programmed */
532 return (16*port->uartclk) / (c*(16*div + frac));
533 }
534
max310x_update_best_err(unsigned long f,long * besterr)535 static int max310x_update_best_err(unsigned long f, long *besterr)
536 {
537 /* Use baudrate 115200 for calculate error */
538 long err = f % (460800 * 16);
539
540 if ((*besterr < 0) || (*besterr > err)) {
541 *besterr = err;
542 return 0;
543 }
544
545 return 1;
546 }
547
max310x_set_ref_clk(struct max310x_port * s,unsigned long freq,bool xtal)548 static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
549 bool xtal)
550 {
551 unsigned int div, clksrc, pllcfg = 0;
552 long besterr = -1;
553 unsigned long fdiv, fmul, bestfreq = freq;
554
555 /* First, update error without PLL */
556 max310x_update_best_err(freq, &besterr);
557
558 /* Try all possible PLL dividers */
559 for (div = 1; (div <= 63) && besterr; div++) {
560 fdiv = DIV_ROUND_CLOSEST(freq, div);
561
562 /* Try multiplier 6 */
563 fmul = fdiv * 6;
564 if ((fdiv >= 500000) && (fdiv <= 800000))
565 if (!max310x_update_best_err(fmul, &besterr)) {
566 pllcfg = (0 << 6) | div;
567 bestfreq = fmul;
568 }
569 /* Try multiplier 48 */
570 fmul = fdiv * 48;
571 if ((fdiv >= 850000) && (fdiv <= 1200000))
572 if (!max310x_update_best_err(fmul, &besterr)) {
573 pllcfg = (1 << 6) | div;
574 bestfreq = fmul;
575 }
576 /* Try multiplier 96 */
577 fmul = fdiv * 96;
578 if ((fdiv >= 425000) && (fdiv <= 1000000))
579 if (!max310x_update_best_err(fmul, &besterr)) {
580 pllcfg = (2 << 6) | div;
581 bestfreq = fmul;
582 }
583 /* Try multiplier 144 */
584 fmul = fdiv * 144;
585 if ((fdiv >= 390000) && (fdiv <= 667000))
586 if (!max310x_update_best_err(fmul, &besterr)) {
587 pllcfg = (3 << 6) | div;
588 bestfreq = fmul;
589 }
590 }
591
592 /* Configure clock source */
593 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
594
595 /* Configure PLL */
596 if (pllcfg) {
597 clksrc |= MAX310X_CLKSRC_PLL_BIT;
598 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
599 } else
600 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
601
602 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
603
604 /* Wait for crystal */
605 if (pllcfg && xtal)
606 msleep(10);
607
608 return (int)bestfreq;
609 }
610
max310x_handle_rx(struct uart_port * port,unsigned int rxlen)611 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
612 {
613 unsigned int sts, ch, flag;
614
615 if (unlikely(rxlen >= port->fifosize)) {
616 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
617 port->icount.buf_overrun++;
618 /* Ensure sanity of RX level */
619 rxlen = port->fifosize;
620 }
621
622 while (rxlen--) {
623 ch = max310x_port_read(port, MAX310X_RHR_REG);
624 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
625
626 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
627 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
628
629 port->icount.rx++;
630 flag = TTY_NORMAL;
631
632 if (unlikely(sts)) {
633 if (sts & MAX310X_LSR_RXBRK_BIT) {
634 port->icount.brk++;
635 if (uart_handle_break(port))
636 continue;
637 } else if (sts & MAX310X_LSR_RXPAR_BIT)
638 port->icount.parity++;
639 else if (sts & MAX310X_LSR_FRERR_BIT)
640 port->icount.frame++;
641 else if (sts & MAX310X_LSR_RXOVR_BIT)
642 port->icount.overrun++;
643
644 sts &= port->read_status_mask;
645 if (sts & MAX310X_LSR_RXBRK_BIT)
646 flag = TTY_BREAK;
647 else if (sts & MAX310X_LSR_RXPAR_BIT)
648 flag = TTY_PARITY;
649 else if (sts & MAX310X_LSR_FRERR_BIT)
650 flag = TTY_FRAME;
651 else if (sts & MAX310X_LSR_RXOVR_BIT)
652 flag = TTY_OVERRUN;
653 }
654
655 if (uart_handle_sysrq_char(port, ch))
656 continue;
657
658 if (sts & port->ignore_status_mask)
659 continue;
660
661 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
662 }
663
664 tty_flip_buffer_push(&port->state->port);
665 }
666
max310x_handle_tx(struct uart_port * port)667 static void max310x_handle_tx(struct uart_port *port)
668 {
669 struct circ_buf *xmit = &port->state->xmit;
670 unsigned int txlen, to_send;
671
672 if (unlikely(port->x_char)) {
673 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
674 port->icount.tx++;
675 port->x_char = 0;
676 return;
677 }
678
679 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
680 return;
681
682 /* Get length of data pending in circular buffer */
683 to_send = uart_circ_chars_pending(xmit);
684 if (likely(to_send)) {
685 /* Limit to size of TX FIFO */
686 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
687 txlen = port->fifosize - txlen;
688 to_send = (to_send > txlen) ? txlen : to_send;
689
690 /* Add data to send */
691 port->icount.tx += to_send;
692 while (to_send--) {
693 max310x_port_write(port, MAX310X_THR_REG,
694 xmit->buf[xmit->tail]);
695 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
696 }
697 }
698
699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
700 uart_write_wakeup(port);
701 }
702
max310x_port_irq(struct max310x_port * s,int portno)703 static void max310x_port_irq(struct max310x_port *s, int portno)
704 {
705 struct uart_port *port = &s->p[portno].port;
706
707 do {
708 unsigned int ists, lsr, rxlen;
709
710 /* Read IRQ status & RX FIFO level */
711 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
712 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
713 if (!ists && !rxlen)
714 break;
715
716 if (ists & MAX310X_IRQ_CTS_BIT) {
717 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
718 uart_handle_cts_change(port,
719 !!(lsr & MAX310X_LSR_CTS_BIT));
720 }
721 if (rxlen)
722 max310x_handle_rx(port, rxlen);
723 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
724 mutex_lock(&s->mutex);
725 max310x_handle_tx(port);
726 mutex_unlock(&s->mutex);
727 }
728 } while (1);
729 }
730
max310x_ist(int irq,void * dev_id)731 static irqreturn_t max310x_ist(int irq, void *dev_id)
732 {
733 struct max310x_port *s = (struct max310x_port *)dev_id;
734
735 if (s->devtype->nr > 1) {
736 do {
737 unsigned int val = ~0;
738
739 WARN_ON_ONCE(regmap_read(s->regmap,
740 MAX310X_GLOBALIRQ_REG, &val));
741 val = ((1 << s->devtype->nr) - 1) & ~val;
742 if (!val)
743 break;
744 max310x_port_irq(s, fls(val) - 1);
745 } while (1);
746 } else
747 max310x_port_irq(s, 0);
748
749 return IRQ_HANDLED;
750 }
751
max310x_wq_proc(struct work_struct * ws)752 static void max310x_wq_proc(struct work_struct *ws)
753 {
754 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
755 struct max310x_port *s = dev_get_drvdata(one->port.dev);
756
757 mutex_lock(&s->mutex);
758 max310x_handle_tx(&one->port);
759 mutex_unlock(&s->mutex);
760 }
761
max310x_start_tx(struct uart_port * port)762 static void max310x_start_tx(struct uart_port *port)
763 {
764 struct max310x_one *one = container_of(port, struct max310x_one, port);
765
766 if (!work_pending(&one->tx_work))
767 schedule_work(&one->tx_work);
768 }
769
max310x_tx_empty(struct uart_port * port)770 static unsigned int max310x_tx_empty(struct uart_port *port)
771 {
772 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
773
774 return lvl ? 0 : TIOCSER_TEMT;
775 }
776
max310x_get_mctrl(struct uart_port * port)777 static unsigned int max310x_get_mctrl(struct uart_port *port)
778 {
779 /* DCD and DSR are not wired and CTS/RTS is handled automatically
780 * so just indicate DSR and CAR asserted
781 */
782 return TIOCM_DSR | TIOCM_CAR;
783 }
784
max310x_md_proc(struct work_struct * ws)785 static void max310x_md_proc(struct work_struct *ws)
786 {
787 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
788
789 max310x_port_update(&one->port, MAX310X_MODE2_REG,
790 MAX310X_MODE2_LOOPBACK_BIT,
791 (one->port.mctrl & TIOCM_LOOP) ?
792 MAX310X_MODE2_LOOPBACK_BIT : 0);
793 }
794
max310x_set_mctrl(struct uart_port * port,unsigned int mctrl)795 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
796 {
797 struct max310x_one *one = container_of(port, struct max310x_one, port);
798
799 schedule_work(&one->md_work);
800 }
801
max310x_break_ctl(struct uart_port * port,int break_state)802 static void max310x_break_ctl(struct uart_port *port, int break_state)
803 {
804 max310x_port_update(port, MAX310X_LCR_REG,
805 MAX310X_LCR_TXBREAK_BIT,
806 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
807 }
808
max310x_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)809 static void max310x_set_termios(struct uart_port *port,
810 struct ktermios *termios,
811 struct ktermios *old)
812 {
813 unsigned int lcr = 0, flow = 0;
814 int baud;
815
816 /* Mask termios capabilities we don't support */
817 termios->c_cflag &= ~CMSPAR;
818
819 /* Word size */
820 switch (termios->c_cflag & CSIZE) {
821 case CS5:
822 break;
823 case CS6:
824 lcr = MAX310X_LCR_LENGTH0_BIT;
825 break;
826 case CS7:
827 lcr = MAX310X_LCR_LENGTH1_BIT;
828 break;
829 case CS8:
830 default:
831 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
832 break;
833 }
834
835 /* Parity */
836 if (termios->c_cflag & PARENB) {
837 lcr |= MAX310X_LCR_PARITY_BIT;
838 if (!(termios->c_cflag & PARODD))
839 lcr |= MAX310X_LCR_EVENPARITY_BIT;
840 }
841
842 /* Stop bits */
843 if (termios->c_cflag & CSTOPB)
844 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
845
846 /* Update LCR register */
847 max310x_port_write(port, MAX310X_LCR_REG, lcr);
848
849 /* Set read status mask */
850 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
851 if (termios->c_iflag & INPCK)
852 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
853 MAX310X_LSR_FRERR_BIT;
854 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
855 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
856
857 /* Set status ignore mask */
858 port->ignore_status_mask = 0;
859 if (termios->c_iflag & IGNBRK)
860 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
861 if (!(termios->c_cflag & CREAD))
862 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
863 MAX310X_LSR_RXOVR_BIT |
864 MAX310X_LSR_FRERR_BIT |
865 MAX310X_LSR_RXBRK_BIT;
866
867 /* Configure flow control */
868 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
869 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
870 if (termios->c_cflag & CRTSCTS)
871 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
872 MAX310X_FLOWCTRL_AUTORTS_BIT;
873 if (termios->c_iflag & IXON)
874 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
875 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
876 if (termios->c_iflag & IXOFF)
877 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
878 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
879 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
880
881 /* Get baud rate generator configuration */
882 baud = uart_get_baud_rate(port, termios, old,
883 port->uartclk / 16 / 0xffff,
884 port->uartclk / 4);
885
886 /* Setup baudrate generator */
887 baud = max310x_set_baud(port, baud);
888
889 /* Update timeout according to new baud rate */
890 uart_update_timeout(port, termios->c_cflag, baud);
891 }
892
max310x_rs_proc(struct work_struct * ws)893 static void max310x_rs_proc(struct work_struct *ws)
894 {
895 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
896 unsigned int val;
897
898 val = (one->port.rs485.delay_rts_before_send << 4) |
899 one->port.rs485.delay_rts_after_send;
900 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
901
902 if (one->port.rs485.flags & SER_RS485_ENABLED) {
903 max310x_port_update(&one->port, MAX310X_MODE1_REG,
904 MAX310X_MODE1_TRNSCVCTRL_BIT,
905 MAX310X_MODE1_TRNSCVCTRL_BIT);
906 max310x_port_update(&one->port, MAX310X_MODE2_REG,
907 MAX310X_MODE2_ECHOSUPR_BIT,
908 MAX310X_MODE2_ECHOSUPR_BIT);
909 } else {
910 max310x_port_update(&one->port, MAX310X_MODE1_REG,
911 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
912 max310x_port_update(&one->port, MAX310X_MODE2_REG,
913 MAX310X_MODE2_ECHOSUPR_BIT, 0);
914 }
915 }
916
max310x_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)917 static int max310x_rs485_config(struct uart_port *port,
918 struct serial_rs485 *rs485)
919 {
920 struct max310x_one *one = container_of(port, struct max310x_one, port);
921
922 if ((rs485->delay_rts_before_send > 0x0f) ||
923 (rs485->delay_rts_after_send > 0x0f))
924 return -ERANGE;
925
926 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
927 memset(rs485->padding, 0, sizeof(rs485->padding));
928 port->rs485 = *rs485;
929
930 schedule_work(&one->rs_work);
931
932 return 0;
933 }
934
max310x_startup(struct uart_port * port)935 static int max310x_startup(struct uart_port *port)
936 {
937 struct max310x_port *s = dev_get_drvdata(port->dev);
938 unsigned int val;
939
940 s->devtype->power(port, 1);
941
942 /* Configure MODE1 register */
943 max310x_port_update(port, MAX310X_MODE1_REG,
944 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
945
946 /* Configure MODE2 register & Reset FIFOs*/
947 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
948 max310x_port_write(port, MAX310X_MODE2_REG, val);
949 max310x_port_update(port, MAX310X_MODE2_REG,
950 MAX310X_MODE2_FIFORST_BIT, 0);
951
952 /* Configure flow control levels */
953 /* Flow control halt level 96, resume level 48 */
954 max310x_port_write(port, MAX310X_FLOWLVL_REG,
955 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
956
957 /* Clear IRQ status register */
958 max310x_port_read(port, MAX310X_IRQSTS_REG);
959
960 /* Enable RX, TX, CTS change interrupts */
961 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
962 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
963
964 return 0;
965 }
966
max310x_shutdown(struct uart_port * port)967 static void max310x_shutdown(struct uart_port *port)
968 {
969 struct max310x_port *s = dev_get_drvdata(port->dev);
970
971 /* Disable all interrupts */
972 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
973
974 s->devtype->power(port, 0);
975 }
976
max310x_type(struct uart_port * port)977 static const char *max310x_type(struct uart_port *port)
978 {
979 struct max310x_port *s = dev_get_drvdata(port->dev);
980
981 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
982 }
983
max310x_request_port(struct uart_port * port)984 static int max310x_request_port(struct uart_port *port)
985 {
986 /* Do nothing */
987 return 0;
988 }
989
max310x_config_port(struct uart_port * port,int flags)990 static void max310x_config_port(struct uart_port *port, int flags)
991 {
992 if (flags & UART_CONFIG_TYPE)
993 port->type = PORT_MAX310X;
994 }
995
max310x_verify_port(struct uart_port * port,struct serial_struct * s)996 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
997 {
998 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
999 return -EINVAL;
1000 if (s->irq != port->irq)
1001 return -EINVAL;
1002
1003 return 0;
1004 }
1005
max310x_null_void(struct uart_port * port)1006 static void max310x_null_void(struct uart_port *port)
1007 {
1008 /* Do nothing */
1009 }
1010
1011 static const struct uart_ops max310x_ops = {
1012 .tx_empty = max310x_tx_empty,
1013 .set_mctrl = max310x_set_mctrl,
1014 .get_mctrl = max310x_get_mctrl,
1015 .stop_tx = max310x_null_void,
1016 .start_tx = max310x_start_tx,
1017 .stop_rx = max310x_null_void,
1018 .break_ctl = max310x_break_ctl,
1019 .startup = max310x_startup,
1020 .shutdown = max310x_shutdown,
1021 .set_termios = max310x_set_termios,
1022 .type = max310x_type,
1023 .request_port = max310x_request_port,
1024 .release_port = max310x_null_void,
1025 .config_port = max310x_config_port,
1026 .verify_port = max310x_verify_port,
1027 };
1028
max310x_suspend(struct device * dev)1029 static int __maybe_unused max310x_suspend(struct device *dev)
1030 {
1031 struct max310x_port *s = dev_get_drvdata(dev);
1032 int i;
1033
1034 for (i = 0; i < s->devtype->nr; i++) {
1035 uart_suspend_port(&max310x_uart, &s->p[i].port);
1036 s->devtype->power(&s->p[i].port, 0);
1037 }
1038
1039 return 0;
1040 }
1041
max310x_resume(struct device * dev)1042 static int __maybe_unused max310x_resume(struct device *dev)
1043 {
1044 struct max310x_port *s = dev_get_drvdata(dev);
1045 int i;
1046
1047 for (i = 0; i < s->devtype->nr; i++) {
1048 s->devtype->power(&s->p[i].port, 1);
1049 uart_resume_port(&max310x_uart, &s->p[i].port);
1050 }
1051
1052 return 0;
1053 }
1054
1055 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1056
1057 #ifdef CONFIG_GPIOLIB
max310x_gpio_get(struct gpio_chip * chip,unsigned offset)1058 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1059 {
1060 unsigned int val;
1061 struct max310x_port *s = gpiochip_get_data(chip);
1062 struct uart_port *port = &s->p[offset / 4].port;
1063
1064 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1065
1066 return !!((val >> 4) & (1 << (offset % 4)));
1067 }
1068
max310x_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1069 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1070 {
1071 struct max310x_port *s = gpiochip_get_data(chip);
1072 struct uart_port *port = &s->p[offset / 4].port;
1073
1074 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1075 value ? 1 << (offset % 4) : 0);
1076 }
1077
max310x_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1078 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1079 {
1080 struct max310x_port *s = gpiochip_get_data(chip);
1081 struct uart_port *port = &s->p[offset / 4].port;
1082
1083 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1084
1085 return 0;
1086 }
1087
max310x_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)1088 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1089 unsigned offset, int value)
1090 {
1091 struct max310x_port *s = gpiochip_get_data(chip);
1092 struct uart_port *port = &s->p[offset / 4].port;
1093
1094 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1095 value ? 1 << (offset % 4) : 0);
1096 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1097 1 << (offset % 4));
1098
1099 return 0;
1100 }
1101 #endif
1102
max310x_probe(struct device * dev,struct max310x_devtype * devtype,struct regmap * regmap,int irq,unsigned long flags)1103 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1104 struct regmap *regmap, int irq, unsigned long flags)
1105 {
1106 int i, ret, fmin, fmax, freq, uartclk;
1107 struct clk *clk_osc, *clk_xtal;
1108 struct max310x_port *s;
1109 bool xtal = false;
1110
1111 if (IS_ERR(regmap))
1112 return PTR_ERR(regmap);
1113
1114 /* Alloc port structure */
1115 s = devm_kzalloc(dev, sizeof(*s) +
1116 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1117 if (!s) {
1118 dev_err(dev, "Error allocating port structure\n");
1119 return -ENOMEM;
1120 }
1121
1122 clk_osc = devm_clk_get(dev, "osc");
1123 clk_xtal = devm_clk_get(dev, "xtal");
1124 if (!IS_ERR(clk_osc)) {
1125 s->clk = clk_osc;
1126 fmin = 500000;
1127 fmax = 35000000;
1128 } else if (!IS_ERR(clk_xtal)) {
1129 s->clk = clk_xtal;
1130 fmin = 1000000;
1131 fmax = 4000000;
1132 xtal = true;
1133 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1134 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1135 return -EPROBE_DEFER;
1136 } else {
1137 dev_err(dev, "Cannot get clock\n");
1138 return -EINVAL;
1139 }
1140
1141 ret = clk_prepare_enable(s->clk);
1142 if (ret)
1143 return ret;
1144
1145 freq = clk_get_rate(s->clk);
1146 /* Check frequency limits */
1147 if (freq < fmin || freq > fmax) {
1148 ret = -ERANGE;
1149 goto out_clk;
1150 }
1151
1152 s->regmap = regmap;
1153 s->devtype = devtype;
1154 dev_set_drvdata(dev, s);
1155
1156 /* Check device to ensure we are talking to what we expect */
1157 ret = devtype->detect(dev);
1158 if (ret)
1159 goto out_clk;
1160
1161 for (i = 0; i < devtype->nr; i++) {
1162 unsigned int offs = i << 5;
1163
1164 /* Reset port */
1165 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1166 MAX310X_MODE2_RST_BIT);
1167 /* Clear port reset */
1168 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1169
1170 /* Wait for port startup */
1171 do {
1172 regmap_read(s->regmap,
1173 MAX310X_BRGDIVLSB_REG + offs, &ret);
1174 } while (ret != 0x01);
1175
1176 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1177 MAX310X_MODE1_AUTOSLEEP_BIT,
1178 MAX310X_MODE1_AUTOSLEEP_BIT);
1179 }
1180
1181 uartclk = max310x_set_ref_clk(s, freq, xtal);
1182 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1183
1184 #ifdef CONFIG_GPIOLIB
1185 /* Setup GPIO cotroller */
1186 s->gpio.owner = THIS_MODULE;
1187 s->gpio.parent = dev;
1188 s->gpio.label = dev_name(dev);
1189 s->gpio.direction_input = max310x_gpio_direction_input;
1190 s->gpio.get = max310x_gpio_get;
1191 s->gpio.direction_output= max310x_gpio_direction_output;
1192 s->gpio.set = max310x_gpio_set;
1193 s->gpio.base = -1;
1194 s->gpio.ngpio = devtype->nr * 4;
1195 s->gpio.can_sleep = 1;
1196 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1197 if (ret)
1198 goto out_clk;
1199 #endif
1200
1201 mutex_init(&s->mutex);
1202
1203 for (i = 0; i < devtype->nr; i++) {
1204 unsigned int line;
1205
1206 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1207 if (line == MAX310X_UART_NRMAX) {
1208 ret = -ERANGE;
1209 goto out_uart;
1210 }
1211
1212 /* Initialize port data */
1213 s->p[i].port.line = line;
1214 s->p[i].port.dev = dev;
1215 s->p[i].port.irq = irq;
1216 s->p[i].port.type = PORT_MAX310X;
1217 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1218 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1219 s->p[i].port.iotype = UPIO_PORT;
1220 s->p[i].port.iobase = i * 0x20;
1221 s->p[i].port.membase = (void __iomem *)~0;
1222 s->p[i].port.uartclk = uartclk;
1223 s->p[i].port.rs485_config = max310x_rs485_config;
1224 s->p[i].port.ops = &max310x_ops;
1225 /* Disable all interrupts */
1226 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1227 /* Clear IRQ status register */
1228 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1229 /* Enable IRQ pin */
1230 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1231 MAX310X_MODE1_IRQSEL_BIT,
1232 MAX310X_MODE1_IRQSEL_BIT);
1233 /* Initialize queue for start TX */
1234 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1235 /* Initialize queue for changing LOOPBACK mode */
1236 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1237 /* Initialize queue for changing RS485 mode */
1238 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1239
1240 /* Register port */
1241 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1242 if (ret) {
1243 s->p[i].port.dev = NULL;
1244 goto out_uart;
1245 }
1246 set_bit(line, max310x_lines);
1247
1248 /* Go to suspend mode */
1249 devtype->power(&s->p[i].port, 0);
1250 }
1251
1252 /* Setup interrupt */
1253 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1254 IRQF_ONESHOT | flags, dev_name(dev), s);
1255 if (!ret)
1256 return 0;
1257
1258 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1259
1260 out_uart:
1261 for (i = 0; i < devtype->nr; i++) {
1262 if (s->p[i].port.dev) {
1263 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1264 clear_bit(s->p[i].port.line, max310x_lines);
1265 }
1266 }
1267
1268 mutex_destroy(&s->mutex);
1269
1270 out_clk:
1271 clk_disable_unprepare(s->clk);
1272
1273 return ret;
1274 }
1275
max310x_remove(struct device * dev)1276 static int max310x_remove(struct device *dev)
1277 {
1278 struct max310x_port *s = dev_get_drvdata(dev);
1279 int i;
1280
1281 for (i = 0; i < s->devtype->nr; i++) {
1282 cancel_work_sync(&s->p[i].tx_work);
1283 cancel_work_sync(&s->p[i].md_work);
1284 cancel_work_sync(&s->p[i].rs_work);
1285 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1286 clear_bit(s->p[i].port.line, max310x_lines);
1287 s->devtype->power(&s->p[i].port, 0);
1288 }
1289
1290 mutex_destroy(&s->mutex);
1291 clk_disable_unprepare(s->clk);
1292
1293 return 0;
1294 }
1295
1296 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1297 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1298 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1299 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1300 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1301 { }
1302 };
1303 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1304
1305 static struct regmap_config regcfg = {
1306 .reg_bits = 8,
1307 .val_bits = 8,
1308 .write_flag_mask = 0x80,
1309 .cache_type = REGCACHE_RBTREE,
1310 .writeable_reg = max310x_reg_writeable,
1311 .volatile_reg = max310x_reg_volatile,
1312 .precious_reg = max310x_reg_precious,
1313 };
1314
1315 #ifdef CONFIG_SPI_MASTER
max310x_spi_probe(struct spi_device * spi)1316 static int max310x_spi_probe(struct spi_device *spi)
1317 {
1318 struct max310x_devtype *devtype;
1319 unsigned long flags = 0;
1320 struct regmap *regmap;
1321 int ret;
1322
1323 /* Setup SPI bus */
1324 spi->bits_per_word = 8;
1325 spi->mode = spi->mode ? : SPI_MODE_0;
1326 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1327 ret = spi_setup(spi);
1328 if (ret)
1329 return ret;
1330
1331 if (spi->dev.of_node) {
1332 const struct of_device_id *of_id =
1333 of_match_device(max310x_dt_ids, &spi->dev);
1334 if (!of_id)
1335 return -ENODEV;
1336
1337 devtype = (struct max310x_devtype *)of_id->data;
1338 } else {
1339 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1340
1341 devtype = (struct max310x_devtype *)id_entry->driver_data;
1342 }
1343
1344 flags = IRQF_TRIGGER_FALLING;
1345 regcfg.max_register = devtype->nr * 0x20 - 1;
1346 regmap = devm_regmap_init_spi(spi, ®cfg);
1347
1348 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1349 }
1350
max310x_spi_remove(struct spi_device * spi)1351 static int max310x_spi_remove(struct spi_device *spi)
1352 {
1353 return max310x_remove(&spi->dev);
1354 }
1355
1356 static const struct spi_device_id max310x_id_table[] = {
1357 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1358 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1359 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1360 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1361 { }
1362 };
1363 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1364
1365 static struct spi_driver max310x_spi_driver = {
1366 .driver = {
1367 .name = MAX310X_NAME,
1368 .of_match_table = of_match_ptr(max310x_dt_ids),
1369 .pm = &max310x_pm_ops,
1370 },
1371 .probe = max310x_spi_probe,
1372 .remove = max310x_spi_remove,
1373 .id_table = max310x_id_table,
1374 };
1375 #endif
1376
max310x_uart_init(void)1377 static int __init max310x_uart_init(void)
1378 {
1379 int ret;
1380
1381 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1382
1383 ret = uart_register_driver(&max310x_uart);
1384 if (ret)
1385 return ret;
1386
1387 #ifdef CONFIG_SPI_MASTER
1388 spi_register_driver(&max310x_spi_driver);
1389 #endif
1390
1391 return 0;
1392 }
1393 module_init(max310x_uart_init);
1394
max310x_uart_exit(void)1395 static void __exit max310x_uart_exit(void)
1396 {
1397 #ifdef CONFIG_SPI_MASTER
1398 spi_unregister_driver(&max310x_spi_driver);
1399 #endif
1400
1401 uart_unregister_driver(&max310x_uart);
1402 }
1403 module_exit(max310x_uart_exit);
1404
1405 MODULE_LICENSE("GPL");
1406 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1407 MODULE_DESCRIPTION("MAX310X serial driver");
1408