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Searched refs:clr (Results 1 – 25 of 61) sorted by relevance

123

/drivers/clocksource/
Dtime-armada-370-xp.c91 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
176 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
181 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
182 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
245 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
264 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
268 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
Dhtc_drv_init.c384 u32 reg_offset, u32 set, u32 clr) in ath9k_reg_rmw_buffer() argument
399 priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].clr = in ath9k_reg_rmw_buffer()
400 cpu_to_be32(clr); in ath9k_reg_rmw_buffer()
467 u32 reg_offset, u32 set, u32 clr) in ath9k_reg_rmw_single() argument
478 buf.clr = cpu_to_be32(clr); in ath9k_reg_rmw_single()
491 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) in ath9k_reg_rmw() argument
501 val &= ~clr; in ath9k_reg_rmw()
509 ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr); in ath9k_reg_rmw()
511 ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr); in ath9k_reg_rmw()
Deeprom_4k.c1009 u32 pwrctrl, mask, clr; in ath9k_hw_4k_set_board_values() local
1013 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1015 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1016 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1017 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1021 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1022 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1026 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1027 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1028 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
/drivers/gpio/
Dgpio-mmio.c439 void __iomem *clr, in bgpio_setup_io() argument
447 if (set && clr) { in bgpio_setup_io()
449 gc->reg_clr = clr; in bgpio_setup_io()
452 } else if (set && !clr) { in bgpio_setup_io()
511 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
530 ret = bgpio_setup_io(gc, dat, set, clr, flags); in bgpio_init()
620 void __iomem *clr; in bgpio_pdev_probe() local
652 clr = bgpio_map(pdev, "clr", sz); in bgpio_pdev_probe()
653 if (IS_ERR(clr)) in bgpio_pdev_probe()
654 return PTR_ERR(clr); in bgpio_pdev_probe()
[all …]
/drivers/staging/media/omap4iss/
Diss.h198 u32 offset, u32 clr) in iss_reg_clr() argument
202 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
233 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
237 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/drivers/staging/sm750fb/
Dsm750_accel.c39 u32 reg, clr; in sm750_hw_de_init() local
46 clr = DE_STRETCH_FORMAT_PATTERN_XY | in sm750_hw_de_init()
54 (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg); in sm750_hw_de_init()
63 clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH | in sm750_hw_de_init()
67 write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr); in sm750_hw_de_init()
/drivers/net/cris/
Deth_v10.c469 IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) | in e100_open()
470 IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) | in e100_open()
471 IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr); in e100_open()
475 IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) | in e100_open()
476 IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) | in e100_open()
477 IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) | in e100_open()
478 IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr); in e100_open()
554 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100_open()
1199 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100nw_interrupt()
1213 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100nw_interrupt()
[all …]
/drivers/irqchip/
Dirq-orion.c55 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_irq_init() local
71 handle_level_irq, clr, 0, in orion_irq_init()
141 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_bridge_irq_init() local
158 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); in orion_bridge_irq_init()
Dirq-digicolor.c75 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in digicolor_of_init() local
106 clr, 0, 0); in digicolor_of_init()
Dirq-zevio.c76 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in zevio_of_init() local
105 clr, 0, IRQ_GC_INIT_MASK_CACHE); in zevio_of_init()
Dirq-sirfsoc.c39 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in sirfsoc_alloc_gc() local
46 handle_level_irq, clr, set, in sirfsoc_alloc_gc()
Dirq-nvic.c89 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in nvic_of_init() local
116 clr, 0, IRQ_GC_INIT_MASK_CACHE); in nvic_of_init()
Dirq-dw-apb-ictl.c71 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in dw_apb_ictl_init() local
132 handle_level_irq, clr, 0, in dw_apb_ictl_init()
Dirq-stm32-exti.c135 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in stm32_exti_init() local
164 handle_edge_irq, clr, 0, 0); in stm32_exti_init()
Dirq-brcmstb-l2.c117 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in brcmstb_l2_intc_of_init() local
166 np->full_name, handle_edge_irq, clr, 0, flags); in brcmstb_l2_intc_of_init()
/drivers/media/platform/xilinx/
Dxilinx-vip.h148 static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr) in xvip_clr() argument
150 xvip_write(xvip, addr, xvip_read(xvip, addr) & ~clr); in xvip_clr()
159 void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set);
Dxilinx-vip.c197 void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set) in xvip_clr_and_set() argument
202 reg &= ~clr; in xvip_clr_and_set()
/drivers/i2c/busses/
Di2c-xiic.c370 u32 clr = 0; in xiic_process() local
415 clr |= XIIC_INTR_RX_FULL_MASK; in xiic_process()
429 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); in xiic_process()
451 clr |= XIIC_INTR_BNB_MASK; in xiic_process()
468 clr |= (pend & in xiic_process()
502 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
504 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
/drivers/video/fbdev/
Dhpfb.c152 u8 clr; in hpfb_fillrect() local
154 clr = region->color & 0xff; in hpfb_fillrect()
160 out_8(fb_regs + TC_WEN, fb_bitmask & clr); in hpfb_fillrect()
164 out_8(fb_regs + TC_WEN, fb_bitmask & ~clr); in hpfb_fillrect()
/drivers/usb/serial/
Dark3116.c458 unsigned set, unsigned clr) in ark3116_tiocmset() argument
477 if (clr & TIOCM_RTS) in ark3116_tiocmset()
479 if (clr & TIOCM_DTR) in ark3116_tiocmset()
481 if (clr & TIOCM_OUT1) in ark3116_tiocmset()
483 if (clr & TIOCM_OUT2) in ark3116_tiocmset()
/drivers/gpu/drm/nouveau/
Dnv50_display.c97 } clr; member
199 } clr; member
278 } clr; member
793 if (asyw->clr.sema && (!asyw->set.sema || flush)) in nv50_wndw_flush_clr()
795 if (asyw->clr.ntfy && (!asyw->set.ntfy || flush)) in nv50_wndw_flush_clr()
797 if (asyw->clr.image && (!asyw->set.image || flush)) in nv50_wndw_flush_clr()
928 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
929 asyw->clr.sema = armw->sema.handle != 0; in nv50_wndw_atomic_check()
931 asyw->clr.image = armw->image.handle != 0; in nv50_wndw_atomic_check()
1021 asyw->clr.mask = 0; in nv50_wndw_atomic_duplicate_state()
[all …]
/drivers/spi/
Dspi-sh-msiof.c214 u32 clr, u32 set) in sh_msiof_modify_ctr_wait() argument
216 u32 mask = clr | set; in sh_msiof_modify_ctr_wait()
221 data &= ~clr; in sh_msiof_modify_ctr_wait()
535 u32 clr, set, tmp; in sh_msiof_spi_setup() local
558 clr = MDR1_SYNCMD_MASK; in sh_msiof_spi_setup()
561 clr |= BIT(MDR1_SYNCAC_SHIFT); in sh_msiof_spi_setup()
565 tmp = sh_msiof_read(p, TMDR1) & ~clr; in sh_msiof_spi_setup()
567 tmp = sh_msiof_read(p, RMDR1) & ~clr; in sh_msiof_spi_setup()
/drivers/usb/phy/
Dphy-isp1301-omap.c544 u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; in otg_update_isp() local
565 clr |= OTG1_DP_PULLDOWN; in otg_update_isp()
576 clr |= OTG1_DP_PULLUP; in otg_update_isp()
582 else clr |= ISP; \ in otg_update_isp()
604 clr |= OTG1_VBUS_DRV; in otg_update_isp()
622 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr); in otg_update_isp()
630 if (clr & OTG1_DP_PULLUP) in otg_update_isp()
636 if (clr & OTG1_DP_PULLUP) in otg_update_isp()
/drivers/tty/serial/
Dsb1250-duart.c265 unsigned int clr = 0, set = 0, mode2; in sbd_set_mctrl() local
270 clr |= M_DUART_CLR_OPR2; in sbd_set_mctrl()
274 clr |= M_DUART_CLR_OPR0; in sbd_set_mctrl()
275 clr <<= (uport->line) % 2; in sbd_set_mctrl()
285 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); in sbd_set_mctrl()

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