| /drivers/misc/cxl/ |
| D | fault.c | 109 ctx->fault_addr = ctx->dar; in cxl_ack_ae()
135 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar) in cxl_handle_mm_fault() argument
157 if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) { in cxl_handle_mm_fault()
171 if (!mm && (REGION_ID(dar) != USER_REGION_ID)) in cxl_handle_mm_fault()
178 hash_page_mm(mm, dar, access, 0x300, inv_flags); in cxl_handle_mm_fault()
186 u64 dsisr, u64 dar) in cxl_handle_page_fault() argument
188 trace_cxl_pte_miss(ctx, dsisr, dar); in cxl_handle_page_fault()
190 if (cxl_handle_mm_fault(mm, dsisr, dar)) { in cxl_handle_page_fault()
248 u64 dar = ctx->dar; in cxl_handle_fault() local
253 cxl_p2n_read(ctx->afu, CXL_PSL_DAR_An) != dar || in cxl_handle_fault()
[all …]
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| D | irq.c | 29 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) in schedule_cxl_fault() argument
32 ctx->dar = dar; in schedule_cxl_fault()
39 u64 dsisr, dar; in cxl_irq_psl9() local
42 dar = irq_info->dar; in cxl_irq_psl9()
44 trace_cxl_psl9_irq(ctx, irq, dsisr, dar); in cxl_irq_psl9()
46 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); in cxl_irq_psl9()
50 return schedule_cxl_fault(ctx, dsisr, dar); in cxl_irq_psl9()
90 u64 dsisr, dar; in cxl_irq_psl8() local
93 dar = irq_info->dar; in cxl_irq_psl8()
95 trace_cxl_psl_irq(ctx, irq, dsisr, dar); in cxl_irq_psl8()
[all …]
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| D | trace.h | 167 TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar),
169 TP_ARGS(ctx, irq, dsisr, dar),
177 __field(u64, dar)
186 __entry->dar = dar;
196 __entry->dar
201 TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar),
203 TP_ARGS(ctx, irq, dsisr, dar),
211 __field(u64, dar)
220 __entry->dar = dar;
229 __entry->dar
[all …]
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| D | cxllib.c | 235 u64 dar, vma_start, vma_end; in cxllib_handle_fault() local
251 for (dar = (addr & ~(page_size - 1)); dar < (addr + size); in cxllib_handle_fault()
252 dar += page_size) { in cxllib_handle_fault()
253 if (dar < vma_start || dar >= vma_end) { in cxllib_handle_fault()
268 rc = get_vma_info(mm, dar, &vma_start, &vma_end, in cxllib_handle_fault()
274 rc = cxl_handle_mm_fault(mm, flags, dar); in cxllib_handle_fault()
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| D | native.c | 137 u64 dsisr, dar; in cxl_psl_purge() local
184 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); in cxl_psl_purge()
186 dsisr, dar); in cxl_psl_purge()
1077 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); in native_get_irq_info()
1196 irq_info.dar); in native_irq_multiplexed()
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| D | cxl.h | 588 u64 dar; member
1017 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
1045 u64 dar; member
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| D | hcalls.c | 417 info->dsisr, info->dar, info->dsr, info->reserved, in cxl_h_collect_int_info()
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| /drivers/dma/ |
| D | idma64.c | 239 u64 sar, dar; in idma64_hw_desc_fill() local
246 dar = config->dst_addr; in idma64_hw_desc_fill()
253 dar = hw->phys; in idma64_hw_desc_fill()
257 dst_width = __ffs(dar | hw->len | 4); in idma64_hw_desc_fill()
261 lli->dar = dar; in idma64_hw_desc_fill()
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| D | idma64.h | 101 u64 dar; member
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| D | fsldma.h | 117 u64 dar; /* 0x18 - Destination Address Register */ member
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| /drivers/dma/sh/ |
| D | shdma.h | 50 u32 dar; /* DAR / destination address */ member
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| D | shdmac.c | 222 sh_dmae_writel(sh_chan, hw->dar, DAR); in dmae_set_reg()
295 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); in sh_dmae_start_xfer()
392 sh_desc->hw.dar = dst; in sh_dmae_desc_setup()
470 (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || in sh_dmae_desc_completed()
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| D | rcar-dmac.c | 52 u32 dar; member
734 hwdesc->dar = chunk->dst_addr; in rcar_dmac_fill_hwdesc()
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| /drivers/staging/comedi/drivers/ |
| D | mite.h | 35 u32 dar; member
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| /drivers/dma/dw/ |
| D | core.c | 265 channel_writel(dwc, DAR, lli_read(desc, dar)); in dwc_do_single_block()
517 lli_read(desc, dar), in dwc_dump_lli()
684 lli_write(desc, dar, dest + offset); in dwc_prep_dma_memcpy()
772 lli_write(desc, dar, reg); in dwc_prep_slave_sg()
818 lli_write(desc, dar, mem); in dwc_prep_slave_sg()
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| D | regs.h | 348 __le32 dar; member
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