| /drivers/clk/berlin/ |
| D | berlin2-div.c | 77 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
78 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
81 if (div->lock) in berlin2_div_is_enabled()
82 spin_lock(div->lock); in berlin2_div_is_enabled()
84 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
87 if (div->lock) in berlin2_div_is_enabled()
88 spin_unlock(div->lock); in berlin2_div_is_enabled()
95 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
96 struct berlin2_div_map *map = &div->map; in berlin2_div_enable()
99 if (div->lock) in berlin2_div_enable()
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| /drivers/clk/ti/ |
| D | divider.c | 36 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
37 if (clkt->div > maxdiv) in _get_table_maxdiv()
38 maxdiv = clkt->div; in _get_table_maxdiv()
58 for (clkt = table; clkt->div; clkt++) in _get_table_div()
60 return clkt->div; in _get_table_div()
76 unsigned int div) in _get_table_val() argument
80 for (clkt = table; clkt->div; clkt++) in _get_table_val()
81 if (clkt->div == div) in _get_table_val()
86 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
89 return div; in _get_val()
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| /drivers/clk/ |
| D | clk-divider.c | 39 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
40 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
41 maxdiv = clkt->div; in _get_table_maxdiv()
50 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
51 if (clkt->div < mindiv) in _get_table_mindiv()
52 mindiv = clkt->div; in _get_table_mindiv()
73 for (clkt = table; clkt->div; clkt++) in _get_table_div()
75 return clkt->div; in _get_table_div()
94 unsigned int div) in _get_table_val() argument
98 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| D | clk-cdce706.c | 32 #define CDCE706_DIVIDER(div) (13 + (div)) argument
53 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
54 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
55 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
75 unsigned div; member
172 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
175 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
178 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
182 if (hwd->div) in cdce706_pll_recalc_rate()
183 return parent_rate / hwd->div; in cdce706_pll_recalc_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sunxi.c | 43 u8 div; in sun4i_get_pll1_factors() local
46 div = req->rate / 6000000; in sun4i_get_pll1_factors()
47 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
60 if (div < 10) in sun4i_get_pll1_factors()
64 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
69 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
77 div <<= req->p; in sun4i_get_pll1_factors()
78 div /= (req->k + 1); in sun4i_get_pll1_factors()
79 req->n = div / 4; in sun4i_get_pll1_factors()
167 u8 div; in sun8i_a23_get_pll1_factors() local
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| D | clk-sun9i-cpus.c | 35 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
36 (div << SUN9I_CPUS_DIV_SHIFT))
41 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
42 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
74 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
83 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
86 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
88 if (div < 32) { in sun9i_a80_cpus_clk_round()
89 pre_div = div; in sun9i_a80_cpus_clk_round()
90 div = 1; in sun9i_a80_cpus_clk_round()
[all …]
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| D | clk-sun6i-ar100.c | 28 unsigned long div; in sun6i_get_ar100_factors() local
35 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ar100_factors()
37 if (div < 32) in sun6i_get_ar100_factors()
39 else if (div >> 1 < 32) in sun6i_get_ar100_factors()
41 else if (div >> 2 < 32) in sun6i_get_ar100_factors()
46 div >>= shift; in sun6i_get_ar100_factors()
48 if (div > 32) in sun6i_get_ar100_factors()
49 div = 32; in sun6i_get_ar100_factors()
51 req->rate = (req->parent_rate >> shift) / div; in sun6i_get_ar100_factors()
52 req->m = div - 1; in sun6i_get_ar100_factors()
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| /drivers/clk/mxs/ |
| D | clk-div.c | 44 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
52 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
54 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
60 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
65 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
79 struct clk_div *div; in mxs_clk_div() local
83 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
84 if (!div) in mxs_clk_div()
[all …]
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| /drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 32 struct iproc_asiu_div div; member
92 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
93 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
114 unsigned int div; in iproc_asiu_clk_round_rate() local
122 div = DIV_ROUND_UP(*parent_rate, rate); in iproc_asiu_clk_round_rate()
123 if (div < 2) in iproc_asiu_clk_round_rate()
126 return *parent_rate / div; in iproc_asiu_clk_round_rate()
134 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
[all …]
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| D | clk-kona.c | 57 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
59 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
67 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build() argument
75 combined <<= div->u.s.frac_width; in scaled_div_build()
82 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
84 if (divider_is_fixed(div)) in scaled_div_min()
85 return (u64)div->u.fixed; in scaled_div_min()
87 return scaled_div_value(div, 0); in scaled_div_min()
91 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max() argument
95 if (divider_is_fixed(div)) in scaled_div_max()
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| D | clk-kona-setup.c | 55 struct bcm_clk_div *div; in clk_requires_trigger() local
64 div = &peri->div; in clk_requires_trigger()
65 if (!divider_exists(div)) in clk_requires_trigger()
69 if (!divider_is_fixed(div)) in clk_requires_trigger()
72 div = &peri->pre_div; in clk_requires_trigger()
74 return divider_exists(div) && !divider_is_fixed(div); in clk_requires_trigger()
83 struct bcm_clk_div *div; in peri_clk_data_offsets_valid() local
129 div = &peri->div; in peri_clk_data_offsets_valid()
130 if (divider_exists(div)) { in peri_clk_data_offsets_valid()
131 if (div->u.s.offset > limit) { in peri_clk_data_offsets_valid()
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| /drivers/clk/spear/ |
| D | spear1340_clock.c | 191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
243 {.div = 0x08000},
244 {.div = 0x06a38},
245 {.div = 0x06666},
246 {.div = 0x06000},
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| /drivers/media/platform/sti/hva/ |
| D | hva-debugfs.c | 121 u64 div; in hva_dbg_perf_begin() local
131 div = (u64)ktime_us_delta(dbg->begin, prev); in hva_dbg_perf_begin()
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
152 div = (u64)dbg->window_stream_size * 80; in hva_dbg_perf_begin()
153 do_div(div, dbg->window_duration); in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
187 div = stream->vbuf.vb2_buf.timestamp; in hva_dbg_perf_end()
188 do_div(div, 1000); in hva_dbg_perf_end()
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| /drivers/clk/ingenic/ |
| D | cgu.c | 319 u32 div_reg, div; in ingenic_clk_recalc_rate() local
324 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
325 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
326 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
327 div += 1; in ingenic_clk_recalc_rate()
328 div *= clk_info->div.div; in ingenic_clk_recalc_rate()
330 rate /= div; in ingenic_clk_recalc_rate()
340 unsigned div; in ingenic_clk_calc_div() local
343 div = DIV_ROUND_UP(parent_rate, req_rate); in ingenic_clk_calc_div()
346 div = min_t(unsigned, div, 1 << clk_info->div.bits); in ingenic_clk_calc_div()
[all …]
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| /drivers/clk/tegra/ |
| D | clk-divider.c | 71 int div, mul; in clk_frac_div_recalc_rate() local
75 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
78 div += mul; in clk_frac_div_recalc_rate()
81 rate += div - 1; in clk_frac_div_recalc_rate()
82 do_div(rate, div); in clk_frac_div_recalc_rate()
91 int div, mul; in clk_frac_div_round_rate() local
97 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
98 if (div < 0) in clk_frac_div_round_rate()
103 return DIV_ROUND_UP(output_rate * mul, div + mul); in clk_frac_div_round_rate()
110 int div; in clk_frac_div_set_rate() local
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| /drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 108 struct hi6220_clk_divider *div; in hi6220_register_clkdiv() local
116 div = kzalloc(sizeof(*div), GFP_KERNEL); in hi6220_register_clkdiv()
117 if (!div) in hi6220_register_clkdiv()
126 kfree(div); in hi6220_register_clkdiv()
131 table[i].div = min_div + i; in hi6220_register_clkdiv()
132 table[i].val = table[i].div - 1; in hi6220_register_clkdiv()
142 div->reg = reg; in hi6220_register_clkdiv()
143 div->shift = shift; in hi6220_register_clkdiv()
144 div->width = width; in hi6220_register_clkdiv()
145 div->mask = mask_bit ? BIT(mask_bit) : 0; in hi6220_register_clkdiv()
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| /drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 48 .div = (sd_div), \
53 unsigned int div; member
130 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
137 unsigned int div; in cpg_sd_clock_calc_div() local
142 div = DIV_ROUND_CLOSEST(parent_rate, rate); in cpg_sd_clock_calc_div()
144 return clamp_t(unsigned int, div, clock->div_min, clock->div_max); in cpg_sd_clock_calc_div()
151 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); in cpg_sd_clock_round_rate() local
153 return DIV_ROUND_CLOSEST(*parent_rate, div); in cpg_sd_clock_round_rate()
160 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); in cpg_sd_clock_set_rate() local
165 if (div == clock->div_table[i].div) in cpg_sd_clock_set_rate()
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| /drivers/pwm/ |
| D | pwm-rcar.c | 75 unsigned int div; in rcar_pwm_get_clock_division() local
80 for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) { in rcar_pwm_get_clock_division()
82 (1 << div); in rcar_pwm_get_clock_division()
88 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; in rcar_pwm_get_clock_division()
92 unsigned int div) in rcar_pwm_set_clock_control() argument
99 if (div & 1) in rcar_pwm_set_clock_control()
102 div >>= 1; in rcar_pwm_set_clock_control()
104 value |= div << RCAR_PWMCR_CC0_SHIFT; in rcar_pwm_set_clock_control()
108 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns, in rcar_pwm_set_counter() argument
115 one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div); in rcar_pwm_set_counter()
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| /drivers/media/i2c/ |
| D | aptina-pll.c | 33 unsigned int div; in aptina_pll_calculate() local
50 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
51 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
52 div = pll->ext_clock / div; in aptina_pll_calculate()
67 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); in aptina_pll_calculate()
71 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); in aptina_pll_calculate()
136 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, in aptina_pll_calculate()
138 p1_max = min(limits->p1_max, limits->out_clock_max * div / in aptina_pll_calculate()
142 unsigned int mf_inc = p1 / gcd(div, p1); in aptina_pll_calculate()
147 limits->int_clock_max * div)), mf_inc); in aptina_pll_calculate()
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| /drivers/clk/sunxi-ng/ |
| D | ccu_div.c | 29 cd->div.table, cd->div.width, in ccu_div_round_rate()
30 cd->div.flags); in ccu_div_round_rate()
67 val = reg >> cd->div.shift; in ccu_div_recalc_rate()
68 val &= (1 << cd->div.width) - 1; in ccu_div_recalc_rate()
73 val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, in ccu_div_recalc_rate()
74 cd->div.flags, cd->div.width); in ccu_div_recalc_rate()
105 val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, in ccu_div_set_rate()
106 cd->div.flags); in ccu_div_set_rate()
111 reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); in ccu_div_set_rate()
113 writel(reg | (val << cd->div.shift), in ccu_div_set_rate()
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| /drivers/clk/mvebu/ |
| D | orion.c | 62 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
68 *div = 2; in mv88f5181_get_clk_ratio()
71 *div = 3; in mv88f5181_get_clk_ratio()
74 *div = 1; in mv88f5181_get_clk_ratio()
130 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
136 *div = 2; in mv88f5182_get_clk_ratio()
139 *div = 3; in mv88f5182_get_clk_ratio()
142 *div = 1; in mv88f5182_get_clk_ratio()
187 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
193 *div = 2; in mv88f5281_get_clk_ratio()
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| /drivers/media/tuners/ |
| D | tea5767.c | 138 unsigned int div, frq; in tea5767_status_dump() local
150 div = ((buffer[0] & 0x3f) << 8) | buffer[1]; in tea5767_status_dump()
154 frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
157 frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
160 frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
164 frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */ in tea5767_status_dump()
167 buffer[0] = (div >> 8) & 0x3f; in tea5767_status_dump()
168 buffer[1] = div & 0xff; in tea5767_status_dump()
171 frq / 1000, frq % 1000, div); in tea5767_status_dump()
196 unsigned div; in set_radio_freq() local
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| /drivers/mmc/host/ |
| D | sdhci-cns3xxx.c | 29 int div = 1; in sdhci_cns3xxx_set_clock() local
40 while (host->max_clk / div > clock) { in sdhci_cns3xxx_set_clock()
45 if (div < 4) in sdhci_cns3xxx_set_clock()
46 div += 1; in sdhci_cns3xxx_set_clock()
47 else if (div < 256) in sdhci_cns3xxx_set_clock()
48 div *= 2; in sdhci_cns3xxx_set_clock()
54 clock, host->max_clk / div); in sdhci_cns3xxx_set_clock()
57 if (div != 3) in sdhci_cns3xxx_set_clock()
58 div >>= 1; in sdhci_cns3xxx_set_clock()
60 clk = div << SDHCI_DIVIDER_SHIFT; in sdhci_cns3xxx_set_clock()
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| /drivers/clk/samsung/ |
| D | clk-s3c2443.c | 126 { .val = 0, .div = 1 },
127 { .val = 1, .div = 2 },
128 { .val = 3, .div = 4 },
133 { .val = 0, .div = 1 },
134 { .val = 1, .div = 3 },
135 { .val = 2, .div = 5 },
136 { .val = 3, .div = 7 },
137 { .val = 4, .div = 9 },
138 { .val = 5, .div = 11 },
139 { .val = 6, .div = 13 },
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| /drivers/clk/rockchip/ |
| D | clk.c | 57 struct clk_divider *div = NULL; in rockchip_clk_register_branch() local
88 div = kzalloc(sizeof(*div), GFP_KERNEL); in rockchip_clk_register_branch()
89 if (!div) in rockchip_clk_register_branch()
92 div->flags = div_flags; in rockchip_clk_register_branch()
93 div->reg = base + muxdiv_offset; in rockchip_clk_register_branch()
94 div->shift = div_shift; in rockchip_clk_register_branch()
95 div->width = div_width; in rockchip_clk_register_branch()
96 div->lock = lock; in rockchip_clk_register_branch()
97 div->table = div_table; in rockchip_clk_register_branch()
105 div ? &div->hw : NULL, div_ops, in rockchip_clk_register_branch()
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