| /drivers/gpu/drm/amd/amdgpu/ |
| D | nbio_v7_0.c | 83 bool use_doorbell, int doorbell_index) in nbio_v7_0_sdma_doorbell_range() argument
88 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_sdma_doorbell_range()
103 bool use_doorbell, int doorbell_index) in nbio_v7_0_ih_doorbell_range() argument
108 …h_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_ih_doorbell_range()
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| D | nbio_v7_0.h | 40 bool use_doorbell, int doorbell_index);
44 bool use_doorbell, int doorbell_index);
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| D | nbio_v6_1.c | 86 bool use_doorbell, int doorbell_index) in nbio_v6_1_sdma_doorbell_range() argument
91 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_sdma_doorbell_range()
126 bool use_doorbell, int doorbell_index) in nbio_v6_1_ih_doorbell_range() argument
131 …h_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_ih_doorbell_range()
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| D | nbio_v6_1.h | 40 bool use_doorbell, int doorbell_index);
46 bool use_doorbell, int doorbell_index);
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| D | vega10_ih.c | 146 OFFSET, adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
155 nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
157 nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
287 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in vega10_ih_set_rptr()
311 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; in vega10_ih_sw_init()
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| D | tonga_ih.c | 153 OFFSET, adev->irq.ih.doorbell_index); in tonga_ih_irq_init()
267 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in tonga_ih_set_rptr()
297 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH; in tonga_ih_sw_init()
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| D | amdgpu_ih.h | 86 u32 doorbell_index; member
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| D | sdma_v4_0.c | 306 ring->doorbell_index, ring->wptr << 2); in sdma_v4_0_ring_set_wptr()
307 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v4_0_ring_set_wptr()
636 OFFSET, ring->doorbell_index); in sdma_v4_0_gfx_resume()
643 nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); in sdma_v4_0_gfx_resume()
645 nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); in sdma_v4_0_gfx_resume()
1242 ring->doorbell_index = (i == 0) ? in sdma_v4_0_sw_init()
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| D | vce_v4_0.c | 107 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
176 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
454 ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2; in vce_v4_0_sw_init()
456 ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1; in vce_v4_0_sw_init()
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| D | amdgpu_ring.h | 179 u32 doorbell_index; member
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| D | uvd_v7_0.c | 143 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
448 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; in uvd_v7_0_sw_init()
450 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; in uvd_v7_0_sw_init()
697 WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0); in uvd_v7_0_mmsch_start()
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| D | amdgpu_gfx.c | 197 ring->doorbell_index = AMDGPU_DOORBELL_KIQ; in amdgpu_gfx_kiq_init_ring()
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| D | gfx_v9_0.c | 1222 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; in gfx_v9_0_compute_ring_init()
1311 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; in gfx_v9_0_sw_init()
2246 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_cp_gfx_resume()
2255 DOORBELL_RANGE_LOWER, ring->doorbell_index); in gfx_v9_0_cp_gfx_resume()
2405 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx_v9_0_kiq_kcq_enable()
2464 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_mqd_init()
2530 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_mqd_init()
3478 WDOORBELL64(ring->doorbell_index, ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
3670 WDOORBELL64(ring->doorbell_index, ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
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| D | sdma_v3_0.c | 384 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
703 OFFSET, ring->doorbell_index); in sdma_v3_0_gfx_resume()
1201 ring->doorbell_index = (i == 0) ? in sdma_v3_0_sw_init()
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| D | gfx_v8_0.c | 1872 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; in gfx_v8_0_compute_ring_init()
1969 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; in gfx_v8_0_sw_init()
4305 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v8_0_set_cpg_door_bell()
4517 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) | in gfx_v8_0_kiq_kcq_enable()
4653 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v8_0_mqd_init()
6113 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6319 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_compute()
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| D | gfx_v7_0.c | 2681 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_compute()
2997 (ring->doorbell_index << in gfx_v7_0_mqd_init()
4499 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; in gfx_v7_0_compute_ring_init()
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| D | gfx_v6_0.c | 3188 ring->doorbell_index = 0; in gfx_v6_0_sw_init()
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| /drivers/gpu/drm/radeon/ |
| D | cik.c | 4206 WDOORBELL32(ring->doorbell_index, ring->wptr); in cik_compute_set_wptr()
4725 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index); in cik_cp_compute_resume()
8632 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8639 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
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| D | radeon.h | 868 u32 doorbell_index; member
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