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Searched refs:fbc (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_fbc.c129 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in i8xx_fbc_activate()
177 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in g4x_fbc_activate()
223 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in ilk_fbc_activate()
225 int threshold = dev_priv->fbc.threshold; in ilk_fbc_activate()
290 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in gen7_fbc_activate()
292 int threshold = dev_priv->fbc.threshold; in gen7_fbc_activate()
325 if (dev_priv->fbc.false_color) in gen7_fbc_activate()
357 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_hw_activate() local
359 fbc->active = true; in intel_fbc_hw_activate()
373 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_hw_deactivate() local
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Dintel_pm.c956 FW_WM(wm->sr.fbc, FBC_SR) | in g4x_write_wm_values()
957 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | in g4x_write_wm_values()
1195 dirty |= raw->fbc != value; in g4x_raw_fbc_wm_set()
1196 raw->fbc = value; in g4x_raw_fbc_wm_set()
1250 dirty |= raw->fbc != wm; in g4x_raw_plane_wm_compute()
1251 raw->fbc = wm; in g4x_raw_plane_wm_compute()
1270 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1271 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); in g4x_raw_plane_wm_compute()
1313 wm_state->sr.fbc = USHRT_MAX; in g4x_invalidate_wms()
1320 wm_state->hpll.fbc = USHRT_MAX; in g4x_invalidate_wms()
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Di915_trace.h112 __field(bool, fbc)
125 __entry->sr_fbc = wm->sr.fbc;
128 __entry->hpll_fbc = wm->hpll.fbc;
131 __entry->fbc = wm->fbc_en;
139 yesno(__entry->fbc))
Di915_debugfs.c1621 mutex_lock(&dev_priv->fbc.lock); in i915_fbc_status()
1627 dev_priv->fbc.no_fbc_reason); in i915_fbc_status()
1647 mutex_unlock(&dev_priv->fbc.lock); in i915_fbc_status()
1660 *val = dev_priv->fbc.false_color; in i915_fbc_false_color_get()
1673 mutex_lock(&dev_priv->fbc.lock); in i915_fbc_false_color_set()
1676 dev_priv->fbc.false_color = val; in i915_fbc_false_color_set()
1682 mutex_unlock(&dev_priv->fbc.lock); in i915_fbc_false_color_set()
Di915_drv.h1748 uint16_t fbc; member
1754 uint16_t fbc; member
2228 struct intel_fbc fbc; member
Di915_reg.h5766 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ argument
5768 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
/drivers/video/fbdev/
Dcg6.c257 struct cg6_fbc __iomem *fbc; member
271 struct cg6_fbc __iomem *fbc = par->fbc; in cg6_sync() local
275 if (!(sbus_readl(&fbc->s) & 0x10000000)) in cg6_sync()
319 struct cg6_fbc __iomem *fbc = par->fbc; in cg6_fillrect() local
329 sbus_writel(rect->color, &fbc->fg); in cg6_fillrect()
330 sbus_writel(~(u32)0, &fbc->pixelm); in cg6_fillrect()
331 sbus_writel(0xea80ff00, &fbc->alu); in cg6_fillrect()
332 sbus_writel(0, &fbc->s); in cg6_fillrect()
333 sbus_writel(0, &fbc->clip); in cg6_fillrect()
334 sbus_writel(~(u32)0, &fbc->pm); in cg6_fillrect()
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Dffb.c241 u32 fbc; member
353 struct ffb_fbc __iomem *fbc; member
377 struct ffb_fbc __iomem *fbc; in FFBFifo() local
381 fbc = par->fbc; in FFBFifo()
383 cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK); in FFBFifo()
392 struct ffb_fbc __iomem *fbc; in FFBWait() local
395 fbc = par->fbc; in FFBWait()
397 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0) in FFBWait()
399 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) { in FFBWait()
400 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr); in FFBWait()
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