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Searched refs:hw_caps (Results 1 – 25 of 25) sorted by relevance

/drivers/net/wireless/ath/ath9k/
Dcommon-init.c134 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { in ath9k_cmn_init_channels_rates()
151 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { in ath9k_cmn_init_channels_rates()
185 if (ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) in ath9k_cmn_setup_ht_cap()
188 if (ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) in ath9k_cmn_setup_ht_cap()
234 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_HT)) in ath9k_cmn_reload_chainmask()
237 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) in ath9k_cmn_reload_chainmask()
240 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) in ath9k_cmn_reload_chainmask()
Dgpio.c129 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath_start_rfkill_poll()
214 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) { in ath_btcoex_period_timer()
219 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) in ath_btcoex_period_timer()
225 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) { in ath_btcoex_period_timer()
265 (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && in ath_btcoex_no_stomp_timer()
351 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit) in ath9k_btcoex_aggr_limit()
374 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) in ath9k_start_btcoex()
395 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) in ath9k_stop_btcoex()
Dar9002_mac.c81 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
87 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) in ar9002_hw_get_isr()
108 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { in ar9002_hw_get_isr()
140 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { in ar9002_hw_get_isr()
156 !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ar9002_hw_get_isr()
159 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
165 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9002_hw_get_isr()
Dinit.c259 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { in ath_descdma_setup()
296 if (!(sc->sc_ah->caps.hw_caps & in ath_descdma_setup()
327 if (!(sc->sc_ah->caps.hw_caps & in ath_descdma_setup()
381 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) in ath9k_init_misc()
442 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; in ath9k_init_pcoem_platform()
446 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; in ath9k_init_pcoem_platform()
668 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) in ath9k_init_softc()
763 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) in ath9k_init_txpower_limits()
765 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) in ath9k_init_txpower_limits()
880 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { in ath9k_set_hw_capab()
[all …]
Dhw.c53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
1526 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { in ath9k_hw_channel_change()
1787 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && in ath9k_hw_do_fastcc()
1976 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
2119 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_set_power_network_sleep()
2342 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) in ath9k_hw_set_sta_beacon_timers()
2488 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; in ath9k_hw_fill_cap_info()
2495 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; in ath9k_hw_fill_cap_info()
2498 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { in ath9k_hw_fill_cap_info()
2550 pCap->hw_caps |= ATH9K_HW_CAP_HT; in ath9k_hw_fill_cap_info()
[all …]
Dar9003_mac.c233 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
239 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) in ar9003_hw_get_isr()
266 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
281 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) in ar9003_hw_get_isr()
295 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
304 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { in ar9003_hw_get_isr()
Drecv.c26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); in ath9k_check_auto_sleep()
283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath_rx_init()
338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath_rx_cleanup()
445 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath_startrecv()
474 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath_flushrecv()
490 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath_stoprecv()
965 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)) in ath9k_antenna_check()
979 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) { in ath9k_antenna_check()
1080 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); in ath_rx_tasklet()
Dmain.c435 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath9k_tasklet()
443 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && in ath9k_tasklet()
451 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath9k_tasklet()
567 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ath_isr()
690 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath9k_start()
706 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) in ath9k_start()
775 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ath9k_tx()
1368 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_enable_ps()
1388 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_disable_ps()
2146 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); in ath9k_tx_last_beacon()
Ddfs_debug.c50 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ? in read_file_dfs()
Dmac.c751 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath9k_hw_beaconq_setup()
915 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ath9k_hw_set_interrupts()
970 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_hw_set_interrupts()
Dhw.h295 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ member
468 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
1158 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); in ath9k_hw_mci_is_enabled()
Ddebug.c258 if (!(pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) in write_file_bt_ant_diversity()
321 if (!(pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)) { in read_file_antenna_diversity()
478 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath_debug_stat_interrupt()
538 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in read_file_interrupt()
Dhtc_drv_gpio.c332 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_start_rfkill_poll()
Dar9003_calib.c1310 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal) in ar9003_hw_do_pcoem_manual_peak_cal()
1322 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) { in ar9003_hw_do_pcoem_manual_peak_cal()
1404 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); in ar9003_hw_init_cal_pcoem()
Dxmit.c893 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) in ath_compute_num_delims()
1765 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath_txq_setup()
1883 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { in ath_draintxq()
2060 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); in ath_tx_txqaddbuf()
2197 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && in ath_txchainmask_reduction()
2857 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath_tx_init()
Dhtc_drv_init.c767 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) in ath9k_set_hw_capab()
770 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) in ath9k_set_hw_capab()
Dbtcoex.c150 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) { in ath9k_hw_btcoex_init_scheme()
Dmci.c638 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) in ath_mci_enable()
Dbeacon.c395 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); in ath9k_beacon_tasklet()
Dar9003_phy.c703 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
1638 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_set_bt_ant_diversity()
Dar9003_paprd.c1008 if ((ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->config.enable_paprd) in ar9003_is_paprd_enabled()
Deeprom_4k.c806 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ath9k_hw_4k_set_board_values()
Dar9003_eeprom.c3708 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_ant_ctrl_apply()
/drivers/memory/
Demif.c1035 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { in emif_interrupt_handler()
1085 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) in clear_all_interrupts()
1097 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) in disable_and_clear_all_interrupts()
1121 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { in setup_interrupts()
1380 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE; in of_get_memory_device_details()
/drivers/gpu/drm/amd/powerplay/inc/
Dhardwaremanager.h245 uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; member