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Searched refs:mec_int_cntl_reg (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c4829 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4840 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4843 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4846 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4849 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4862 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4864 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4867 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4869 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c3856 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
3867 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
3870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
3873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
3876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
3889 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
3892 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
3895 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
3898 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6471 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6482 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6485 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6488 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6491 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6504 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6506 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6509 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6511 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()