| /drivers/clk/imx/ |
| D | clk-pllv3.c | 116 unsigned long parent_rate) in clk_pllv3_recalc_rate() argument
121 return (div == 1) ? parent_rate * 22 : parent_rate * 20; in clk_pllv3_recalc_rate()
127 unsigned long parent_rate = *prate; in clk_pllv3_round_rate() local
129 return (rate >= parent_rate * 22) ? parent_rate * 22 : in clk_pllv3_round_rate()
130 parent_rate * 20; in clk_pllv3_round_rate()
134 unsigned long parent_rate) in clk_pllv3_set_rate() argument
139 if (rate == parent_rate * 22) in clk_pllv3_set_rate()
141 else if (rate == parent_rate * 20) in clk_pllv3_set_rate()
164 unsigned long parent_rate) in clk_pllv3_sys_recalc_rate() argument
169 return parent_rate * div / 2; in clk_pllv3_sys_recalc_rate()
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| /drivers/clk/at91/ |
| D | clk-h32mx.c | 34 unsigned long parent_rate) in clk_sama5d4_h32mx_recalc_rate() argument
41 return parent_rate / 2; in clk_sama5d4_h32mx_recalc_rate()
43 if (parent_rate > H32MX_MAX_FREQ) in clk_sama5d4_h32mx_recalc_rate()
45 return parent_rate; in clk_sama5d4_h32mx_recalc_rate()
49 unsigned long *parent_rate) in clk_sama5d4_h32mx_round_rate() argument
53 if (rate > *parent_rate) in clk_sama5d4_h32mx_round_rate()
54 return *parent_rate; in clk_sama5d4_h32mx_round_rate()
55 div = *parent_rate / 2; in clk_sama5d4_h32mx_round_rate()
59 if (rate - div < *parent_rate - rate) in clk_sama5d4_h32mx_round_rate()
62 return *parent_rate; in clk_sama5d4_h32mx_round_rate()
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| D | clk-plldiv.c | 28 unsigned long parent_rate) in clk_plldiv_recalc_rate() argument
36 return parent_rate / 2; in clk_plldiv_recalc_rate()
38 return parent_rate; in clk_plldiv_recalc_rate()
42 unsigned long *parent_rate) in clk_plldiv_round_rate() argument
46 if (rate > *parent_rate) in clk_plldiv_round_rate()
47 return *parent_rate; in clk_plldiv_round_rate()
48 div = *parent_rate / 2; in clk_plldiv_round_rate()
52 if (rate - div < *parent_rate - rate) in clk_plldiv_round_rate()
55 return *parent_rate; in clk_plldiv_round_rate()
59 unsigned long parent_rate) in clk_plldiv_set_rate() argument
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| D | clk-audio-pll.c | 162 static unsigned long clk_audio_pll_fout(unsigned long parent_rate, in clk_audio_pll_fout() argument
165 unsigned long long fr = (unsigned long long)parent_rate * fracr; in clk_audio_pll_fout()
173 return parent_rate * (nd + 1) + fr; in clk_audio_pll_fout()
177 unsigned long parent_rate) in clk_audio_pll_frac_recalc_rate() argument
182 fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); in clk_audio_pll_frac_recalc_rate()
191 unsigned long parent_rate) in clk_audio_pll_pad_recalc_rate() argument
197 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); in clk_audio_pll_pad_recalc_rate()
206 unsigned long parent_rate) in clk_audio_pll_pmc_recalc_rate() argument
211 apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); in clk_audio_pll_pmc_recalc_rate()
220 unsigned long parent_rate, in clk_audio_pll_frac_compute_frac() argument
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| D | clk-smd.c | 34 unsigned long parent_rate) in at91sam9x5_clk_smd_recalc_rate() argument
43 return parent_rate / (smddiv + 1); in at91sam9x5_clk_smd_recalc_rate()
47 unsigned long *parent_rate) in at91sam9x5_clk_smd_round_rate() argument
53 if (rate >= *parent_rate) in at91sam9x5_clk_smd_round_rate()
54 return *parent_rate; in at91sam9x5_clk_smd_round_rate()
56 div = *parent_rate / rate; in at91sam9x5_clk_smd_round_rate()
58 return *parent_rate / (SMD_MAX_DIV + 1); in at91sam9x5_clk_smd_round_rate()
60 bestrate = *parent_rate / div; in at91sam9x5_clk_smd_round_rate()
61 tmp = *parent_rate / (div + 1); in at91sam9x5_clk_smd_round_rate()
92 unsigned long parent_rate) in at91sam9x5_clk_smd_set_rate() argument
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| /drivers/clk/meson/ |
| D | clk-audio-divider.c | 34 static int _div_round(unsigned long parent_rate, unsigned long rate, in _div_round() argument
38 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate); in _div_round()
40 return DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round()
43 static int _get_val(unsigned long parent_rate, unsigned long rate) in _get_val() argument
45 return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; in _get_val()
62 unsigned long parent_rate) in audio_divider_recalc_rate() argument
73 return DIV_ROUND_UP_ULL((u64)parent_rate, divider); in audio_divider_recalc_rate()
78 unsigned long *parent_rate) in audio_divider_round_rate() argument
86 divider = _div_round(*parent_rate, rate, adiv->flags); in audio_divider_round_rate()
88 return DIV_ROUND_UP_ULL((u64)*parent_rate, divider); in audio_divider_round_rate()
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| D | gxbb-aoclk-32k.c | 45 unsigned long parent_rate; member
56 .parent_rate = 24000000,
75 unsigned long parent_rate) in aoclk_cec_32k_recalc_rate() argument
85 return parent_rate; in aoclk_cec_32k_recalc_rate()
96 f1 = DIV_ROUND_CLOSEST(parent_rate, n1); in aoclk_cec_32k_recalc_rate()
97 f2 = DIV_ROUND_CLOSEST(parent_rate, n2); in aoclk_cec_32k_recalc_rate()
107 return DIV_ROUND_CLOSEST(parent_rate, n1); in aoclk_cec_32k_recalc_rate()
116 if (aoclk_cec_32k_table[i].parent_rate == prate && in find_cec_32k_freq()
142 unsigned long parent_rate) in aoclk_cec_32k_set_rate() argument
145 parent_rate); in aoclk_cec_32k_set_rate()
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| /drivers/clk/ |
| D | clk-multiplier.c | 19 unsigned long parent_rate) in __get_mult() argument
22 return DIV_ROUND_CLOSEST(rate, parent_rate); in __get_mult()
24 return rate / parent_rate; in __get_mult()
28 unsigned long parent_rate) in clk_multiplier_recalc_rate() argument
39 return parent_rate * val; in clk_multiplier_recalc_rate()
57 unsigned long parent_rate, current_rate, best_rate = ~0; in __bestmult() local
87 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), in __bestmult()
89 current_rate = parent_rate * i; in __bestmult()
94 *best_parent_rate = parent_rate; in __bestmult()
102 unsigned long *parent_rate) in clk_multiplier_round_rate() argument
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| D | clk-vt8500.c | 124 unsigned long parent_rate) in vt8500_dclk_recalc_rate() argument
137 return parent_rate / div; in vt8500_dclk_recalc_rate()
167 unsigned long parent_rate) in vt8500_dclk_set_rate() argument
176 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
359 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
365 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
371 if (rate <= parent_rate * 31) in vt8500_find_pll_bits()
377 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
378 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
399 unsigned long parent_rate, u32 *multiplier, u32 *divisor1, in wm8650_find_pll_bits() argument
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| D | clk-cdce925.c | 91 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, in cdce925_pll_calculate_rate() argument
95 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
96 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); in cdce925_pll_calculate_rate()
100 unsigned long parent_rate) in cdce925_pll_recalc_rate() argument
105 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
109 unsigned long parent_rate, u16 *n, u16 *m) in cdce925_pll_find_rate() argument
115 if (rate <= parent_rate) { in cdce925_pll_find_rate()
117 rate = parent_rate; in cdce925_pll_find_rate()
127 g = gcd(rate, parent_rate); in cdce925_pll_find_rate()
128 um = parent_rate / g; in cdce925_pll_find_rate()
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| D | clk-xgene.c | 86 unsigned long parent_rate) in xgene_clk_pll_recalc_rate() argument
105 fvco = parent_rate * (N_DIV_RD(pll) + 4); in xgene_clk_pll_recalc_rate()
115 fref = parent_rate / nref; in xgene_clk_pll_recalc_rate()
124 fvco = parent_rate * SC_N_DIV_RD(pll); in xgene_clk_pll_recalc_rate()
127 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
255 unsigned long parent_rate) in xgene_clk_pmd_recalc_rate() argument
274 ret = (u64)parent_rate; in xgene_clk_pmd_recalc_rate()
286 ret = (u64)parent_rate; in xgene_clk_pmd_recalc_rate()
292 unsigned long *parent_rate) in xgene_clk_pmd_round_rate() argument
297 if (!rate || rate >= *parent_rate) in xgene_clk_pmd_round_rate()
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| D | clk-fractional-divider.c | 20 unsigned long parent_rate) in clk_fd_recalc_rate() argument
44 return parent_rate; in clk_fd_recalc_rate()
46 ret = (u64)parent_rate * m; in clk_fd_recalc_rate()
53 unsigned long *parent_rate, in clk_fd_general_approximation() argument
64 scale = fls_long(*parent_rate / rate - 1); in clk_fd_general_approximation()
68 rational_best_approximation(rate, *parent_rate, in clk_fd_general_approximation()
74 unsigned long *parent_rate) in clk_fd_round_rate() argument
80 if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate)) in clk_fd_round_rate()
81 return *parent_rate; in clk_fd_round_rate()
84 fd->approximation(hw, rate, parent_rate, &m, &n); in clk_fd_round_rate()
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| D | clk-highbank.c | 106 unsigned long parent_rate) in clk_pll_recalc_rate() argument
113 return parent_rate; in clk_pll_recalc_rate()
117 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
147 unsigned long *parent_rate) in clk_pll_round_rate() argument
150 unsigned long ref_freq = *parent_rate; in clk_pll_round_rate()
158 unsigned long parent_rate) in clk_pll_set_rate() argument
164 clk_pll_calc(rate, parent_rate, &divq, &divf); in clk_pll_set_rate()
206 unsigned long parent_rate) in clk_cpu_periphclk_recalc_rate() argument
210 return parent_rate / div; in clk_cpu_periphclk_recalc_rate()
218 unsigned long parent_rate) in clk_cpu_a9bclk_recalc_rate() argument
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| D | clk-versaclock5.c | 280 unsigned long parent_rate) in vc5_dbl_recalc_rate() argument
288 parent_rate *= 2; in vc5_dbl_recalc_rate()
290 return parent_rate; in vc5_dbl_recalc_rate()
294 unsigned long *parent_rate) in vc5_dbl_round_rate() argument
296 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) in vc5_dbl_round_rate()
303 unsigned long parent_rate) in vc5_dbl_set_rate() argument
309 if ((parent_rate * 2) == rate) in vc5_dbl_set_rate()
328 unsigned long parent_rate) in vc5_pfd_recalc_rate() argument
338 return parent_rate; in vc5_pfd_recalc_rate()
344 return parent_rate / 2; in vc5_pfd_recalc_rate()
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| D | clk-divider.c | 118 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, in divider_recalc_rate() argument
130 return parent_rate; in divider_recalc_rate()
133 return DIV_ROUND_UP_ULL((u64)parent_rate, div); in divider_recalc_rate()
138 unsigned long parent_rate) in clk_divider_recalc_rate() argument
146 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate()
208 unsigned long parent_rate, unsigned long rate, in _div_round_up() argument
211 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up()
222 unsigned long parent_rate, unsigned long rate, in _div_round_closest() argument
228 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_closest()
229 down = parent_rate / rate; in _div_round_closest()
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| /drivers/clk/microchip/ |
| D | clk-core.c | 127 unsigned long parent_rate, in calc_best_divided_rate() argument
138 div = parent_rate / rate; in calc_best_divided_rate()
142 divided_rate = parent_rate / div; in calc_best_divided_rate()
143 divided_rate_down = parent_rate / div_up; in calc_best_divided_rate()
158 unsigned long parent_rate) in pbclk_recalc_rate() argument
162 return parent_rate / pbclk_read_pbdiv(pb); in pbclk_recalc_rate()
166 unsigned long *parent_rate) in pbclk_round_rate() argument
168 return calc_best_divided_rate(rate, *parent_rate, in pbclk_round_rate()
173 unsigned long parent_rate) in pbclk_set_rate() argument
187 div = DIV_ROUND_CLOSEST(parent_rate, rate); in pbclk_set_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sun9i-cpus.c | 52 unsigned long parent_rate) in sun9i_a80_cpus_clk_recalc_rate() argument
63 parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1; in sun9i_a80_cpus_clk_recalc_rate()
66 rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1); in sun9i_a80_cpus_clk_recalc_rate()
72 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
80 if (parent_rate && rate > parent_rate) in sun9i_a80_cpus_clk_round()
81 rate = parent_rate; in sun9i_a80_cpus_clk_round()
83 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
109 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
117 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; in sun9i_a80_cpus_clk_determine_rate() local
127 parent_rate = clk_hw_round_rate(parent, rate); in sun9i_a80_cpus_clk_determine_rate()
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| D | clk-sun9i-core.c | 113 if (req->parent_rate < req->rate) in sun9i_a80_get_gt_factors()
114 req->rate = req->parent_rate; in sun9i_a80_get_gt_factors()
116 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun9i_a80_get_gt_factors()
122 req->rate = req->parent_rate / div; in sun9i_a80_get_gt_factors()
172 if (req->parent_rate < req->rate) in sun9i_a80_get_ahb_factors()
173 req->rate = req->parent_rate; in sun9i_a80_get_ahb_factors()
175 _p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun9i_a80_get_ahb_factors()
181 req->rate = req->parent_rate >> _p; in sun9i_a80_get_ahb_factors()
252 if (req->parent_rate < req->rate) in sun9i_a80_get_apb1_factors()
253 req->rate = req->parent_rate; in sun9i_a80_get_apb1_factors()
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| /drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 79 unsigned long parent_rate) in iproc_asiu_clk_recalc_rate() argument
86 if (parent_rate == 0) { in iproc_asiu_clk_recalc_rate()
94 clk->rate = parent_rate; in iproc_asiu_clk_recalc_rate()
95 return parent_rate; in iproc_asiu_clk_recalc_rate()
104 clk->rate = parent_rate / (div_h + div_l); in iproc_asiu_clk_recalc_rate()
106 __func__, clk->rate, parent_rate, div_h, div_l); in iproc_asiu_clk_recalc_rate()
112 unsigned long *parent_rate) in iproc_asiu_clk_round_rate() argument
116 if (rate == 0 || *parent_rate == 0) in iproc_asiu_clk_round_rate()
119 if (rate == *parent_rate) in iproc_asiu_clk_round_rate()
120 return *parent_rate; in iproc_asiu_clk_round_rate()
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| /drivers/clk/pxa/ |
| D | clk-pxa27x.c | 228 unsigned long parent_rate) in clk_pxa27x_cpll_get_rate() argument
241 L = l * parent_rate; in clk_pxa27x_cpll_get_rate()
255 unsigned long parent_rate) in clk_pxa27x_cpll_set_rate() argument
259 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate); in clk_pxa27x_cpll_set_rate()
275 unsigned long parent_rate) in clk_pxa27x_lcd_base_get_rate() argument
285 return parent_rate * 2; in clk_pxa27x_lcd_base_get_rate()
287 return parent_rate; in clk_pxa27x_lcd_base_get_rate()
291 return parent_rate; in clk_pxa27x_lcd_base_get_rate()
293 return parent_rate / 2; in clk_pxa27x_lcd_base_get_rate()
294 return parent_rate / 4; in clk_pxa27x_lcd_base_get_rate()
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| D | clk-pxa3xx.c | 85 unsigned long parent_rate) in clk_pxa3xx_ac97_get_rate() argument
94 rate = parent_rate / 2; in clk_pxa3xx_ac97_get_rate()
104 unsigned long parent_rate) in clk_pxa3xx_smemc_get_rate() argument
109 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / in clk_pxa3xx_smemc_get_rate()
195 unsigned long parent_rate) in clk_pxa3xx_system_bus_get_rate() argument
201 return parent_rate; in clk_pxa3xx_system_bus_get_rate()
202 return parent_rate / 48 * hss_mult[hss]; in clk_pxa3xx_system_bus_get_rate()
217 unsigned long parent_rate) in clk_pxa3xx_core_get_rate() argument
219 return parent_rate; in clk_pxa3xx_core_get_rate()
242 unsigned long parent_rate) in clk_pxa3xx_run_get_rate() argument
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| /drivers/clk/qcom/ |
| D | clk-rcg2.c | 158 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) in clk_rcg2_recalc_rate() argument
181 return calc_rate(parent_rate, m, n, mode, hid_div); in clk_rcg2_recalc_rate()
321 unsigned long parent_rate) in clk_rcg2_set_rate() argument
327 unsigned long parent_rate) in clk_rcg2_set_floor_rate() argument
333 unsigned long rate, unsigned long parent_rate, u8 index) in clk_rcg2_set_rate_and_parent() argument
339 unsigned long rate, unsigned long parent_rate, u8 index) in clk_rcg2_set_floor_rate_and_parent() argument
399 unsigned long parent_rate) in clk_rcg2_shared_set_rate() argument
413 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) in clk_rcg2_shared_recalc_rate() argument
417 return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate); in clk_rcg2_shared_recalc_rate()
473 unsigned long parent_rate) in clk_edp_pixel_set_rate() argument
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| /drivers/clk/ti/ |
| D | fapll.c | 167 unsigned long parent_rate) in ti_fapll_recalc_rate() argument
174 return parent_rate; in ti_fapll_recalc_rate()
176 rate = parent_rate; in ti_fapll_recalc_rate()
201 unsigned long parent_rate, in ti_fapll_set_div_mult() argument
210 if (rate < parent_rate) { in ti_fapll_set_div_mult()
215 *mult_n = rate / parent_rate; in ti_fapll_set_div_mult()
224 unsigned long *parent_rate) in ti_fapll_round_rate() argument
232 error = ti_fapll_set_div_mult(rate, *parent_rate, in ti_fapll_round_rate()
237 rate = *parent_rate / pre_div_p; in ti_fapll_round_rate()
244 unsigned long parent_rate) in ti_fapll_set_rate() argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_mp.c | 45 unsigned long *parent_rate, in ccu_mp_round_rate() argument
56 ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); in ccu_mp_round_rate()
58 return *parent_rate / p / m; in ccu_mp_round_rate()
83 unsigned long parent_rate) in ccu_mp_recalc_rate() argument
90 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, in ccu_mp_recalc_rate()
91 parent_rate); in ccu_mp_recalc_rate()
104 return (parent_rate >> p) / m; in ccu_mp_recalc_rate()
117 unsigned long parent_rate) in ccu_mp_set_rate() argument
126 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, in ccu_mp_set_rate()
127 parent_rate); in ccu_mp_set_rate()
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| /drivers/clk/zte/ |
| D | clk.c | 69 unsigned long parent_rate) in zx_pll_recalc_rate() argument
93 unsigned long parent_rate) in zx_pll_set_rate() argument
192 static u32 calc_reg(u32 parent_rate, u32 rate) in calc_reg() argument
195 u64 tmp64 = (u64)parent_rate * BPAR; in calc_reg()
215 static u32 calc_rate(u32 reg, u32 parent_rate) in calc_rate() argument
218 u64 tmp64 = (u64)parent_rate * BPAR; in calc_rate()
235 unsigned long parent_rate) in zx_audio_recalc_rate() argument
241 return calc_rate(reg, parent_rate); in zx_audio_recalc_rate()
257 unsigned long parent_rate) in zx_audio_set_rate() argument
262 reg = calc_reg(parent_rate, rate); in zx_audio_set_rate()
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