| /drivers/usb/renesas_usbhs/ |
| D | pipe.c | 42 char *usbhs_pipe_name(struct usbhs_pipe *pipe) in usbhs_pipe_name() argument
44 return usbhsp_pipe_name[usbhs_pipe_type(pipe)]; in usbhs_pipe_name()
59 static void usbhsp_pipectrl_set(struct usbhs_pipe *pipe, u16 mask, u16 val) in usbhsp_pipectrl_set() argument
61 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhsp_pipectrl_set()
62 int offset = usbhsp_addr_offset(pipe); in usbhsp_pipectrl_set()
64 if (usbhs_pipe_is_dcp(pipe)) in usbhsp_pipectrl_set()
70 static u16 usbhsp_pipectrl_get(struct usbhs_pipe *pipe) in usbhsp_pipectrl_get() argument
72 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhsp_pipectrl_get()
73 int offset = usbhsp_addr_offset(pipe); in usbhsp_pipectrl_get()
75 if (usbhs_pipe_is_dcp(pipe)) in usbhsp_pipectrl_get()
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| D | fifo.c | 26 #define usbhsf_fifo_is_busy(f) ((f)->pipe) /* see usbhs_pipe_select_fifo */
41 struct usbhs_priv *priv = usbhs_pipe_to_priv(pkt->pipe); in usbhsf_null_handle()
54 void usbhs_pkt_push(struct usbhs_pipe *pipe, struct usbhs_pkt *pkt, in usbhs_pkt_push() argument
59 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhs_pkt_push()
71 if (!pipe->handler) { in usbhs_pkt_push()
73 pipe->handler = &usbhsf_null_handler; in usbhs_pkt_push()
76 list_move_tail(&pkt->node, &pipe->list); in usbhs_pkt_push()
83 pkt->pipe = pipe; in usbhs_pkt_push()
85 pkt->handler = pipe->handler; in usbhs_pkt_push()
101 struct usbhs_pkt *__usbhsf_pkt_get(struct usbhs_pipe *pipe) in __usbhsf_pkt_get() argument
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| D | pipe.h | 47 struct usbhs_pipe *pipe; member
59 ((i) < (info)->size) && ((pos) = (info)->pipe + (i)); \
76 char *usbhs_pipe_name(struct usbhs_pipe *pipe);
79 void usbhs_pipe_free(struct usbhs_pipe *pipe);
82 int usbhs_pipe_is_dir_in(struct usbhs_pipe *pipe);
83 int usbhs_pipe_is_dir_host(struct usbhs_pipe *pipe);
84 int usbhs_pipe_is_running(struct usbhs_pipe *pipe);
85 void usbhs_pipe_running(struct usbhs_pipe *pipe, int running);
90 int usbhs_pipe_get_maxpacket(struct usbhs_pipe *pipe);
91 void usbhs_pipe_clear(struct usbhs_pipe *pipe);
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| /drivers/gpu/drm/gma500/ |
| D | mdfld_dsi_output.h | 75 #define CHECK_PIPE(pipe) ({ \ argument
76 const typeof(pipe) __pipe = (pipe); \
80 #define CHECK_PIPE(pipe) (pipe) argument
86 #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400) argument
89 #define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe)) argument
90 #define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe)) argument
91 #define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe)) argument
92 #define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe)) argument
93 #define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe)) argument
94 #define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe)) argument
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| D | mdfld_dsi_dpi.c | 35 int pipe);
37 static void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_DATA_FIFO() argument
39 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_DATA_FIFO()
55 static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_CTRL_FIFO() argument
57 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_CTRL_FIFO()
72 static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_DPI_CTRL_FIFO() argument
74 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_DPI_CTRL_FIFO()
90 static void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe) in mdfld_wait_for_SPL_PKG_SENT() argument
92 u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe); in mdfld_wait_for_SPL_PKG_SENT()
111 int pipe) in dsi_set_device_ready_state() argument
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| D | psb_irq.c | 38 psb_pipestat(int pipe) in psb_pipestat() argument
40 if (pipe == 0) in psb_pipestat()
42 if (pipe == 1) in psb_pipestat()
44 if (pipe == 2) in psb_pipestat()
50 mid_pipe_event(int pipe) in mid_pipe_event() argument
52 if (pipe == 0) in mid_pipe_event()
54 if (pipe == 1) in mid_pipe_event()
56 if (pipe == 2) in mid_pipe_event()
62 mid_pipe_vsync(int pipe) in mid_pipe_vsync() argument
64 if (pipe == 0) in mid_pipe_vsync()
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| /drivers/media/platform/vsp1/ |
| D | vsp1_pipe.c | 186 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) in vsp1_pipeline_reset() argument
190 if (pipe->bru) { in vsp1_pipeline_reset()
191 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev); in vsp1_pipeline_reset()
197 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) { in vsp1_pipeline_reset()
198 if (pipe->inputs[i]) { in vsp1_pipeline_reset()
199 pipe->inputs[i]->pipe = NULL; in vsp1_pipeline_reset()
200 pipe->inputs[i] = NULL; in vsp1_pipeline_reset()
204 if (pipe->output) { in vsp1_pipeline_reset()
205 pipe->output->pipe = NULL; in vsp1_pipeline_reset()
206 pipe->output = NULL; in vsp1_pipeline_reset()
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| D | vsp1_video.c | 193 static void vsp1_video_calculate_partition(struct vsp1_pipeline *pipe, in vsp1_video_calculate_partition() argument
206 format = vsp1_entity_get_pad_format(&pipe->output->entity, in vsp1_video_calculate_partition()
207 pipe->output->entity.config, in vsp1_video_calculate_partition()
211 if (pipe->partitions <= 1) { in vsp1_video_calculate_partition()
215 vsp1_pipeline_propagate_partition(pipe, partition, index, in vsp1_video_calculate_partition()
240 unsigned int partitions = pipe->partitions - 1; in vsp1_video_calculate_partition()
256 vsp1_pipeline_propagate_partition(pipe, partition, index, &window); in vsp1_video_calculate_partition()
259 static int vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe) in vsp1_video_pipeline_setup_partitions() argument
261 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; in vsp1_video_pipeline_setup_partitions()
271 format = vsp1_entity_get_pad_format(&pipe->output->entity, in vsp1_video_pipeline_setup_partitions()
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| D | vsp1_drm.c | 35 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe, in vsp1_du_pipeline_frame_end() argument
38 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe); in vsp1_du_pipeline_frame_end()
85 struct vsp1_pipeline *pipe; in vsp1_du_setup_lif() local
95 drm_pipe = &vsp1->drm->pipe[pipe_index]; in vsp1_du_setup_lif()
96 pipe = &drm_pipe->pipe; in vsp1_du_setup_lif()
97 bru = to_bru(&pipe->bru->subdev); in vsp1_du_setup_lif()
98 bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"; in vsp1_du_setup_lif()
105 ret = vsp1_pipeline_stop(pipe); in vsp1_du_setup_lif()
109 media_pipeline_stop(&pipe->output->entity.subdev.entity); in vsp1_du_setup_lif()
111 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) { in vsp1_du_setup_lif()
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| /drivers/platform/goldfish/ |
| D | goldfish_pipe_v2.c | 256 static int goldfish_pipe_cmd_locked(struct goldfish_pipe *pipe, in goldfish_pipe_cmd_locked() argument
259 pipe->command_buffer->cmd = cmd; in goldfish_pipe_cmd_locked()
261 pipe->command_buffer->status = PIPE_ERROR_INVAL; in goldfish_pipe_cmd_locked()
262 writel(pipe->id, pipe->dev->base + PIPE_V2_REG_CMD); in goldfish_pipe_cmd_locked()
263 return pipe->command_buffer->status; in goldfish_pipe_cmd_locked()
266 static int goldfish_pipe_cmd(struct goldfish_pipe *pipe, enum PipeCmdCode cmd) in goldfish_pipe_cmd() argument
270 if (mutex_lock_interruptible(&pipe->lock)) in goldfish_pipe_cmd()
272 status = goldfish_pipe_cmd_locked(pipe, cmd); in goldfish_pipe_cmd()
273 mutex_unlock(&pipe->lock); in goldfish_pipe_cmd()
374 static int transfer_max_buffers(struct goldfish_pipe *pipe, in transfer_max_buffers() argument
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| D | goldfish_pipe_v1.c | 99 static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd) in goldfish_cmd_status() argument
103 struct goldfish_pipe_dev *dev = pipe->dev; in goldfish_cmd_status()
106 gf_write_ptr(pipe, dev->base + PIPE_V1_REG_CHANNEL, in goldfish_cmd_status()
114 static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd) in goldfish_cmd() argument
117 struct goldfish_pipe_dev *dev = pipe->dev; in goldfish_cmd()
120 gf_write_ptr(pipe, dev->base + PIPE_V1_REG_CHANNEL, in goldfish_cmd()
186 struct goldfish_pipe *pipe, int *status) in access_with_param() argument
194 aps->channel = (unsigned long)pipe; in access_with_param()
212 struct goldfish_pipe *pipe, in transfer_pages() argument
221 if (access_with_param(dev, cmd, xaddr, size, pipe, &status)) { in transfer_pages()
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| /drivers/gpu/drm/ |
| D | drm_vblank.c | 80 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
100 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
104 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank()
120 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
126 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
129 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); in __get_vblank_counter()
136 return dev->driver->get_vblank_counter(dev, pipe); in __get_vblank_counter()
138 return drm_vblank_no_hw_counter(dev, pipe); in __get_vblank_counter()
150 static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe) in drm_reset_vblank_timestamp() argument
164 cur_vblank = __get_vblank_counter(dev, pipe); in drm_reset_vblank_timestamp()
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| D | drm_simple_kms_helper.c | 53 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_enable() local
55 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_enable()
56 if (!pipe->funcs || !pipe->funcs->enable) in drm_simple_kms_crtc_enable()
59 pipe->funcs->enable(pipe, crtc->state); in drm_simple_kms_crtc_enable()
65 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_disable() local
67 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_disable()
68 if (!pipe->funcs || !pipe->funcs->disable) in drm_simple_kms_crtc_disable()
71 pipe->funcs->disable(pipe); in drm_simple_kms_crtc_disable()
93 struct drm_simple_display_pipe *pipe; in drm_simple_kms_plane_atomic_check() local
97 pipe = container_of(plane, struct drm_simple_display_pipe, plane); in drm_simple_kms_plane_atomic_check()
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| /drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/ |
| D | pipe_binarydesc.c | 33 struct ia_css_pipe const * const pipe, in pipe_binarydesc_get_offline() argument
42 assert(pipe != NULL); in pipe_binarydesc_get_offline()
49 descr->continuous = pipe->stream->config.continuous; in pipe_binarydesc_get_offline()
67 descr->stream_format = pipe->stream->config.input_config.format; in pipe_binarydesc_get_offline()
73 descr->isp_pipe_version = pipe->config.isp_pipe_version; in pipe_binarydesc_get_offline()
79 struct ia_css_pipe const * const pipe, in ia_css_pipe_get_copy_binarydesc() argument
88 assert(pipe != NULL); in ia_css_pipe_get_copy_binarydesc()
96 pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_COPY, in ia_css_pipe_get_copy_binarydesc()
100 copy_descr->two_ppc = (pipe->stream->config.pixels_per_clock == 2); in ia_css_pipe_get_copy_binarydesc()
106 struct ia_css_pipe const * const pipe, in ia_css_pipe_get_vfpp_binarydesc() argument
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| /drivers/gpu/drm/i915/ |
| D | intel_fifo_underrun.c | 55 enum pipe pipe; in ivb_can_enable_err_int() local
59 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
72 enum pipe pipe; in cpt_can_enable_serr_int() local
77 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
90 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
101 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
102 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
106 enum pipe pipe, in i9xx_set_fifo_underrun_reporting() argument
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| D | intel_color.c | 112 int pipe = intel_crtc->pipe; in i9xx_load_ycbcr_conversion_matrix() local
115 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
116 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
117 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
119 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); in i9xx_load_ycbcr_conversion_matrix()
120 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); in i9xx_load_ycbcr_conversion_matrix()
122 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); in i9xx_load_ycbcr_conversion_matrix()
123 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); in i9xx_load_ycbcr_conversion_matrix()
125 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); in i9xx_load_ycbcr_conversion_matrix()
126 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); in i9xx_load_ycbcr_conversion_matrix()
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| D | intel_dpio_phy.c | 647 enum pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level() local
654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
658 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
665 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
671 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
677 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
682 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
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| D | intel_sprite.c | 131 pipe_name(crtc->pipe)); in intel_pipe_update_start()
182 enum pipe pipe = crtc->pipe; in intel_pipe_update_end() local
212 pipe_name(pipe), crtc->debug.start_vbl_count, in intel_pipe_update_end()
222 pipe_name(pipe), in intel_pipe_update_end()
236 enum pipe pipe = plane->pipe; in skl_update_plane() local
262 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), in skl_update_plane()
269 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); in skl_update_plane()
270 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value); in skl_update_plane()
271 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask); in skl_update_plane()
274 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); in skl_update_plane()
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| D | i915_reg.h | 144 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) argument
145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
1161 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) argument
1214 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
1215 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
1216 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
1217 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) argument
1218 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) argument
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| /drivers/staging/media/atomisp/pci/atomisp2/css2400/ |
| D | sh_css.c | 184 allocate_delay_frames(struct ia_css_pipe *pipe);
225 ia_css_pipe_check_format(struct ia_css_pipe *pipe, enum ia_css_frame_format format);
228 check_pipe_resolutions(const struct ia_css_pipe *pipe);
233 ia_css_pipe_load_extension(struct ia_css_pipe *pipe,
237 ia_css_pipe_unload_extension(struct ia_css_pipe *pipe,
248 need_capture_pp(const struct ia_css_pipe *pipe);
251 need_yuv_scaler_stage(const struct ia_css_pipe *pipe);
265 static bool need_capt_ldc(const struct ia_css_pipe *pipe);
268 sh_css_pipe_load_binaries(struct ia_css_pipe *pipe);
272 struct ia_css_pipe *pipe,
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| D | sh_css_mipi.c | 53 static bool ia_css_mipi_is_source_port_valid(struct ia_css_pipe *pipe, in ia_css_mipi_is_source_port_valid() argument
60 switch (pipe->stream->config.mode) { in ia_css_mipi_is_source_port_valid()
62 port = (unsigned int) pipe->stream->config.source.port.port; in ia_css_mipi_is_source_port_valid()
66 port = (unsigned int) pipe->stream->config.source.tpg.id; in ia_css_mipi_is_source_port_valid()
70 port = (unsigned int) pipe->stream->config.source.prbs.id; in ia_css_mipi_is_source_port_valid()
385 allocate_mipi_frames(struct ia_css_pipe *pipe, struct ia_css_stream_info *info) argument
397 "allocate_mipi_frames(%p) enter:\n", pipe);
399 assert(pipe != NULL);
400 assert(pipe->stream != NULL);
401 if ((pipe == NULL) || (pipe->stream == NULL)) {
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| /drivers/staging/octeon-usb/ |
| D | octeon-hcd.c | 488 if (usb_pipeisoc(urb->pipe)) in octeon_free_temp_buffer()
575 struct cvmx_usb_pipe *pipe) in cvmx_usb_pipe_needs_split() argument
577 return pipe->device_speed != CVMX_USB_SPEED_HIGH && in cvmx_usb_pipe_needs_split()
588 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe) in cvmx_usb_get_data_pid() argument
590 if (pipe->pid_toggle) in cvmx_usb_get_data_pid()
1094 struct cvmx_usb_pipe *pipe; in cvmx_usb_open_pipe() local
1096 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC); in cvmx_usb_open_pipe()
1097 if (!pipe) in cvmx_usb_open_pipe()
1102 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; in cvmx_usb_open_pipe()
1103 pipe->device_addr = device_addr; in cvmx_usb_open_pipe()
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| /drivers/net/wireless/ath/ath10k/ |
| D | usb.c | 47 ath10k_usb_alloc_urb_from_pipe(struct ath10k_usb_pipe *pipe) in ath10k_usb_alloc_urb_from_pipe() argument
53 if (!pipe->ar_usb) in ath10k_usb_alloc_urb_from_pipe()
56 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_alloc_urb_from_pipe()
57 if (!list_empty(&pipe->urb_list_head)) { in ath10k_usb_alloc_urb_from_pipe()
58 urb_context = list_first_entry(&pipe->urb_list_head, in ath10k_usb_alloc_urb_from_pipe()
61 pipe->urb_cnt--; in ath10k_usb_alloc_urb_from_pipe()
63 spin_unlock_irqrestore(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_alloc_urb_from_pipe()
68 static void ath10k_usb_free_urb_to_pipe(struct ath10k_usb_pipe *pipe, in ath10k_usb_free_urb_to_pipe() argument
74 if (!pipe->ar_usb) in ath10k_usb_free_urb_to_pipe()
77 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_free_urb_to_pipe()
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| /drivers/net/wireless/ath/ath6kl/ |
| D | usb.c | 79 struct ath6kl_usb_pipe *pipe; member
130 ath6kl_usb_alloc_urb_from_pipe(struct ath6kl_usb_pipe *pipe) in ath6kl_usb_alloc_urb_from_pipe() argument
136 if (!pipe->ar_usb) in ath6kl_usb_alloc_urb_from_pipe()
139 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath6kl_usb_alloc_urb_from_pipe()
140 if (!list_empty(&pipe->urb_list_head)) { in ath6kl_usb_alloc_urb_from_pipe()
142 list_first_entry(&pipe->urb_list_head, in ath6kl_usb_alloc_urb_from_pipe()
145 pipe->urb_cnt--; in ath6kl_usb_alloc_urb_from_pipe()
147 spin_unlock_irqrestore(&pipe->ar_usb->cs_lock, flags); in ath6kl_usb_alloc_urb_from_pipe()
152 static void ath6kl_usb_free_urb_to_pipe(struct ath6kl_usb_pipe *pipe, in ath6kl_usb_free_urb_to_pipe() argument
158 if (!pipe->ar_usb) in ath6kl_usb_free_urb_to_pipe()
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| /drivers/rpmsg/ |
| D | qcom_glink_smem.c | 61 struct glink_smem_pipe *pipe = to_smem_pipe(np); in glink_smem_rx_avail() local
67 if (!pipe->fifo) { in glink_smem_rx_avail()
68 fifo = qcom_smem_get(pipe->remote_pid, in glink_smem_rx_avail()
76 pipe->fifo = fifo; in glink_smem_rx_avail()
77 pipe->native.length = len; in glink_smem_rx_avail()
80 head = le32_to_cpu(*pipe->head); in glink_smem_rx_avail()
81 tail = le32_to_cpu(*pipe->tail); in glink_smem_rx_avail()
84 return pipe->native.length - tail + head; in glink_smem_rx_avail()
92 struct glink_smem_pipe *pipe = to_smem_pipe(np); in glink_smem_rx_peak() local
96 tail = le32_to_cpu(*pipe->tail); in glink_smem_rx_peak()
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