1 /*
2 * vsp1_drm.c -- R-Car VSP1 DRM API
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17
18 #include <media/media-entity.h>
19 #include <media/v4l2-subdev.h>
20 #include <media/vsp1.h>
21
22 #include "vsp1.h"
23 #include "vsp1_bru.h"
24 #include "vsp1_dl.h"
25 #include "vsp1_drm.h"
26 #include "vsp1_lif.h"
27 #include "vsp1_pipe.h"
28 #include "vsp1_rwpf.h"
29
30
31 /* -----------------------------------------------------------------------------
32 * Interrupt Handling
33 */
34
vsp1_du_pipeline_frame_end(struct vsp1_pipeline * pipe,bool completed)35 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
36 bool completed)
37 {
38 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
39
40 if (drm_pipe->du_complete)
41 drm_pipe->du_complete(drm_pipe->du_private, completed);
42 }
43
44 /* -----------------------------------------------------------------------------
45 * DU Driver API
46 */
47
vsp1_du_init(struct device * dev)48 int vsp1_du_init(struct device *dev)
49 {
50 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
51
52 if (!vsp1)
53 return -EPROBE_DEFER;
54
55 return 0;
56 }
57 EXPORT_SYMBOL_GPL(vsp1_du_init);
58
59 /**
60 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
61 * @dev: the VSP device
62 * @pipe_index: the DRM pipeline index
63 * @cfg: the LIF configuration
64 *
65 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
66 * and @cfg.height. This sets up formats on the blend unit (BRU or BRS) source
67 * pad, the WPF sink and source pads, and the LIF sink pad.
68 *
69 * The @pipe_index argument selects which DRM pipeline to setup. The number of
70 * available pipelines depend on the VSP instance.
71 *
72 * As the media bus code on the blend unit source pad is conditioned by the
73 * configuration of its sink 0 pad, we also set up the formats on all blend unit
74 * sinks, even if the configuration will be overwritten later by
75 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
76 * a well defined state.
77 *
78 * Return 0 on success or a negative error code on failure.
79 */
vsp1_du_setup_lif(struct device * dev,unsigned int pipe_index,const struct vsp1_du_lif_config * cfg)80 int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
81 const struct vsp1_du_lif_config *cfg)
82 {
83 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
84 struct vsp1_drm_pipeline *drm_pipe;
85 struct vsp1_pipeline *pipe;
86 struct vsp1_bru *bru;
87 struct v4l2_subdev_format format;
88 const char *bru_name;
89 unsigned int i;
90 int ret;
91
92 if (pipe_index >= vsp1->info->lif_count)
93 return -EINVAL;
94
95 drm_pipe = &vsp1->drm->pipe[pipe_index];
96 pipe = &drm_pipe->pipe;
97 bru = to_bru(&pipe->bru->subdev);
98 bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
99
100 if (!cfg) {
101 /*
102 * NULL configuration means the CRTC is being disabled, stop
103 * the pipeline and turn the light off.
104 */
105 ret = vsp1_pipeline_stop(pipe);
106 if (ret == -ETIMEDOUT)
107 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
108
109 media_pipeline_stop(&pipe->output->entity.subdev.entity);
110
111 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
112 struct vsp1_rwpf *rpf = pipe->inputs[i];
113
114 if (!rpf)
115 continue;
116
117 /*
118 * Remove the RPF from the pipe and the list of BRU
119 * inputs.
120 */
121 WARN_ON(list_empty(&rpf->entity.list_pipe));
122 list_del_init(&rpf->entity.list_pipe);
123 pipe->inputs[i] = NULL;
124
125 bru->inputs[rpf->bru_input].rpf = NULL;
126 }
127
128 drm_pipe->du_complete = NULL;
129 pipe->num_inputs = 0;
130
131 vsp1_dlm_reset(pipe->output->dlm);
132 vsp1_device_put(vsp1);
133
134 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
135
136 return 0;
137 }
138
139 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u\n",
140 __func__, pipe_index, cfg->width, cfg->height);
141
142 /*
143 * Configure the format at the BRU sinks and propagate it through the
144 * pipeline.
145 */
146 memset(&format, 0, sizeof(format));
147 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
148
149 for (i = 0; i < pipe->bru->source_pad; ++i) {
150 format.pad = i;
151
152 format.format.width = cfg->width;
153 format.format.height = cfg->height;
154 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
155 format.format.field = V4L2_FIELD_NONE;
156
157 ret = v4l2_subdev_call(&pipe->bru->subdev, pad,
158 set_fmt, NULL, &format);
159 if (ret < 0)
160 return ret;
161
162 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
163 __func__, format.format.width, format.format.height,
164 format.format.code, bru_name, i);
165 }
166
167 format.pad = pipe->bru->source_pad;
168 format.format.width = cfg->width;
169 format.format.height = cfg->height;
170 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
171 format.format.field = V4L2_FIELD_NONE;
172
173 ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
174 &format);
175 if (ret < 0)
176 return ret;
177
178 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
179 __func__, format.format.width, format.format.height,
180 format.format.code, bru_name, i);
181
182 format.pad = RWPF_PAD_SINK;
183 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
184 &format);
185 if (ret < 0)
186 return ret;
187
188 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
189 __func__, format.format.width, format.format.height,
190 format.format.code, pipe->output->entity.index);
191
192 format.pad = RWPF_PAD_SOURCE;
193 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
194 &format);
195 if (ret < 0)
196 return ret;
197
198 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
199 __func__, format.format.width, format.format.height,
200 format.format.code, pipe->output->entity.index);
201
202 format.pad = LIF_PAD_SINK;
203 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
204 &format);
205 if (ret < 0)
206 return ret;
207
208 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
209 __func__, format.format.width, format.format.height,
210 format.format.code, pipe_index);
211
212 /*
213 * Verify that the format at the output of the pipeline matches the
214 * requested frame size and media bus code.
215 */
216 if (format.format.width != cfg->width ||
217 format.format.height != cfg->height ||
218 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
219 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
220 return -EPIPE;
221 }
222
223 /*
224 * Mark the pipeline as streaming and enable the VSP1. This will store
225 * the pipeline pointer in all entities, which the s_stream handlers
226 * will need. We don't start the entities themselves right at this point
227 * as there's no plane configured yet, so we can't start processing
228 * buffers.
229 */
230 ret = vsp1_device_get(vsp1);
231 if (ret < 0)
232 return ret;
233
234 /*
235 * Register a callback to allow us to notify the DRM driver of frame
236 * completion events.
237 */
238 drm_pipe->du_complete = cfg->callback;
239 drm_pipe->du_private = cfg->callback_data;
240
241 ret = media_pipeline_start(&pipe->output->entity.subdev.entity,
242 &pipe->pipe);
243 if (ret < 0) {
244 dev_dbg(vsp1->dev, "%s: pipeline start failed\n", __func__);
245 vsp1_device_put(vsp1);
246 return ret;
247 }
248
249 /* Disable the display interrupts. */
250 vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
251 vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
252
253 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
254
255 return 0;
256 }
257 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
258
259 /**
260 * vsp1_du_atomic_begin - Prepare for an atomic update
261 * @dev: the VSP device
262 * @pipe_index: the DRM pipeline index
263 */
vsp1_du_atomic_begin(struct device * dev,unsigned int pipe_index)264 void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
265 {
266 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
267 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
268
269 drm_pipe->enabled = drm_pipe->pipe.num_inputs != 0;
270 }
271 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
272
273 /**
274 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
275 * @dev: the VSP device
276 * @pipe_index: the DRM pipeline index
277 * @rpf_index: index of the RPF to setup (0-based)
278 * @cfg: the RPF configuration
279 *
280 * Configure the VSP to perform image composition through RPF @rpf_index as
281 * described by the @cfg configuration. The image to compose is referenced by
282 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
283 * composition rectangle. The Z-order is configurable with higher @zpos values
284 * displayed on top.
285 *
286 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
287 * function on a disabled RPF is allowed.
288 *
289 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
290 * value. The memory pitch is configurable to allow for padding at end of lines,
291 * or simply for images that extend beyond the crop rectangle boundaries. The
292 * @cfg.pitch value is expressed in bytes and applies to all planes for
293 * multiplanar formats.
294 *
295 * The source memory buffer is referenced by the DMA address of its planes in
296 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
297 * address is ignored for formats using a single plane.
298 *
299 * This function isn't reentrant, the caller needs to serialize calls.
300 *
301 * Return 0 on success or a negative error code on failure.
302 */
vsp1_du_atomic_update(struct device * dev,unsigned int pipe_index,unsigned int rpf_index,const struct vsp1_du_atomic_config * cfg)303 int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
304 unsigned int rpf_index,
305 const struct vsp1_du_atomic_config *cfg)
306 {
307 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
308 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
309 const struct vsp1_format_info *fmtinfo;
310 struct vsp1_rwpf *rpf;
311
312 if (rpf_index >= vsp1->info->rpf_count)
313 return -EINVAL;
314
315 rpf = vsp1->rpf[rpf_index];
316
317 if (!cfg) {
318 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
319 rpf_index);
320
321 /*
322 * Remove the RPF from the pipe's inputs. The atomic flush
323 * handler will disable the input and remove the entity from the
324 * pipe's entities list.
325 */
326 drm_pipe->pipe.inputs[rpf_index] = NULL;
327 return 0;
328 }
329
330 dev_dbg(vsp1->dev,
331 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
332 __func__, rpf_index,
333 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
334 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
335 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
336 &cfg->mem[2], cfg->zpos);
337
338 /*
339 * Store the format, stride, memory buffer address, crop and compose
340 * rectangles and Z-order position and for the input.
341 */
342 fmtinfo = vsp1_get_format_info(vsp1, cfg->pixelformat);
343 if (!fmtinfo) {
344 dev_dbg(vsp1->dev, "Unsupport pixel format %08x for RPF\n",
345 cfg->pixelformat);
346 return -EINVAL;
347 }
348
349 rpf->fmtinfo = fmtinfo;
350 rpf->format.num_planes = fmtinfo->planes;
351 rpf->format.plane_fmt[0].bytesperline = cfg->pitch;
352 rpf->format.plane_fmt[1].bytesperline = cfg->pitch;
353 rpf->alpha = cfg->alpha;
354
355 rpf->mem.addr[0] = cfg->mem[0];
356 rpf->mem.addr[1] = cfg->mem[1];
357 rpf->mem.addr[2] = cfg->mem[2];
358
359 vsp1->drm->inputs[rpf_index].crop = cfg->src;
360 vsp1->drm->inputs[rpf_index].compose = cfg->dst;
361 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
362
363 drm_pipe->pipe.inputs[rpf_index] = rpf;
364
365 return 0;
366 }
367 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
368
vsp1_du_setup_rpf_pipe(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_rwpf * rpf,unsigned int bru_input)369 static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1,
370 struct vsp1_pipeline *pipe,
371 struct vsp1_rwpf *rpf, unsigned int bru_input)
372 {
373 struct v4l2_subdev_selection sel;
374 struct v4l2_subdev_format format;
375 const struct v4l2_rect *crop;
376 int ret;
377
378 /*
379 * Configure the format on the RPF sink pad and propagate it up to the
380 * BRU sink pad.
381 */
382 crop = &vsp1->drm->inputs[rpf->entity.index].crop;
383
384 memset(&format, 0, sizeof(format));
385 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
386 format.pad = RWPF_PAD_SINK;
387 format.format.width = crop->width + crop->left;
388 format.format.height = crop->height + crop->top;
389 format.format.code = rpf->fmtinfo->mbus;
390 format.format.field = V4L2_FIELD_NONE;
391
392 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
393 &format);
394 if (ret < 0)
395 return ret;
396
397 dev_dbg(vsp1->dev,
398 "%s: set format %ux%u (%x) on RPF%u sink\n",
399 __func__, format.format.width, format.format.height,
400 format.format.code, rpf->entity.index);
401
402 memset(&sel, 0, sizeof(sel));
403 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
404 sel.pad = RWPF_PAD_SINK;
405 sel.target = V4L2_SEL_TGT_CROP;
406 sel.r = *crop;
407
408 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
409 &sel);
410 if (ret < 0)
411 return ret;
412
413 dev_dbg(vsp1->dev,
414 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
415 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
416 rpf->entity.index);
417
418 /*
419 * RPF source, hardcode the format to ARGB8888 to turn on format
420 * conversion if needed.
421 */
422 format.pad = RWPF_PAD_SOURCE;
423
424 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
425 &format);
426 if (ret < 0)
427 return ret;
428
429 dev_dbg(vsp1->dev,
430 "%s: got format %ux%u (%x) on RPF%u source\n",
431 __func__, format.format.width, format.format.height,
432 format.format.code, rpf->entity.index);
433
434 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
435
436 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
437 &format);
438 if (ret < 0)
439 return ret;
440
441 /* BRU sink, propagate the format from the RPF source. */
442 format.pad = bru_input;
443
444 ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_fmt, NULL,
445 &format);
446 if (ret < 0)
447 return ret;
448
449 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
450 __func__, format.format.width, format.format.height,
451 format.format.code, format.pad);
452
453 sel.pad = bru_input;
454 sel.target = V4L2_SEL_TGT_COMPOSE;
455 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
456
457 ret = v4l2_subdev_call(&pipe->bru->subdev, pad, set_selection, NULL,
458 &sel);
459 if (ret < 0)
460 return ret;
461
462 dev_dbg(vsp1->dev,
463 "%s: set selection (%u,%u)/%ux%u on BRU pad %u\n",
464 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
465 sel.pad);
466
467 return 0;
468 }
469
rpf_zpos(struct vsp1_device * vsp1,struct vsp1_rwpf * rpf)470 static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
471 {
472 return vsp1->drm->inputs[rpf->entity.index].zpos;
473 }
474
475 /**
476 * vsp1_du_atomic_flush - Commit an atomic update
477 * @dev: the VSP device
478 * @pipe_index: the DRM pipeline index
479 */
vsp1_du_atomic_flush(struct device * dev,unsigned int pipe_index)480 void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index)
481 {
482 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
483 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
484 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
485 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
486 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
487 struct vsp1_entity *entity;
488 struct vsp1_entity *next;
489 struct vsp1_dl_list *dl;
490 const char *bru_name;
491 unsigned long flags;
492 unsigned int i;
493 int ret;
494
495 bru_name = pipe->bru->type == VSP1_ENTITY_BRU ? "BRU" : "BRS";
496
497 /* Prepare the display list. */
498 dl = vsp1_dl_list_get(pipe->output->dlm);
499
500 /* Count the number of enabled inputs and sort them by Z-order. */
501 pipe->num_inputs = 0;
502
503 for (i = 0; i < vsp1->info->rpf_count; ++i) {
504 struct vsp1_rwpf *rpf = vsp1->rpf[i];
505 unsigned int j;
506
507 /*
508 * Make sure we don't accept more inputs than the hardware can
509 * handle. This is a temporary fix to avoid display stall, we
510 * need to instead allocate the BRU or BRS to display pipelines
511 * dynamically based on the number of planes they each use.
512 */
513 if (pipe->num_inputs >= pipe->bru->source_pad)
514 pipe->inputs[i] = NULL;
515
516 if (!pipe->inputs[i])
517 continue;
518
519 /* Insert the RPF in the sorted RPFs array. */
520 for (j = pipe->num_inputs++; j > 0; --j) {
521 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
522 break;
523 inputs[j] = inputs[j-1];
524 }
525
526 inputs[j] = rpf;
527 }
528
529 /* Setup the RPF input pipeline for every enabled input. */
530 for (i = 0; i < pipe->bru->source_pad; ++i) {
531 struct vsp1_rwpf *rpf = inputs[i];
532
533 if (!rpf) {
534 bru->inputs[i].rpf = NULL;
535 continue;
536 }
537
538 if (list_empty(&rpf->entity.list_pipe))
539 list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
540
541 bru->inputs[i].rpf = rpf;
542 rpf->bru_input = i;
543 rpf->entity.sink = pipe->bru;
544 rpf->entity.sink_pad = i;
545
546 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
547 __func__, rpf->entity.index, bru_name, i);
548
549 ret = vsp1_du_setup_rpf_pipe(vsp1, pipe, rpf, i);
550 if (ret < 0)
551 dev_err(vsp1->dev,
552 "%s: failed to setup RPF.%u\n",
553 __func__, rpf->entity.index);
554 }
555
556 /* Configure all entities in the pipeline. */
557 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
558 /* Disconnect unused RPFs from the pipeline. */
559 if (entity->type == VSP1_ENTITY_RPF &&
560 !pipe->inputs[entity->index]) {
561 vsp1_dl_list_write(dl, entity->route->reg,
562 VI6_DPR_NODE_UNUSED);
563
564 list_del_init(&entity->list_pipe);
565
566 continue;
567 }
568
569 vsp1_entity_route_setup(entity, pipe, dl);
570
571 if (entity->ops->configure) {
572 entity->ops->configure(entity, pipe, dl,
573 VSP1_ENTITY_PARAMS_INIT);
574 entity->ops->configure(entity, pipe, dl,
575 VSP1_ENTITY_PARAMS_RUNTIME);
576 entity->ops->configure(entity, pipe, dl,
577 VSP1_ENTITY_PARAMS_PARTITION);
578 }
579 }
580
581 vsp1_dl_list_commit(dl);
582
583 /* Start or stop the pipeline if needed. */
584 if (!drm_pipe->enabled && pipe->num_inputs) {
585 spin_lock_irqsave(&pipe->irqlock, flags);
586 vsp1_pipeline_run(pipe);
587 spin_unlock_irqrestore(&pipe->irqlock, flags);
588 } else if (drm_pipe->enabled && !pipe->num_inputs) {
589 vsp1_pipeline_stop(pipe);
590 }
591 }
592 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
593
vsp1_du_map_sg(struct device * dev,struct sg_table * sgt)594 int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
595 {
596 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
597
598 /*
599 * As all the buffers allocated by the DU driver are coherent, we can
600 * skip cache sync. This will need to be revisited when support for
601 * non-coherent buffers will be added to the DU driver.
602 */
603 return dma_map_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
604 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
605 }
606 EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
607
vsp1_du_unmap_sg(struct device * dev,struct sg_table * sgt)608 void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
609 {
610 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
611
612 dma_unmap_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
613 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
614 }
615 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
616
617 /* -----------------------------------------------------------------------------
618 * Initialization
619 */
620
vsp1_drm_init(struct vsp1_device * vsp1)621 int vsp1_drm_init(struct vsp1_device *vsp1)
622 {
623 unsigned int i;
624
625 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
626 if (!vsp1->drm)
627 return -ENOMEM;
628
629 /* Create one DRM pipeline per LIF. */
630 for (i = 0; i < vsp1->info->lif_count; ++i) {
631 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
632 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
633
634 vsp1_pipeline_init(pipe);
635
636 /*
637 * The DRM pipeline is static, add entities manually. The first
638 * pipeline uses the BRU and the second pipeline the BRS.
639 */
640 pipe->bru = i == 0 ? &vsp1->bru->entity : &vsp1->brs->entity;
641 pipe->lif = &vsp1->lif[i]->entity;
642 pipe->output = vsp1->wpf[i];
643 pipe->output->pipe = pipe;
644 pipe->frame_end = vsp1_du_pipeline_frame_end;
645
646 pipe->bru->sink = &pipe->output->entity;
647 pipe->bru->sink_pad = 0;
648 pipe->output->entity.sink = pipe->lif;
649 pipe->output->entity.sink_pad = 0;
650
651 list_add_tail(&pipe->bru->list_pipe, &pipe->entities);
652 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
653 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
654 }
655
656 /* Disable all RPFs initially. */
657 for (i = 0; i < vsp1->info->rpf_count; ++i) {
658 struct vsp1_rwpf *input = vsp1->rpf[i];
659
660 INIT_LIST_HEAD(&input->entity.list_pipe);
661 }
662
663 return 0;
664 }
665
vsp1_drm_cleanup(struct vsp1_device * vsp1)666 void vsp1_drm_cleanup(struct vsp1_device *vsp1)
667 {
668 }
669