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Searched refs:reg_clear (Results 1 – 8 of 8) sorted by relevance

/drivers/media/i2c/soc_camera/
Dmt9t031.c113 static int reg_clear(struct i2c_client *client, const u8 reg, in reg_clear() function
159 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2); in mt9t031_idle()
174 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2); in mt9t031_s_stream()
286 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1); in mt9t031_set_params()
475 data = reg_clear(client, MT9T031_READ_MODE_2, 0x8000); in mt9t031_s_ctrl()
483 data = reg_clear(client, MT9T031_READ_MODE_2, 0x4000); in mt9t031_s_ctrl()
724 return reg_clear(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000); in mt9t031_s_mbus_config()
Dmt9v022.c195 static int reg_clear(struct i2c_client *client, const u8 reg, in reg_clear() function
233 ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1); in mt9v022_init()
256 if (reg_clear(client, MT9V022_REG32, 0x204)) in mt9v022_s_stream()
585 data = reg_clear(client, MT9V022_READ_MODE, 0x10); in mt9v022_s_ctrl()
593 data = reg_clear(client, MT9V022_READ_MODE, 0x20); in mt9v022_s_ctrl()
616 if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) in mt9v022_s_ctrl()
638 data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1); in mt9v022_s_ctrl()
Dmt9m001.c132 static int reg_clear(struct i2c_client *client, const u8 reg, in reg_clear() function
416 data = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000); in mt9m001_s_ctrl()
/drivers/gpu/drm/i2c/
Dtda998x_drv.c552 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) in reg_clear() function
572 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); in tda998x_reset()
693 reg_clear(priv, REG_DIP_IF_FLAGS, bit); in tda998x_write_if()
727 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); in tda998x_audio_mute()
730 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_audio_mute()
781 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | in tda998x_configure_audio()
822 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); in tda998x_configure_audio()
1089 reg_clear(priv, REG_TX4, TX4_PD_RAM); in tda998x_connector_get_modes()
1289 reg_clear(priv, REG_TX33, TX33_HDMI); in tda998x_encoder_mode_set()
1300 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); in tda998x_encoder_mode_set()
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/drivers/gpu/drm/stm/
Dltdc.c239 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) in reg_clear() function
398 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); in ltdc_crtc_atomic_disable()
401 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); in ltdc_crtc_atomic_disable()
526 reg_clear(ldev->regs, LTDC_IER, IER_LIE); in ltdc_crtc_disable_vblank()
679 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); in ltdc_plane_atomic_disable()
922 reg_clear(ldev->regs, LTDC_IER, in ltdc_load()
/drivers/media/i2c/
Dmt9m111.c135 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) macro
381 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE in mt9m111_reset()
694 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); in mt9m111_set_autoexposure()
703 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); in mt9m111_set_autowhitebalance()
742 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_suspend()
/drivers/iommu/
Dexynos-iommu.c412 unsigned short reg_status, reg_clear; in exynos_sysmmu_irq() local
419 reg_clear = REG_INT_CLEAR; in exynos_sysmmu_irq()
424 reg_clear = REG_V5_INT_CLEAR; in exynos_sysmmu_irq()
450 writel(1 << itype, data->sfrbase + reg_clear); in exynos_sysmmu_irq()
/drivers/media/platform/stm32/
Dstm32-dcmi.c189 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) in reg_clear() function
384 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); in dcmi_irq_thread()
683 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); in dcmi_stop_streaming()
686 reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE); in dcmi_stop_streaming()