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Searched refs:reg_off (Results 1 – 25 of 27) sorted by relevance

12

/drivers/clk/meson/
Dclk-pll.c60 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
64 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
68 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
73 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
79 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
127 reg = readl(pll->base + p_n->reg_off); in meson_clk_pll_wait_lock_reset()
128 writel(reg | MESON_PLL_RESET, pll->base + p_n->reg_off); in meson_clk_pll_wait_lock_reset()
130 writel(reg & ~MESON_PLL_RESET, pll->base + p_n->reg_off); in meson_clk_pll_wait_lock_reset()
135 reg = readl(pll->base + p_n->reg_off); in meson_clk_pll_wait_lock_reset()
150 reg = readl(pll->base + p_n->reg_off); in meson_clk_pll_wait_lock()
[all …]
Dclk-cpu.c82 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_set_rate()
84 writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_set_rate()
86 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_set_rate()
88 writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_set_rate()
101 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_recalc_rate()
104 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_recalc_rate()
122 cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
125 writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
131 writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
144 cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_post_rate_change()
[all …]
Dclk-mpll.c114 reg = readl(mpll->base + p->reg_off); in mpll_recalc_rate()
118 reg = readl(mpll->base + p->reg_off); in mpll_recalc_rate()
155 reg = readl(mpll->base + p->reg_off); in mpll_set_rate()
157 writel(reg, mpll->base + p->reg_off); in mpll_set_rate()
160 reg = readl(mpll->base + p->reg_off); in mpll_set_rate()
162 writel(reg, mpll->base + p->reg_off); in mpll_set_rate()
166 reg = readl(mpll->base + p->reg_off); in mpll_set_rate()
168 writel(reg, mpll->base + p->reg_off); in mpll_set_rate()
172 reg = readl(mpll->base + p->reg_off); in mpll_set_rate()
174 writel(reg, mpll->base + p->reg_off); in mpll_set_rate()
[all …]
Dmeson8b.c125 .reg_off = HHI_MPLL_CNTL,
130 .reg_off = HHI_MPLL_CNTL,
135 .reg_off = HHI_MPLL_CNTL,
151 .reg_off = HHI_VID_PLL_CNTL,
156 .reg_off = HHI_VID_PLL_CNTL,
161 .reg_off = HHI_VID_PLL_CNTL,
177 .reg_off = HHI_SYS_PLL_CNTL,
182 .reg_off = HHI_SYS_PLL_CNTL,
187 .reg_off = HHI_SYS_PLL_CNTL,
260 .reg_off = HHI_MPLL_CNTL7,
[all …]
Dgxbb.c283 .reg_off = HHI_MPLL_CNTL,
288 .reg_off = HHI_MPLL_CNTL,
293 .reg_off = HHI_MPLL_CNTL,
309 .reg_off = HHI_HDMI_PLL_CNTL,
314 .reg_off = HHI_HDMI_PLL_CNTL,
319 .reg_off = HHI_HDMI_PLL_CNTL2,
324 .reg_off = HHI_HDMI_PLL_CNTL2,
329 .reg_off = HHI_HDMI_PLL_CNTL2,
345 .reg_off = HHI_SYS_PLL_CNTL,
350 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
Dclkc.h33 u16 reg_off; member
66 unsigned int reg_off; member
72 .reg_off = (_reg), \
106 u16 reg_off; member
Dclk-audio-divider.c70 reg = readl(adiv->base + p->reg_off); in audio_divider_recalc_rate()
123 reg = readl(adiv->base + p->reg_off); in audio_divider_set_rate()
125 writel(reg, adiv->base + p->reg_off); in audio_divider_set_rate()
/drivers/mmc/host/
Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
Dcavium-thunderx.c85 host->reg_off = 0x2000; in thunder_mmc_probe()
Dcavium-octeon.c217 host->reg_off = 0; in octeon_mmc_probe()
Dsunxi-mmc.c701 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) in sunxi_mmc_calibrate() argument
715 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); in sunxi_mmc_calibrate()
/drivers/pinctrl/
Dpinctrl-digicolor.c134 int bit_off, reg_off; in dc_set_mux() local
137 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
139 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
142 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
152 int bit_off, reg_off; in dc_pmx_request_gpio() local
155 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
157 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
175 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
181 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
183 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/drivers/pinctrl/spear/
Dpinctrl-plgpio.c83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local
84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset() local
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
323 void __iomem *reg_off; in plgpio_irq_set_type() local
340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); in plgpio_irq_set_type()
[all …]
/drivers/net/ethernet/cavium/liquidio/
Docteon_device.h696 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
697 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
699 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
700 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
702 #define octeon_read_csr(oct_dev, reg_off) \ argument
703 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
705 #define octeon_read_csr64(oct_dev, reg_off) \ argument
706 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/drivers/mtd/nand/
Dqcom_nandc.c772 int reg_off, const void *vaddr, int size, in prep_adm_dma_desc() argument
809 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
813 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
921 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
927 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
939 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
945 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1672 int reg_off = FLASH_BUF_ACC; in qcom_nandc_read_page_raw() local
1703 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_page_raw()
1704 reg_off += data_size1; in qcom_nandc_read_page_raw()
[all …]
/drivers/staging/vt6656/
Dusbpipe.c78 void vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) in vnt_control_out_u8() argument
81 reg_off, reg, sizeof(u8), &data); in vnt_control_out_u8()
119 void vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data) in vnt_control_in_u8() argument
122 reg_off, reg, sizeof(u8), data); in vnt_control_in_u8()
Dusbpipe.h37 void vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data);
/drivers/rtc/
Drtc-sh.c462 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) in sh_rtc_read_alarm_value() argument
467 byte = readb(rtc->regbase + reg_off); in sh_rtc_read_alarm_value()
501 int value, int reg_off) in sh_rtc_write_alarm_value() argument
505 writeb(0, rtc->regbase + reg_off); in sh_rtc_write_alarm_value()
507 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); in sh_rtc_write_alarm_value()
/drivers/thermal/samsung/
Dexynos_tmu.c681 unsigned int reg_off, bit_off; in exynos7_tmu_initialize() local
719 reg_off = ((7 - i) / 2) * 4; in exynos7_tmu_initialize()
731 EXYNOS7_THD_TEMP_RISE7_6 + reg_off); in exynos7_tmu_initialize()
735 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); in exynos7_tmu_initialize()
742 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); in exynos7_tmu_initialize()
/drivers/thermal/tegra/
Dsoctherm.c484 u32 r, reg_off; in throttrip_program() local
493 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
507 r = readl(ts->regs + reg_off); in throttrip_program()
513 writel(r, ts->regs + reg_off); in throttrip_program()
/drivers/scsi/bnx2i/
Dbnx2i_hwi.c2732 u32 reg_off; in bnx2i_map_ep_dbell_regs() local
2743 reg_off = (1 << BNX2X_DB_SHIFT) * (cid_num & 0x1FFFF); in bnx2i_map_ep_dbell_regs()
2744 ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2i_map_ep_dbell_regs()
2756 reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE in bnx2i_map_ep_dbell_regs()
2760 reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); in bnx2i_map_ep_dbell_regs()
2763 reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); in bnx2i_map_ep_dbell_regs()
2765 ep->qp.ctx_base = ioremap_nocache(ep->hba->reg_base + reg_off, in bnx2i_map_ep_dbell_regs()
/drivers/net/ethernet/amazon/ena/
Dena_admin_defs.h918 u16 reg_off; member
/drivers/scsi/bnx2fc/
Dbnx2fc_hwi.c1420 u32 reg_off; in bnx2fc_map_doorbell() local
1427 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF); in bnx2fc_map_doorbell()
1428 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2fc_map_doorbell()
/drivers/tty/serial/
Dfsl_lpuart.c267 u8 reg_off; member
280 .reg_off = IMX_REG_OFF,
2169 sport->port.membase += sdata->reg_off; in lpuart_probe()
/drivers/scsi/
Dadvansys.c1895 #define AdvReadByteRegister(iop_base, reg_off) \ argument
1896 (ADV_MEM_READB((iop_base) + (reg_off)))
1899 #define AdvWriteByteRegister(iop_base, reg_off, byte) \ argument
1900 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1903 #define AdvReadWordRegister(iop_base, reg_off) \ argument
1904 (ADV_MEM_READW((iop_base) + (reg_off)))
1907 #define AdvWriteWordRegister(iop_base, reg_off, word) \ argument
1908 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1911 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ argument
1912 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))

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