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Searched refs:rlc (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c421 adev->gfx.rlc.save_and_restore_offset = in gfx_v9_0_init_microcode()
423 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v9_0_init_microcode()
425 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v9_0_init_microcode()
427 adev->gfx.rlc.reg_restore_list_size = in gfx_v9_0_init_microcode()
429 adev->gfx.rlc.reg_list_format_start = in gfx_v9_0_init_microcode()
431 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v9_0_init_microcode()
433 adev->gfx.rlc.starting_offsets_start = in gfx_v9_0_init_microcode()
435 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v9_0_init_microcode()
437 adev->gfx.rlc.reg_list_size_bytes = in gfx_v9_0_init_microcode()
439 adev->gfx.rlc.register_list_format = in gfx_v9_0_init_microcode()
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Dgfx_v7_0.c2524 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3302 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3303 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3304 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3318 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3319 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3322 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3323 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3327 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3328 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
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Dgfx_v6_0.c2080 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2407 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); in gfx_v6_0_rlc_fini()
2408 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v6_0_rlc_fini()
2409 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v6_0_rlc_fini()
2421 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2422 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2425 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2426 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2427 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2428 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
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Dgfx_v8_0.c876 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
975 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
977 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
979 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
981 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
983 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
985 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
987 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
989 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
991 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
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Damdgpu_cgs.c605 if (adev->gfx.rlc.funcs->enter_safe_mode == NULL || in amdgpu_cgs_enter_safe_mode()
606 adev->gfx.rlc.funcs->exit_safe_mode == NULL) in amdgpu_cgs_enter_safe_mode()
610 adev->gfx.rlc.funcs->enter_safe_mode(adev); in amdgpu_cgs_enter_safe_mode()
612 adev->gfx.rlc.funcs->exit_safe_mode(adev); in amdgpu_cgs_enter_safe_mode()
Damdgpu_ucode.h149 struct rlc_firmware_header_v1_0 rlc; member
Dkv_dpm.c512 adev->gfx.rlc.funcs->enter_safe_mode(adev); in kv_enable_didt()
517 adev->gfx.rlc.funcs->exit_safe_mode(adev); in kv_enable_didt()
524 adev->gfx.rlc.funcs->exit_safe_mode(adev); in kv_enable_didt()
Damdgpu.h978 struct amdgpu_rlc rlc; member
Dci_dpm.c745 adev->gfx.rlc.funcs->enter_safe_mode(adev); in ci_enable_didt()
750 adev->gfx.rlc.funcs->exit_safe_mode(adev); in ci_enable_didt()
757 adev->gfx.rlc.funcs->exit_safe_mode(adev); in ci_enable_didt()
/drivers/gpu/drm/radeon/
Devergreen.c4110 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4111 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4114 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4115 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4117 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4118 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4122 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4123 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4126 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4127 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
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Dradeon_ucode.h215 struct rlc_firmware_header_v1_0 rlc; member
Dcik.c5854 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5859 if (tmp != rlc) in cik_update_rlc()
5860 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6476 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6480 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6674 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6676 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6677 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6678 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6684 if (rdev->rlc.reg_list) { in cik_init_gfx_cgpg()
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Dsi.c5217 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5222 if (tmp != rlc) in si_update_rlc()
5223 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5279 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5285 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5685 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5693 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5717 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5729 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5781 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
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Dni.c2186 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2187 rdev->rlc.reg_list_size = in cayman_startup()
2189 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
Dradeon.h2413 struct radeon_rlc rlc; member