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Searched refs:src_h (Results 1 – 25 of 58) sorted by relevance

123

/drivers/media/platform/ti-vpe/
Dsc.c113 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h, in sc_set_vs_coeffs() argument
122 if (dst_h > src_h) { in sc_set_vs_coeffs()
124 } else if (dst_h == src_h) { in sc_set_vs_coeffs()
127 sixteenths = (dst_h << 4) / src_h; in sc_set_vs_coeffs()
151 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
181 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
216 if (dst_h < (src_h >> 2)) { in sc_config_scaler()
225 factor = (u16) ((dst_h << 10) / src_h); in sc_config_scaler()
241 src_h, dst_h, factor, row_acc_init_rav, in sc_config_scaler()
245 row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1); in sc_config_scaler()
[all …]
Dsc.h204 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
207 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
/drivers/media/pci/ivtv/
Divtv-yuv.c53 y_decode_height = uv_decode_height = f->src_h + f->src_y; in ivtv_yuv_prep_user_dma()
407 f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y); in ivtv_yuv_handle_vertical()
437 reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y); in ivtv_yuv_handle_vertical()
439 reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1); in ivtv_yuv_handle_vertical()
442 reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1); in ivtv_yuv_handle_vertical()
444 reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv); in ivtv_yuv_handle_vertical()
446 reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
447 reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
449 if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) { in ivtv_yuv_handle_vertical()
450 master_height = (f->src_h * 0x00400000) / f->dst_h; in ivtv_yuv_handle_vertical()
[all …]
/drivers/gpu/drm/zte/
Dzx_plane.c158 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
162 u32 src_chroma_h = src_h; in zx_vl_rsz_setup()
166 zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); in zx_vl_rsz_setup()
177 src_chroma_h = src_h >> 1; in zx_vl_rsz_setup()
184 zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); in zx_vl_rsz_setup()
204 u32 src_x, src_y, src_w, src_h; in zx_vl_plane_atomic_update() local
219 src_h = drm_rect_height(src) >> 16; in zx_vl_plane_atomic_update()
239 zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); in zx_vl_plane_atomic_update()
261 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
356 static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h, in zx_gl_rsz_setup() argument
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_plane.c59 uint32_t src_w, uint32_t src_h);
149 state->src_w, state->src_h); in mdp4_plane_atomic_update()
223 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
246 src_h = src_h >> 16; in mdp4_plane_mode_set()
249 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
259 if (src_h > (crtc_h * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
269 if (crtc_h > (src_h * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
290 if (src_h != crtc_h) { in mdp4_plane_mode_set()
296 if (crtc_h > src_h) in mdp4_plane_mode_set()
298 else if (crtc_h <= (src_h / 4)) in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/vc4/
Dvc4_plane.c61 u32 src_w[2], src_h[2]; member
313 (state->src_h & subpixel_src_mask)) { in vc4_plane_setup_clipping_and_scaling()
320 vc4_state->src_h[0] = state->src_h >> 16; in vc4_plane_setup_clipping_and_scaling()
329 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], in vc4_plane_setup_clipping_and_scaling()
341 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; in vc4_plane_setup_clipping_and_scaling()
347 vc4_get_scaling_mode(vc4_state->src_h[1], in vc4_plane_setup_clipping_and_scaling()
394 vc4_state->src_h[0] += vc4_state->crtc_y; in vc4_plane_setup_clipping_and_scaling()
395 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample; in vc4_plane_setup_clipping_and_scaling()
475 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
488 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
[all …]
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_plane.c40 uint32_t src_w, uint32_t src_h,
321 if (state->src_h > max_height) in mdp5_plane_atomic_check_with_state()
367 ((state->src_h >> 16) != state->crtc_h)) in mdp5_plane_atomic_check_with_state()
714 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) in mdp5_write_pixel_ext() argument
722 uint32_t roi_h = src_h; in mdp5_write_pixel_ext()
794 u32 src_w, u32 src_h) in mdp5_hwpipe_mode_set() argument
807 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); in mdp5_hwpipe_mode_set()
851 src_h, pe->top, pe->bottom); in mdp5_hwpipe_mode_set()
900 uint32_t src_w, src_h; in mdp5_plane_mode_set() local
918 src_h = drm_rect_height(src); in mdp5_plane_mode_set()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c474 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
507 src_h = c->top.input_viewport_size >> 16; in hqvdp_dbg_dump_cmd()
508 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
534 if (dst_h > src_h) in hqvdp_dbg_dump_cmd()
535 seq_printf(s, " %d/1", dst_h / src_h); in hqvdp_dbg_dump_cmd()
537 seq_printf(s, " 1/%d", src_h / dst_h); in hqvdp_dbg_dump_cmd()
728 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
737 inv_zy = DIV_ROUND_UP(src_h, dst_h); in sti_hqvdp_check_hw_scaling()
1023 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1039 src_h = state->src_h >> 16; in sti_hqvdp_atomic_check()
[all …]
Dsti_cursor.c191 int src_w, src_h; in sti_cursor_atomic_check() local
205 src_h = state->src_h >> 16; in sti_cursor_atomic_check()
208 src_h < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
210 src_h > STI_CURS_MAX_SIZE) { in sti_cursor_atomic_check()
212 src_w, src_h); in sti_cursor_atomic_check()
219 (cursor->height != src_h)) { in sti_cursor_atomic_check()
221 cursor->height = src_h; in sti_cursor_atomic_check()
Dsti_gdp.c619 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
637 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_check()
683 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
698 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
720 (oldstate->src_h == state->src_h)) { in sti_gdp_atomic_update()
746 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_update()
777 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); in sti_gdp_atomic_update()
788 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
Dsti_vid.c146 int src_h = state->src_h >> 16; in sti_vid_commit() local
168 if (src_h >= VID_MIN_HD_HEIGHT) { in sti_vid_commit()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c95 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, in verify_scaling() argument
98 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
100 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
118 uint32_t src_w, uint32_t src_h, in nv10_update_plane() argument
139 src_h >>= 16; in nv10_update_plane()
141 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
156 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
159 nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); in nv10_update_plane()
366 uint32_t src_w, uint32_t src_h, in nv04_update_plane() argument
382 src_h >>= 16; in nv04_update_plane()
[all …]
/drivers/gpu/drm/arm/
Dmalidp_planes.c146 u32 src_w, src_h; in malidp_se_check_scaling() local
159 src_h = state->src_h >> 16; in malidp_se_check_scaling()
160 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
270 u32 src_w, src_h, dest_w, dest_h, val; in malidp_de_plane_update() local
278 src_h = plane->state->src_h >> 16; in malidp_de_plane_update()
298 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
310 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
Dhdlcd_crtc.c234 u32 src_h = state->src_h >> 16; in hdlcd_plane_atomic_check() local
237 if (src_h >= HDLCD_MAX_YRES) { in hdlcd_plane_atomic_check()
238 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h); in hdlcd_plane_atomic_check()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c55 uint32_t src_h; member
310 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
321 yfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_h, in atmel_hlcdc_plane_setup_scaler()
333 state->crtc_h < state->src_h ? in atmel_hlcdc_plane_setup_scaler()
340 yfactor = (1024 * state->src_h) / state->crtc_h; in atmel_hlcdc_plane_setup_scaler()
364 state->src_h)); in atmel_hlcdc_plane_update_pos_and_size()
516 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
639 state->src_h = s->src_h; in atmel_hlcdc_plane_atomic_check()
645 if ((state->src_x | state->src_y | state->src_w | state->src_h) & in atmel_hlcdc_plane_atomic_check()
652 state->src_h >>= 16; in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/
Ddrm_rect.c162 int src_h = drm_rect_height(src); in drm_rect_calc_vscale() local
164 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale()
249 int src_h = drm_rect_height(src); in drm_rect_calc_vscale_relaxed() local
251 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale_relaxed()
257 int max_dst_h = src_h / min_vscale; in drm_rect_calc_vscale_relaxed()
267 drm_rect_adjust_size(src, 0, max_src_h - src_h); in drm_rect_calc_vscale_relaxed()
Ddrm_plane_helper.c240 .src_h = drm_rect_height(src), in drm_plane_helper_check_update()
307 uint32_t src_w, uint32_t src_h, in drm_primary_helper_update() argument
321 .y2 = src_y + src_h, in drm_primary_helper_update()
550 uint32_t src_w, uint32_t src_h) in drm_plane_helper_update() argument
574 plane_state->src_h = src_h; in drm_plane_helper_update()
Ddrm_plane.c589 uint32_t src_w, uint32_t src_h, in __setplane_internal() argument
635 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_internal()
642 src_x, src_y, src_w, src_h, ctx); in __setplane_internal()
668 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
680 src_x, src_y, src_w, src_h, &ctx); in setplane_internal()
740 plane_req->src_w, plane_req->src_h); in drm_mode_setplane()
759 uint32_t src_w = 0, src_h = 0; in drm_mode_cursor_universal() local
800 src_h = fb->height << 16; in drm_mode_cursor_universal()
809 0, 0, src_w, src_h, ctx); in drm_mode_cursor_universal()
1021 state->src_h, in drm_mode_page_flip_ioctl()
/drivers/gpu/drm/i915/
Dintel_sprite.c250 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in skl_update_plane() local
255 src_h--; in skl_update_plane()
276 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); in skl_update_plane()
664 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in ivb_update_plane() local
669 src_h--; in ivb_update_plane()
673 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
674 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; in ivb_update_plane()
820 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in g4x_update_plane() local
825 src_h--; in g4x_update_plane()
829 if (crtc_w != src_w || crtc_h != src_h) in g4x_update_plane()
[all …]
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c70 unsigned int src_w, src_h; in exynos_plane_mode_set() local
88 src_h = state->src_h >> 16; in exynos_plane_mode_set()
92 exynos_state->v_ratio = (src_h << 16) / crtc_h; in exynos_plane_mode_set()
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c163 cpu_to_le32(plane->state->src_h >> 16), in virtio_gpu_primary_plane_update()
175 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
180 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
187 plane->state->src_h >> 16); in virtio_gpu_primary_plane_update()
/drivers/gpu/drm/armada/
Darmada_trace.h31 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h),
32 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
/drivers/gpu/drm/stm/
Dltdc.c546 u32 src_x, src_y, src_w, src_h; in ltdc_plane_atomic_check() local
557 src_h = state->src_h >> 16; in ltdc_plane_atomic_check()
560 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) { in ltdc_plane_atomic_check()
579 u32 src_x, src_y, src_w, src_h; in ltdc_plane_atomic_update() local
592 src_h = state->src_h >> 16; in ltdc_plane_atomic_update()
596 src_w, src_h, src_x, src_y, in ltdc_plane_atomic_update()
/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.h295 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, in scl_get_bili_dn_vskip() argument
300 act_height = (src_h + vskiplines - 1) / vskiplines; in scl_get_bili_dn_vskip()
303 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; in scl_get_bili_dn_vskip()
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c787 u32 src_y, u32 src_w, u32 src_h) in ade_update_channel() argument
797 ch + 1, src_x, src_y, src_w, src_h, in ade_update_channel()
802 in_h = src_h; in ade_update_channel()
843 u32 src_h = state->src_h >> 16; in ade_plane_atomic_check() local
861 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
867 src_y + src_h > fb->height) in ade_plane_atomic_check()
889 state->src_w >> 16, state->src_h >> 16); in ade_plane_atomic_update()

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