1 /*
2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
8 * of such GNU licence.
9 *
10 * ARM Mali DP plane manipulation routines.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_fb_cma_helper.h>
17 #include <drm/drm_gem_cma_helper.h>
18 #include <drm/drm_plane_helper.h>
19 #include <drm/drm_print.h>
20
21 #include "malidp_hw.h"
22 #include "malidp_drv.h"
23
24 /* Layer specific register offsets */
25 #define MALIDP_LAYER_FORMAT 0x000
26 #define LAYER_FORMAT_MASK 0x3f
27 #define MALIDP_LAYER_CONTROL 0x004
28 #define LAYER_ENABLE (1 << 0)
29 #define LAYER_FLOWCFG_MASK 7
30 #define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1)
31 #define LAYER_FLOWCFG_SCALE_SE 3
32 #define LAYER_ROT_OFFSET 8
33 #define LAYER_H_FLIP (1 << 10)
34 #define LAYER_V_FLIP (1 << 11)
35 #define LAYER_ROT_MASK (0xf << 8)
36 #define LAYER_COMP_MASK (0x3 << 12)
37 #define LAYER_COMP_PIXEL (0x3 << 12)
38 #define LAYER_COMP_PLANE (0x2 << 12)
39 #define MALIDP_LAYER_COMPOSE 0x008
40 #define MALIDP_LAYER_SIZE 0x00c
41 #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
42 #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
43 #define MALIDP_LAYER_COMP_SIZE 0x010
44 #define MALIDP_LAYER_OFFSET 0x014
45 #define MALIDP550_LS_ENABLE 0x01c
46 #define MALIDP550_LS_R1_IN_SIZE 0x020
47
48 /*
49 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
50 * for formats with 1- or 2-bit alpha channels.
51 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
52 * opacity for 2-bit formats.
53 */
54 #define MALIDP_ALPHA_LUT 0xffaa5500
55
malidp_de_plane_destroy(struct drm_plane * plane)56 static void malidp_de_plane_destroy(struct drm_plane *plane)
57 {
58 struct malidp_plane *mp = to_malidp_plane(plane);
59
60 if (mp->base.fb)
61 drm_framebuffer_unreference(mp->base.fb);
62
63 drm_plane_helper_disable(plane);
64 drm_plane_cleanup(plane);
65 devm_kfree(plane->dev->dev, mp);
66 }
67
68 /*
69 * Replicate what the default ->reset hook does: free the state pointer and
70 * allocate a new empty object. We just need enough space to store
71 * a malidp_plane_state instead of a drm_plane_state.
72 */
malidp_plane_reset(struct drm_plane * plane)73 static void malidp_plane_reset(struct drm_plane *plane)
74 {
75 struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
76
77 if (state)
78 __drm_atomic_helper_plane_destroy_state(&state->base);
79 kfree(state);
80 plane->state = NULL;
81 state = kzalloc(sizeof(*state), GFP_KERNEL);
82 if (state) {
83 state->base.plane = plane;
84 state->base.rotation = DRM_MODE_ROTATE_0;
85 plane->state = &state->base;
86 }
87 }
88
89 static struct
malidp_duplicate_plane_state(struct drm_plane * plane)90 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
91 {
92 struct malidp_plane_state *state, *m_state;
93
94 if (!plane->state)
95 return NULL;
96
97 state = kmalloc(sizeof(*state), GFP_KERNEL);
98 if (!state)
99 return NULL;
100
101 m_state = to_malidp_plane_state(plane->state);
102 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
103 state->rotmem_size = m_state->rotmem_size;
104 state->format = m_state->format;
105 state->n_planes = m_state->n_planes;
106
107 return &state->base;
108 }
109
malidp_destroy_plane_state(struct drm_plane * plane,struct drm_plane_state * state)110 static void malidp_destroy_plane_state(struct drm_plane *plane,
111 struct drm_plane_state *state)
112 {
113 struct malidp_plane_state *m_state = to_malidp_plane_state(state);
114
115 __drm_atomic_helper_plane_destroy_state(state);
116 kfree(m_state);
117 }
118
malidp_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)119 static void malidp_plane_atomic_print_state(struct drm_printer *p,
120 const struct drm_plane_state *state)
121 {
122 struct malidp_plane_state *ms = to_malidp_plane_state(state);
123
124 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
125 drm_printf(p, "\tformat_id=%u\n", ms->format);
126 drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
127 }
128
129 static const struct drm_plane_funcs malidp_de_plane_funcs = {
130 .update_plane = drm_atomic_helper_update_plane,
131 .disable_plane = drm_atomic_helper_disable_plane,
132 .destroy = malidp_de_plane_destroy,
133 .reset = malidp_plane_reset,
134 .atomic_duplicate_state = malidp_duplicate_plane_state,
135 .atomic_destroy_state = malidp_destroy_plane_state,
136 .atomic_print_state = malidp_plane_atomic_print_state,
137 };
138
malidp_se_check_scaling(struct malidp_plane * mp,struct drm_plane_state * state)139 static int malidp_se_check_scaling(struct malidp_plane *mp,
140 struct drm_plane_state *state)
141 {
142 struct drm_crtc_state *crtc_state =
143 drm_atomic_get_existing_crtc_state(state->state, state->crtc);
144 struct malidp_crtc_state *mc;
145 struct drm_rect clip = { 0 };
146 u32 src_w, src_h;
147 int ret;
148
149 if (!crtc_state)
150 return -EINVAL;
151
152 clip.x2 = crtc_state->adjusted_mode.hdisplay;
153 clip.y2 = crtc_state->adjusted_mode.vdisplay;
154 ret = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, true, true);
155 if (ret)
156 return ret;
157
158 src_w = state->src_w >> 16;
159 src_h = state->src_h >> 16;
160 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
161 /* Scaling not necessary for this plane. */
162 mc->scaled_planes_mask &= ~(mp->layer->id);
163 return 0;
164 }
165
166 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
167 return -EINVAL;
168
169 mc = to_malidp_crtc_state(crtc_state);
170
171 mc->scaled_planes_mask |= mp->layer->id;
172 /* Defer scaling requirements calculation to the crtc check. */
173 return 0;
174 }
175
malidp_de_plane_check(struct drm_plane * plane,struct drm_plane_state * state)176 static int malidp_de_plane_check(struct drm_plane *plane,
177 struct drm_plane_state *state)
178 {
179 struct malidp_plane *mp = to_malidp_plane(plane);
180 struct malidp_plane_state *ms = to_malidp_plane_state(state);
181 struct drm_framebuffer *fb;
182 int i, ret;
183
184 if (!state->crtc || !state->fb)
185 return 0;
186
187 fb = state->fb;
188
189 ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
190 fb->format->format);
191 if (ms->format == MALIDP_INVALID_FORMAT_ID)
192 return -EINVAL;
193
194 ms->n_planes = fb->format->num_planes;
195 for (i = 0; i < ms->n_planes; i++) {
196 if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
197 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
198 fb->pitches[i], i);
199 return -EINVAL;
200 }
201 }
202
203 if ((state->crtc_w > mp->hwdev->max_line_size) ||
204 (state->crtc_h > mp->hwdev->max_line_size) ||
205 (state->crtc_w < mp->hwdev->min_line_size) ||
206 (state->crtc_h < mp->hwdev->min_line_size))
207 return -EINVAL;
208
209 /*
210 * DP550/650 video layers can accept 3 plane formats only if
211 * fb->pitches[1] == fb->pitches[2] since they don't have a
212 * third plane stride register.
213 */
214 if (ms->n_planes == 3 &&
215 !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
216 (state->fb->pitches[1] != state->fb->pitches[2]))
217 return -EINVAL;
218
219 ret = malidp_se_check_scaling(mp, state);
220 if (ret)
221 return ret;
222
223 /* packed RGB888 / BGR888 can't be rotated or flipped */
224 if (state->rotation != DRM_MODE_ROTATE_0 &&
225 (fb->format->format == DRM_FORMAT_RGB888 ||
226 fb->format->format == DRM_FORMAT_BGR888))
227 return -EINVAL;
228
229 ms->rotmem_size = 0;
230 if (state->rotation & MALIDP_ROTATED_MASK) {
231 int val;
232
233 val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h,
234 state->crtc_w,
235 fb->format->format);
236 if (val < 0)
237 return val;
238
239 ms->rotmem_size = val;
240 }
241
242 return 0;
243 }
244
malidp_de_set_plane_pitches(struct malidp_plane * mp,int num_planes,unsigned int pitches[3])245 static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
246 int num_planes, unsigned int pitches[3])
247 {
248 int i;
249 int num_strides = num_planes;
250
251 if (!mp->layer->stride_offset)
252 return;
253
254 if (num_planes == 3)
255 num_strides = (mp->hwdev->features &
256 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
257
258 for (i = 0; i < num_strides; ++i)
259 malidp_hw_write(mp->hwdev, pitches[i],
260 mp->layer->base +
261 mp->layer->stride_offset + i * 4);
262 }
263
malidp_de_plane_update(struct drm_plane * plane,struct drm_plane_state * old_state)264 static void malidp_de_plane_update(struct drm_plane *plane,
265 struct drm_plane_state *old_state)
266 {
267 struct malidp_plane *mp;
268 const struct malidp_hw_regmap *map;
269 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
270 u32 src_w, src_h, dest_w, dest_h, val;
271 int i;
272
273 mp = to_malidp_plane(plane);
274 map = &mp->hwdev->map;
275
276 /* convert src values from Q16 fixed point to integer */
277 src_w = plane->state->src_w >> 16;
278 src_h = plane->state->src_h >> 16;
279 dest_w = plane->state->crtc_w;
280 dest_h = plane->state->crtc_h;
281
282 val = malidp_hw_read(mp->hwdev, mp->layer->base);
283 val = (val & ~LAYER_FORMAT_MASK) | ms->format;
284 malidp_hw_write(mp->hwdev, val, mp->layer->base);
285
286 for (i = 0; i < ms->n_planes; i++) {
287 /* calculate the offset for the layer's plane registers */
288 u16 ptr = mp->layer->ptr + (i << 4);
289 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
290 plane->state, i);
291
292 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
293 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
294 }
295 malidp_de_set_plane_pitches(mp, ms->n_planes,
296 plane->state->fb->pitches);
297
298 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
299 mp->layer->base + MALIDP_LAYER_SIZE);
300
301 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
302 mp->layer->base + MALIDP_LAYER_COMP_SIZE);
303
304 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
305 LAYER_V_VAL(plane->state->crtc_y),
306 mp->layer->base + MALIDP_LAYER_OFFSET);
307
308 if (mp->layer->id == DE_SMART)
309 malidp_hw_write(mp->hwdev,
310 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
311 mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
312
313 /* first clear the rotation bits */
314 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
315 val &= ~LAYER_ROT_MASK;
316
317 /* setup the rotation and axis flip bits */
318 if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
319 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
320 LAYER_ROT_OFFSET;
321 if (plane->state->rotation & DRM_MODE_REFLECT_X)
322 val |= LAYER_H_FLIP;
323 if (plane->state->rotation & DRM_MODE_REFLECT_Y)
324 val |= LAYER_V_FLIP;
325
326 /*
327 * always enable pixel alpha blending until we have a way to change
328 * blend modes
329 */
330 val &= ~LAYER_COMP_MASK;
331 val |= LAYER_COMP_PIXEL;
332
333 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
334 if (plane->state->crtc) {
335 struct malidp_crtc_state *m =
336 to_malidp_crtc_state(plane->state->crtc->state);
337
338 if (m->scaler_config.scale_enable &&
339 m->scaler_config.plane_src_id == mp->layer->id)
340 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
341 }
342
343 /* set the 'enable layer' bit */
344 val |= LAYER_ENABLE;
345
346 malidp_hw_write(mp->hwdev, val,
347 mp->layer->base + MALIDP_LAYER_CONTROL);
348 }
349
malidp_de_plane_disable(struct drm_plane * plane,struct drm_plane_state * state)350 static void malidp_de_plane_disable(struct drm_plane *plane,
351 struct drm_plane_state *state)
352 {
353 struct malidp_plane *mp = to_malidp_plane(plane);
354
355 malidp_hw_clearbits(mp->hwdev,
356 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
357 mp->layer->base + MALIDP_LAYER_CONTROL);
358 }
359
360 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
361 .atomic_check = malidp_de_plane_check,
362 .atomic_update = malidp_de_plane_update,
363 .atomic_disable = malidp_de_plane_disable,
364 };
365
malidp_de_planes_init(struct drm_device * drm)366 int malidp_de_planes_init(struct drm_device *drm)
367 {
368 struct malidp_drm *malidp = drm->dev_private;
369 const struct malidp_hw_regmap *map = &malidp->dev->map;
370 struct malidp_plane *plane = NULL;
371 enum drm_plane_type plane_type;
372 unsigned long crtcs = 1 << drm->mode_config.num_crtc;
373 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
374 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
375 u32 *formats;
376 int ret, i, j, n;
377
378 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
379 if (!formats) {
380 ret = -ENOMEM;
381 goto cleanup;
382 }
383
384 for (i = 0; i < map->n_layers; i++) {
385 u8 id = map->layers[i].id;
386
387 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
388 if (!plane) {
389 ret = -ENOMEM;
390 goto cleanup;
391 }
392
393 /* build the list of DRM supported formats based on the map */
394 for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
395 if ((map->pixel_formats[j].layer & id) == id)
396 formats[n++] = map->pixel_formats[j].format;
397 }
398
399 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
400 DRM_PLANE_TYPE_OVERLAY;
401 ret = drm_universal_plane_init(drm, &plane->base, crtcs,
402 &malidp_de_plane_funcs, formats,
403 n, NULL, plane_type, NULL);
404 if (ret < 0)
405 goto cleanup;
406
407 drm_plane_helper_add(&plane->base,
408 &malidp_de_plane_helper_funcs);
409 plane->hwdev = malidp->dev;
410 plane->layer = &map->layers[i];
411
412 if (id == DE_SMART) {
413 /*
414 * Enable the first rectangle in the SMART layer to be
415 * able to use it as a drm plane.
416 */
417 malidp_hw_write(malidp->dev, 1,
418 plane->layer->base + MALIDP550_LS_ENABLE);
419 /* Skip the features which the SMART layer doesn't have. */
420 continue;
421 }
422
423 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
424 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
425 plane->layer->base + MALIDP_LAYER_COMPOSE);
426 }
427
428 kfree(formats);
429
430 return 0;
431
432 cleanup:
433 malidp_de_planes_destroy(drm);
434 kfree(formats);
435
436 return ret;
437 }
438
malidp_de_planes_destroy(struct drm_device * drm)439 void malidp_de_planes_destroy(struct drm_device *drm)
440 {
441 struct drm_plane *p, *pt;
442
443 list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
444 drm_plane_cleanup(p);
445 kfree(p);
446 }
447 }
448