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Searched refs:src_w (Results 1 – 25 of 53) sorted by relevance

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/drivers/media/platform/ti-vpe/
Dsc.c64 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w, in sc_set_hs_coeffs() argument
73 if (dst_w > src_w) { in sc_set_hs_coeffs()
76 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
78 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
81 if (dst_w == src_w) { in sc_set_hs_coeffs()
84 sixteenths = (dst_w << 4) / src_w; in sc_set_hs_coeffs()
151 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
181 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
193 dcm_x = src_w / dst_w; in sc_config_scaler()
205 lin_acc_inc = div64_u64(((u64)(src_w >> dcm_shift) - 1) << 24, lltmp); in sc_config_scaler()
[all …]
Dsc.h202 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
207 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
/drivers/media/pci/ivtv/
Divtv-yuv.c241 f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x); in ivtv_yuv_handle_horizontal()
244 x_cutoff = f->src_w + f->src_x; in ivtv_yuv_handle_horizontal()
268 if (f->dst_w >= f->src_w) in ivtv_yuv_handle_horizontal()
274 if (f->dst_w < f->src_w) in ivtv_yuv_handle_horizontal()
280 reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19; in ivtv_yuv_handle_horizontal()
282 if (f->dst_w >= f->src_w) { in ivtv_yuv_handle_horizontal()
284 master_width = (f->src_w * 0x00200000) / (f->dst_w); in ivtv_yuv_handle_horizontal()
285 if (master_width * f->dst_w != f->src_w * 0x00200000) in ivtv_yuv_handle_horizontal()
297 if (f->dst_w > f->src_w) in ivtv_yuv_handle_horizontal()
298 reg_2870_base = ((f->dst_w - f->src_w)<<16) / (f->src_w <<14); in ivtv_yuv_handle_horizontal()
[all …]
/drivers/gpu/drm/zte/
Dzx_plane.c158 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
161 u32 src_chroma_w = src_w; in zx_vl_rsz_setup()
166 zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); in zx_vl_rsz_setup()
176 src_chroma_w = src_w >> 1; in zx_vl_rsz_setup()
179 src_chroma_w = src_w >> 1; in zx_vl_rsz_setup()
183 zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); in zx_vl_rsz_setup()
204 u32 src_x, src_y, src_w, src_h; in zx_vl_plane_atomic_update() local
218 src_w = drm_rect_width(src) >> 16; in zx_vl_plane_atomic_update()
239 zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); in zx_vl_plane_atomic_update()
261 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_plane.c59 uint32_t src_w, uint32_t src_h);
149 state->src_w, state->src_h); in mdp4_plane_atomic_update()
223 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
245 src_w = src_w >> 16; in mdp4_plane_mode_set()
249 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
254 if (src_w > (crtc_w * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
264 if (crtc_w > (src_w * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
274 if (src_w != crtc_w) { in mdp4_plane_mode_set()
279 if (crtc_w > src_w) in mdp4_plane_mode_set()
281 else if (crtc_w <= (src_w / 4)) in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_plane.c40 uint32_t src_w, uint32_t src_h,
324 if (state->src_w > max_width) { in mdp5_plane_atomic_check_with_state()
331 (state->src_w <= 2 * max_width)) in mdp5_plane_atomic_check_with_state()
366 if (((state->src_w >> 16) != state->crtc_w) || in mdp5_plane_atomic_check_with_state()
402 state->src_w >> 16, false); in mdp5_plane_atomic_check_with_state()
713 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], in mdp5_write_pixel_ext() argument
721 uint32_t roi_w = src_w; in mdp5_write_pixel_ext()
794 u32 src_w, u32 src_h) in mdp5_hwpipe_mode_set() argument
806 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | in mdp5_hwpipe_mode_set()
850 src_w, pe->left, pe->right, in mdp5_hwpipe_mode_set()
[all …]
/drivers/gpu/drm/vc4/
Dvc4_plane.c61 u32 src_w[2], src_h[2]; member
312 (state->src_w & subpixel_src_mask) || in vc4_plane_setup_clipping_and_scaling()
319 vc4_state->src_w[0] = state->src_w >> 16; in vc4_plane_setup_clipping_and_scaling()
327 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], in vc4_plane_setup_clipping_and_scaling()
340 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; in vc4_plane_setup_clipping_and_scaling()
344 vc4_get_scaling_mode(vc4_state->src_w[1], in vc4_plane_setup_clipping_and_scaling()
382 vc4_state->src_w[0] += vc4_state->crtc_x; in vc4_plane_setup_clipping_and_scaling()
383 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample; in vc4_plane_setup_clipping_and_scaling()
436 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); in vc4_lbm_size()
469 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c474 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
506 src_w = c->top.input_viewport_size & 0x0000FFFF; in hqvdp_dbg_dump_cmd()
508 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
528 if (dst_w > src_w) in hqvdp_dbg_dump_cmd()
529 seq_printf(s, " %d/1", dst_w / src_w); in hqvdp_dbg_dump_cmd()
531 seq_printf(s, " 1/%d", src_w / dst_w); in hqvdp_dbg_dump_cmd()
728 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
735 lfw /= max(src_w, dst_w) * mode->clock / 1000; in sti_hqvdp_check_hw_scaling()
1023 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1038 src_w = state->src_w >> 16; in sti_hqvdp_atomic_check()
[all …]
Dsti_cursor.c191 int src_w, src_h; in sti_cursor_atomic_check() local
204 src_w = state->src_w >> 16; in sti_cursor_atomic_check()
207 if (src_w < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
209 src_w > STI_CURS_MAX_SIZE || in sti_cursor_atomic_check()
212 src_w, src_h); in sti_cursor_atomic_check()
218 (cursor->width != src_w) || in sti_cursor_atomic_check()
220 cursor->width = src_w; in sti_cursor_atomic_check()
Dsti_gdp.c619 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
636 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); in sti_gdp_atomic_check()
683 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
698 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
719 (oldstate->src_w == state->src_w) && in sti_gdp_atomic_update()
745 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); in sti_gdp_atomic_update()
776 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); in sti_gdp_atomic_update()
786 src_w = dst_w; in sti_gdp_atomic_update()
788 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c95 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, in verify_scaling() argument
98 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
100 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
118 uint32_t src_w, uint32_t src_h, in nv10_update_plane() argument
138 src_w >>= 16; in nv10_update_plane()
141 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
156 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
158 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
366 uint32_t src_w, uint32_t src_h, in nv04_update_plane() argument
381 src_w >>= 16; in nv04_update_plane()
[all …]
/drivers/gpu/drm/arm/
Dmalidp_planes.c146 u32 src_w, src_h; in malidp_se_check_scaling() local
158 src_w = state->src_w >> 16; in malidp_se_check_scaling()
160 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
270 u32 src_w, src_h, dest_w, dest_h, val; in malidp_de_plane_update() local
277 src_w = plane->state->src_w >> 16; in malidp_de_plane_update()
298 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
310 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c54 uint32_t src_w; member
310 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
317 xfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_w, in atmel_hlcdc_plane_setup_scaler()
326 state->crtc_w < state->src_w ? in atmel_hlcdc_plane_setup_scaler()
339 xfactor = (1024 * state->src_w) / state->crtc_w; in atmel_hlcdc_plane_setup_scaler()
363 ATMEL_HLCDC_LAYER_SIZE(state->src_w, in atmel_hlcdc_plane_update_pos_and_size()
516 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
640 state->src_w = s->src_w; in atmel_hlcdc_plane_atomic_check()
645 if ((state->src_x | state->src_y | state->src_w | state->src_h) & in atmel_hlcdc_plane_atomic_check()
651 state->src_w >>= 16; in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/
Ddrm_rect.c131 int src_w = drm_rect_width(src); in drm_rect_calc_hscale() local
133 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale()
199 int src_w = drm_rect_width(src); in drm_rect_calc_hscale_relaxed() local
201 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale_relaxed()
207 int max_dst_w = src_w / min_hscale; in drm_rect_calc_hscale_relaxed()
217 drm_rect_adjust_size(src, max_src_w - src_w, 0); in drm_rect_calc_hscale_relaxed()
Ddrm_plane_helper.c239 .src_w = drm_rect_width(src), in drm_plane_helper_check_update()
307 uint32_t src_w, uint32_t src_h, in drm_primary_helper_update() argument
320 .x2 = src_x + src_w, in drm_primary_helper_update()
550 uint32_t src_w, uint32_t src_h) in drm_plane_helper_update() argument
575 plane_state->src_w = src_w; in drm_plane_helper_update()
Ddrm_plane.c589 uint32_t src_w, uint32_t src_h, in __setplane_internal() argument
635 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_internal()
642 src_x, src_y, src_w, src_h, ctx); in __setplane_internal()
668 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
680 src_x, src_y, src_w, src_h, &ctx); in setplane_internal()
740 plane_req->src_w, plane_req->src_h); in drm_mode_setplane()
759 uint32_t src_w = 0, src_h = 0; in drm_mode_cursor_universal() local
799 src_w = fb->width << 16; in drm_mode_cursor_universal()
809 0, 0, src_w, src_h, ctx); in drm_mode_cursor_universal()
1020 state->src_w, in drm_mode_page_flip_ioctl()
Ddrm_framebuffer.c67 uint32_t src_w, uint32_t src_h, in drm_framebuffer_check_src_coords() argument
76 if (src_w > fb_width || in drm_framebuffer_check_src_coords()
77 src_x > fb_width - src_w || in drm_framebuffer_check_src_coords()
82 src_w >> 16, ((src_w & 0xffff) * 15625) >> 10, in drm_framebuffer_check_src_coords()
/drivers/gpu/drm/i915/
Dintel_sprite.c249 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in skl_update_plane() local
254 src_w--; in skl_update_plane()
276 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); in skl_update_plane()
663 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in ivb_update_plane() local
668 src_w--; in ivb_update_plane()
673 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
674 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; in ivb_update_plane()
819 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in g4x_update_plane() local
824 src_w--; in g4x_update_plane()
829 if (crtc_w != src_w || crtc_h != src_h) in g4x_update_plane()
[all …]
Dintel_overlay.c518 short src_w; member
844 tmp_width = packed_width_bytes(params->format, params->src_w); in intel_overlay_do_put_image()
846 tmp_width = params->src_w; in intel_overlay_do_put_image()
848 swidth = params->src_w; in intel_overlay_do_put_image()
858 swidth |= (params->src_w/uv_hscale) << 16; in intel_overlay_do_put_image()
860 params->src_w/uv_hscale); in intel_overlay_do_put_image()
862 params->src_w/uv_hscale); in intel_overlay_do_put_image()
1201 params->src_w = put_image_rec->src_width; in intel_overlay_put_image_ioctl()
1206 params->src_scan_w > params->src_w) { in intel_overlay_put_image_ioctl()
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c70 unsigned int src_w, src_h; in exynos_plane_mode_set() local
87 src_w = state->src_w >> 16; in exynos_plane_mode_set()
91 exynos_state->h_ratio = (src_w << 16) / crtc_w; in exynos_plane_mode_set()
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c162 cpu_to_le32(plane->state->src_w >> 16), in virtio_gpu_primary_plane_update()
174 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
179 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
186 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
/drivers/gpu/drm/armada/
Darmada_trace.h31 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h),
32 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
/drivers/gpu/drm/stm/
Dltdc.c546 u32 src_x, src_y, src_w, src_h; in ltdc_plane_atomic_check() local
556 src_w = state->src_w >> 16; in ltdc_plane_atomic_check()
560 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) { in ltdc_plane_atomic_check()
579 u32 src_x, src_y, src_w, src_h; in ltdc_plane_atomic_update() local
591 src_w = state->src_w >> 16; in ltdc_plane_atomic_update()
596 src_w, src_h, src_x, src_y, in ltdc_plane_atomic_update()
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c787 u32 src_y, u32 src_w, u32 src_h) in ade_update_channel() argument
797 ch + 1, src_x, src_y, src_w, src_h, in ade_update_channel()
801 in_w = src_w; in ade_update_channel()
842 u32 src_w = state->src_w >> 16; in ade_plane_atomic_check() local
861 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
866 if (src_x + src_w > fb->width || in ade_plane_atomic_check()
889 state->src_w >> 16, state->src_h >> 16); in ade_plane_atomic_update()
/drivers/gpu/drm/rcar-du/
Drcar_du_vsp.c64 .src_w = mode->hdisplay << 16, in rcar_du_vsp_enable()
183 cfg.src.width = state->state.src_w >> 16; in rcar_du_vsp_plane_setup()
279 if (state->src_w >> 16 != state->crtc_w || in rcar_du_vsp_plane_atomic_check()

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