1 ARM64 CPU Feature Registers 2 =========================== 3 4Author: Suzuki K Poulose <suzuki.poulose@arm.com> 5 6 7This file describes the ABI for exporting the AArch64 CPU ID/feature 8registers to userspace. The availability of this ABI is advertised 9via the HWCAP_CPUID in HWCAPs. 10 111. Motivation 12--------------- 13 14The ARM architecture defines a set of feature registers, which describe 15the capabilities of the CPU/system. Access to these system registers is 16restricted from EL0 and there is no reliable way for an application to 17extract this information to make better decisions at runtime. There is 18limited information available to the application via HWCAPs, however 19there are some issues with their usage. 20 21 a) Any change to the HWCAPs requires an update to userspace (e.g libc) 22 to detect the new changes, which can take a long time to appear in 23 distributions. Exposing the registers allows applications to get the 24 information without requiring updates to the toolchains. 25 26 b) Access to HWCAPs is sometimes limited (e.g prior to libc, or 27 when ld is initialised at startup time). 28 29 c) HWCAPs cannot represent non-boolean information effectively. The 30 architecture defines a canonical format for representing features 31 in the ID registers; this is well defined and is capable of 32 representing all valid architecture variations. 33 34 352. Requirements 36----------------- 37 38 a) Safety : 39 Applications should be able to use the information provided by the 40 infrastructure to run safely across the system. This has greater 41 implications on a system with heterogeneous CPUs. 42 The infrastructure exports a value that is safe across all the 43 available CPU on the system. 44 45 e.g, If at least one CPU doesn't implement CRC32 instructions, while 46 others do, we should report that the CRC32 is not implemented. 47 Otherwise an application could crash when scheduled on the CPU 48 which doesn't support CRC32. 49 50 b) Security : 51 Applications should only be able to receive information that is 52 relevant to the normal operation in userspace. Hence, some of the 53 fields are masked out(i.e, made invisible) and their values are set to 54 indicate the feature is 'not supported'. See Section 4 for the list 55 of visible features. Also, the kernel may manipulate the fields 56 based on what it supports. e.g, If FP is not supported by the 57 kernel, the values could indicate that the FP is not available 58 (even when the CPU provides it). 59 60 c) Implementation Defined Features 61 The infrastructure doesn't expose any register which is 62 IMPLEMENTATION DEFINED as per ARMv8-A Architecture. 63 64 d) CPU Identification : 65 MIDR_EL1 is exposed to help identify the processor. On a 66 heterogeneous system, this could be racy (just like getcpu()). The 67 process could be migrated to another CPU by the time it uses the 68 register value, unless the CPU affinity is set. Hence, there is no 69 guarantee that the value reflects the processor that it is 70 currently executing on. The REVIDR is not exposed due to this 71 constraint, as REVIDR makes sense only in conjunction with the 72 MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs 73 at: 74 75 /sys/devices/system/cpu/cpu$ID/regs/identification/ 76 \- midr 77 \- revidr 78 793. Implementation 80-------------------- 81 82The infrastructure is built on the emulation of the 'MRS' instruction. 83Accessing a restricted system register from an application generates an 84exception and ends up in SIGILL being delivered to the process. 85The infrastructure hooks into the exception handler and emulates the 86operation if the source belongs to the supported system register space. 87 88The infrastructure emulates only the following system register space: 89 Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 90 91(See Table C5-6 'System instruction encodings for non-Debug System 92register accesses' in ARMv8 ARM DDI 0487A.h, for the list of 93registers). 94 95The following rules are applied to the value returned by the 96infrastructure: 97 98 a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. 99 b) The value of a reserved field is populated with the reserved 100 value as defined by the architecture. 101 c) The value of a 'visible' field holds the system wide safe value 102 for the particular feature (except for MIDR_EL1, see section 4). 103 d) All other fields (i.e, invisible fields) are set to indicate 104 the feature is missing (as defined by the architecture). 105 1064. List of registers with visible features 107------------------------------------------- 108 109 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 110 x--------------------------------------------------x 111 | Name | bits | visible | 112 |--------------------------------------------------| 113 | RES0 | [63-48] | n | 114 | TS | [55-52] | y | 115 |--------------------------------------------------| 116 | FHM | [51-48] | y | 117 |--------------------------------------------------| 118 | DP | [47-44] | y | 119 |--------------------------------------------------| 120 | SM4 | [43-40] | y | 121 |--------------------------------------------------| 122 | SM3 | [39-36] | y | 123 |--------------------------------------------------| 124 | SHA3 | [35-32] | y | 125 |--------------------------------------------------| 126 | RDM | [31-28] | y | 127 |--------------------------------------------------| 128 | RES0 | [27-24] | n | 129 |--------------------------------------------------| 130 | ATOMICS | [23-20] | y | 131 |--------------------------------------------------| 132 | CRC32 | [19-16] | y | 133 |--------------------------------------------------| 134 | SHA2 | [15-12] | y | 135 |--------------------------------------------------| 136 | SHA1 | [11-8] | y | 137 |--------------------------------------------------| 138 | AES | [7-4] | y | 139 x--------------------------------------------------x 140 141 142 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 143 x--------------------------------------------------x 144 | Name | bits | visible | 145 |--------------------------------------------------| 146 | DIT | [51-48] | y | 147 |--------------------------------------------------| 148 | SVE | [35-32] | y | 149 |--------------------------------------------------| 150 | GIC | [27-24] | n | 151 |--------------------------------------------------| 152 | AdvSIMD | [23-20] | y | 153 |--------------------------------------------------| 154 | FP | [19-16] | y | 155 |--------------------------------------------------| 156 | EL3 | [15-12] | n | 157 |--------------------------------------------------| 158 | EL2 | [11-8] | n | 159 |--------------------------------------------------| 160 | EL1 | [7-4] | n | 161 |--------------------------------------------------| 162 | EL0 | [3-0] | n | 163 x--------------------------------------------------x 164 165 166 3) MIDR_EL1 - Main ID Register 167 x--------------------------------------------------x 168 | Name | bits | visible | 169 |--------------------------------------------------| 170 | Implementer | [31-24] | y | 171 |--------------------------------------------------| 172 | Variant | [23-20] | y | 173 |--------------------------------------------------| 174 | Architecture | [19-16] | y | 175 |--------------------------------------------------| 176 | PartNum | [15-4] | y | 177 |--------------------------------------------------| 178 | Revision | [3-0] | y | 179 x--------------------------------------------------x 180 181 NOTE: The 'visible' fields of MIDR_EL1 will contain the value 182 as available on the CPU where it is fetched and is not a system 183 wide safe value. 184 185 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 186 187 x--------------------------------------------------x 188 | Name | bits | visible | 189 |--------------------------------------------------| 190 | LRCPC | [23-20] | y | 191 |--------------------------------------------------| 192 | FCMA | [19-16] | y | 193 |--------------------------------------------------| 194 | JSCVT | [15-12] | y | 195 |--------------------------------------------------| 196 | DPB | [3-0] | y | 197 x--------------------------------------------------x 198 199 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 200 201 x--------------------------------------------------x 202 | Name | bits | visible | 203 |--------------------------------------------------| 204 | AT | [35-32] | y | 205 x--------------------------------------------------x 206 207Appendix I: Example 208--------------------------- 209 210/* 211 * Sample program to demonstrate the MRS emulation ABI. 212 * 213 * Copyright (C) 2015-2016, ARM Ltd 214 * 215 * Author: Suzuki K Poulose <suzuki.poulose@arm.com> 216 * 217 * This program is free software; you can redistribute it and/or modify 218 * it under the terms of the GNU General Public License version 2 as 219 * published by the Free Software Foundation. 220 * 221 * This program is distributed in the hope that it will be useful, 222 * but WITHOUT ANY WARRANTY; without even the implied warranty of 223 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 224 * GNU General Public License for more details. 225 * This program is free software; you can redistribute it and/or modify 226 * it under the terms of the GNU General Public License version 2 as 227 * published by the Free Software Foundation. 228 * 229 * This program is distributed in the hope that it will be useful, 230 * but WITHOUT ANY WARRANTY; without even the implied warranty of 231 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 232 * GNU General Public License for more details. 233 */ 234 235#include <asm/hwcap.h> 236#include <stdio.h> 237#include <sys/auxv.h> 238 239#define get_cpu_ftr(id) ({ \ 240 unsigned long __val; \ 241 asm("mrs %0, "#id : "=r" (__val)); \ 242 printf("%-20s: 0x%016lx\n", #id, __val); \ 243 }) 244 245int main(void) 246{ 247 248 if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { 249 fputs("CPUID registers unavailable\n", stderr); 250 return 1; 251 } 252 253 get_cpu_ftr(ID_AA64ISAR0_EL1); 254 get_cpu_ftr(ID_AA64ISAR1_EL1); 255 get_cpu_ftr(ID_AA64MMFR0_EL1); 256 get_cpu_ftr(ID_AA64MMFR1_EL1); 257 get_cpu_ftr(ID_AA64PFR0_EL1); 258 get_cpu_ftr(ID_AA64PFR1_EL1); 259 get_cpu_ftr(ID_AA64DFR0_EL1); 260 get_cpu_ftr(ID_AA64DFR1_EL1); 261 262 get_cpu_ftr(MIDR_EL1); 263 get_cpu_ftr(MPIDR_EL1); 264 get_cpu_ftr(REVIDR_EL1); 265 266#if 0 267 /* Unexposed register access causes SIGILL */ 268 get_cpu_ftr(ID_MMFR0_EL1); 269#endif 270 271 return 0; 272} 273 274 275 276