1LVDS Display Panel 2================== 3 4LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 5incompatible data link layers have been used over time to transmit image data 6to LVDS panels. This bindings supports display panels compatible with the 7following specifications. 8 9[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 101999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 11[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 12Semiconductor 13[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 14Electronics Standards Association (VESA) 15 16Device compatible with those specifications have been marketed under the 17FPD-Link and FlatLink brands. 18 19 20Required properties: 21 22- compatible: Shall contain "panel-lvds" in addition to a mandatory 23 panel-specific compatible string defined in individual panel bindings. The 24 "panel-lvds" value shall never be used on its own. 25- width-mm: See panel-common.txt. 26- height-mm: See panel-common.txt. 27- data-mapping: The color signals mapping order, "jeida-18", "jeida-24" 28 or "vesa-24". 29 30Optional properties: 31 32- label: See panel-common.txt. 33- gpios: See panel-common.txt. 34- backlight: See panel-common.txt. 35- data-mirror: If set, reverse the bit order described in the data mappings 36 below on all data lanes, transmitting bits for slots 6 to 0 instead of 37 0 to 6. 38 39Required nodes: 40 41- panel-timing: See panel-common.txt. 42- ports: See panel-common.txt. These bindings require a single port subnode 43 corresponding to the panel LVDS input. 44 45 46LVDS data mappings are defined as follows. 47 48- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 49 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 50 51Slot 0 1 2 3 4 5 6 52 ________________ _________________ 53Clock \_______________________/ 54 ______ ______ ______ ______ ______ ______ ______ 55DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 56DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 57DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 58 59- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 60 specifications. Data are transferred as follows on 4 LVDS lanes. 61 62Slot 0 1 2 3 4 5 6 63 ________________ _________________ 64Clock \_______________________/ 65 ______ ______ ______ ______ ______ ______ ______ 66DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 67DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 68DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 69DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 70 71- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 72 Data are transferred as follows on 4 LVDS lanes. 73 74Slot 0 1 2 3 4 5 6 75 ________________ _________________ 76Clock \_______________________/ 77 ______ ______ ______ ______ ______ ______ ______ 78DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 79DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 80DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 81DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 82 83Control signals are mapped as follows. 84 85CTL0: HSync 86CTL1: VSync 87CTL2: Data Enable 88CTL3: 0 89 90 91Example 92------- 93 94panel { 95 compatible = "mitsubishi,aa121td01", "panel-lvds"; 96 97 width-mm = <261>; 98 height-mm = <163>; 99 100 data-mapping = "jeida-24"; 101 102 panel-timing { 103 /* 1280x800 @60Hz */ 104 clock-frequency = <71000000>; 105 hactive = <1280>; 106 vactive = <800>; 107 hsync-len = <70>; 108 hfront-porch = <20>; 109 hback-porch = <70>; 110 vsync-len = <5>; 111 vfront-porch = <3>; 112 vback-porch = <15>; 113 }; 114 115 port { 116 panel_in: endpoint { 117 remote-endpoint = <&lvds_encoder>; 118 }; 119 }; 120}; 121