1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6- interrupts: The interrupt outputs from the controller. 7- #address-cells: The number of cells used to represent physical base addresses 8 in the host1x address space. Should be 1. 9- #size-cells: The number of cells used to represent the size of an address 10 range in the host1x address space. Should be 1. 11- ranges: The mapping of the host1x address space to the CPU address space. 12- clocks: Must contain one entry, for the module clock. 13 See ../clocks/clock-bindings.txt for details. 14- resets: Must contain an entry for each entry in reset-names. 15 See ../reset/reset.txt for details. 16- reset-names: Must include the following entries: 17 - host1x 18 19The host1x top-level node defines a number of children, each representing one 20of the following host1x client modules: 21 22- mpe: video encoder 23 24 Required properties: 25 - compatible: "nvidia,tegra<chip>-mpe" 26 - reg: Physical base address and length of the controller's registers. 27 - interrupts: The interrupt outputs from the controller. 28 - clocks: Must contain one entry, for the module clock. 29 See ../clocks/clock-bindings.txt for details. 30 - resets: Must contain an entry for each entry in reset-names. 31 See ../reset/reset.txt for details. 32 - reset-names: Must include the following entries: 33 - mpe 34 35- vi: video input 36 37 Required properties: 38 - compatible: "nvidia,tegra<chip>-vi" 39 - reg: Physical base address and length of the controller's registers. 40 - interrupts: The interrupt outputs from the controller. 41 - clocks: Must contain one entry, for the module clock. 42 See ../clocks/clock-bindings.txt for details. 43 - resets: Must contain an entry for each entry in reset-names. 44 See ../reset/reset.txt for details. 45 - reset-names: Must include the following entries: 46 - vi 47 48- epp: encoder pre-processor 49 50 Required properties: 51 - compatible: "nvidia,tegra<chip>-epp" 52 - reg: Physical base address and length of the controller's registers. 53 - interrupts: The interrupt outputs from the controller. 54 - clocks: Must contain one entry, for the module clock. 55 See ../clocks/clock-bindings.txt for details. 56 - resets: Must contain an entry for each entry in reset-names. 57 See ../reset/reset.txt for details. 58 - reset-names: Must include the following entries: 59 - epp 60 61- isp: image signal processor 62 63 Required properties: 64 - compatible: "nvidia,tegra<chip>-isp" 65 - reg: Physical base address and length of the controller's registers. 66 - interrupts: The interrupt outputs from the controller. 67 - clocks: Must contain one entry, for the module clock. 68 See ../clocks/clock-bindings.txt for details. 69 - resets: Must contain an entry for each entry in reset-names. 70 See ../reset/reset.txt for details. 71 - reset-names: Must include the following entries: 72 - isp 73 74- gr2d: 2D graphics engine 75 76 Required properties: 77 - compatible: "nvidia,tegra<chip>-gr2d" 78 - reg: Physical base address and length of the controller's registers. 79 - interrupts: The interrupt outputs from the controller. 80 - clocks: Must contain one entry, for the module clock. 81 See ../clocks/clock-bindings.txt for details. 82 - resets: Must contain an entry for each entry in reset-names. 83 See ../reset/reset.txt for details. 84 - reset-names: Must include the following entries: 85 - 2d 86 87- gr3d: 3D graphics engine 88 89 Required properties: 90 - compatible: "nvidia,tegra<chip>-gr3d" 91 - reg: Physical base address and length of the controller's registers. 92 - clocks: Must contain an entry for each entry in clock-names. 93 See ../clocks/clock-bindings.txt for details. 94 - clock-names: Must include the following entries: 95 (This property may be omitted if the only clock in the list is "3d") 96 - 3d 97 This MUST be the first entry. 98 - 3d2 (Only required on SoCs with two 3D clocks) 99 - resets: Must contain an entry for each entry in reset-names. 100 See ../reset/reset.txt for details. 101 - reset-names: Must include the following entries: 102 - 3d 103 - 3d2 (Only required on SoCs with two 3D clocks) 104 105- dc: display controller 106 107 Required properties: 108 - compatible: "nvidia,tegra<chip>-dc" 109 - reg: Physical base address and length of the controller's registers. 110 - interrupts: The interrupt outputs from the controller. 111 - clocks: Must contain an entry for each entry in clock-names. 112 See ../clocks/clock-bindings.txt for details. 113 - clock-names: Must include the following entries: 114 - dc 115 This MUST be the first entry. 116 - parent 117 - resets: Must contain an entry for each entry in reset-names. 118 See ../reset/reset.txt for details. 119 - reset-names: Must include the following entries: 120 - dc 121 - nvidia,head: The number of the display controller head. This is used to 122 setup the various types of output to receive video data from the given 123 head. 124 125 Each display controller node has a child node, named "rgb", that represents 126 the RGB output associated with the controller. It can take the following 127 optional properties: 128 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 129 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 130 - nvidia,edid: supplies a binary EDID blob 131 - nvidia,panel: phandle of a display panel 132 133- hdmi: High Definition Multimedia Interface 134 135 Required properties: 136 - compatible: "nvidia,tegra<chip>-hdmi" 137 - reg: Physical base address and length of the controller's registers. 138 - interrupts: The interrupt outputs from the controller. 139 - hdmi-supply: supply for the +5V HDMI connector pin 140 - vdd-supply: regulator for supply voltage 141 - pll-supply: regulator for PLL 142 - clocks: Must contain an entry for each entry in clock-names. 143 See ../clocks/clock-bindings.txt for details. 144 - clock-names: Must include the following entries: 145 - hdmi 146 This MUST be the first entry. 147 - parent 148 - resets: Must contain an entry for each entry in reset-names. 149 See ../reset/reset.txt for details. 150 - reset-names: Must include the following entries: 151 - hdmi 152 153 Optional properties: 154 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 155 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 156 - nvidia,edid: supplies a binary EDID blob 157 - nvidia,panel: phandle of a display panel 158 159- tvo: TV encoder output 160 161 Required properties: 162 - compatible: "nvidia,tegra<chip>-tvo" 163 - reg: Physical base address and length of the controller's registers. 164 - interrupts: The interrupt outputs from the controller. 165 - clocks: Must contain one entry, for the module clock. 166 See ../clocks/clock-bindings.txt for details. 167 168- dsi: display serial interface 169 170 Required properties: 171 - compatible: "nvidia,tegra<chip>-dsi" 172 - reg: Physical base address and length of the controller's registers. 173 - clocks: Must contain an entry for each entry in clock-names. 174 See ../clocks/clock-bindings.txt for details. 175 - clock-names: Must include the following entries: 176 - dsi 177 This MUST be the first entry. 178 - lp 179 - parent 180 - resets: Must contain an entry for each entry in reset-names. 181 See ../reset/reset.txt for details. 182 - reset-names: Must include the following entries: 183 - dsi 184 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 185 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 186 which pads are used by this DSI output and need to be calibrated. See also 187 ../display/tegra/nvidia,tegra114-mipi.txt. 188 189 Optional properties: 190 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 191 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 192 - nvidia,edid: supplies a binary EDID blob 193 - nvidia,panel: phandle of a display panel 194 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 195 up with in order to support up to 8 data lanes 196 197- sor: serial output resource 198 199 Required properties: 200 - compatible: Should be: 201 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 202 - "nvidia,tegra132-sor": for Tegra132 203 - "nvidia,tegra210-sor": for Tegra210 204 - "nvidia,tegra210-sor1": for Tegra210 205 - reg: Physical base address and length of the controller's registers. 206 - interrupts: The interrupt outputs from the controller. 207 - clocks: Must contain an entry for each entry in clock-names. 208 See ../clocks/clock-bindings.txt for details. 209 - clock-names: Must include the following entries: 210 - sor: clock input for the SOR hardware 211 - source: source clock for the SOR clock 212 - parent: input for the pixel clock 213 - dp: reference clock for the SOR clock 214 - safe: safe reference for the SOR clock during power up 215 - resets: Must contain an entry for each entry in reset-names. 216 See ../reset/reset.txt for details. 217 - reset-names: Must include the following entries: 218 - sor 219 220 Optional properties: 221 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 222 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 223 - nvidia,edid: supplies a binary EDID blob 224 - nvidia,panel: phandle of a display panel 225 226 Optional properties when driving an eDP output: 227 - nvidia,dpaux: phandle to a DispayPort AUX interface 228 229- dpaux: DisplayPort AUX interface 230 - compatible : Should contain one of the following: 231 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 232 - "nvidia,tegra210-dpaux": for Tegra210 233 - reg: Physical base address and length of the controller's registers. 234 - interrupts: The interrupt outputs from the controller. 235 - clocks: Must contain an entry for each entry in clock-names. 236 See ../clocks/clock-bindings.txt for details. 237 - clock-names: Must include the following entries: 238 - dpaux: clock input for the DPAUX hardware 239 - parent: reference clock 240 - resets: Must contain an entry for each entry in reset-names. 241 See ../reset/reset.txt for details. 242 - reset-names: Must include the following entries: 243 - dpaux 244 - vdd-supply: phandle of a supply that powers the DisplayPort link 245 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 246 must be always present. If there are no I2C slave devices, an empty 247 node should be added. See ../../i2c/i2c.txt for more information. 248 249 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 250 regarding the DPAUX pad controller bindings. 251 252- vic: Video Image Compositor 253 - compatible : "nvidia,tegra<chip>-vic" 254 - reg: Physical base address and length of the controller's registers. 255 - interrupts: The interrupt outputs from the controller. 256 - clocks: Must contain an entry for each entry in clock-names. 257 See ../clocks/clock-bindings.txt for details. 258 - clock-names: Must include the following entries: 259 - vic: clock input for the VIC hardware 260 - resets: Must contain an entry for each entry in reset-names. 261 See ../reset/reset.txt for details. 262 - reset-names: Must include the following entries: 263 - vic 264 265Example: 266 267/ { 268 ... 269 270 host1x { 271 compatible = "nvidia,tegra20-host1x", "simple-bus"; 272 reg = <0x50000000 0x00024000>; 273 interrupts = <0 65 0x04 /* mpcore syncpt */ 274 0 67 0x04>; /* mpcore general */ 275 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 276 resets = <&tegra_car 28>; 277 reset-names = "host1x"; 278 279 #address-cells = <1>; 280 #size-cells = <1>; 281 282 ranges = <0x54000000 0x54000000 0x04000000>; 283 284 mpe { 285 compatible = "nvidia,tegra20-mpe"; 286 reg = <0x54040000 0x00040000>; 287 interrupts = <0 68 0x04>; 288 clocks = <&tegra_car TEGRA20_CLK_MPE>; 289 resets = <&tegra_car 60>; 290 reset-names = "mpe"; 291 }; 292 293 vi { 294 compatible = "nvidia,tegra20-vi"; 295 reg = <0x54080000 0x00040000>; 296 interrupts = <0 69 0x04>; 297 clocks = <&tegra_car TEGRA20_CLK_VI>; 298 resets = <&tegra_car 100>; 299 reset-names = "vi"; 300 }; 301 302 epp { 303 compatible = "nvidia,tegra20-epp"; 304 reg = <0x540c0000 0x00040000>; 305 interrupts = <0 70 0x04>; 306 clocks = <&tegra_car TEGRA20_CLK_EPP>; 307 resets = <&tegra_car 19>; 308 reset-names = "epp"; 309 }; 310 311 isp { 312 compatible = "nvidia,tegra20-isp"; 313 reg = <0x54100000 0x00040000>; 314 interrupts = <0 71 0x04>; 315 clocks = <&tegra_car TEGRA20_CLK_ISP>; 316 resets = <&tegra_car 23>; 317 reset-names = "isp"; 318 }; 319 320 gr2d { 321 compatible = "nvidia,tegra20-gr2d"; 322 reg = <0x54140000 0x00040000>; 323 interrupts = <0 72 0x04>; 324 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 325 resets = <&tegra_car 21>; 326 reset-names = "2d"; 327 }; 328 329 gr3d { 330 compatible = "nvidia,tegra20-gr3d"; 331 reg = <0x54180000 0x00040000>; 332 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 333 resets = <&tegra_car 24>; 334 reset-names = "3d"; 335 }; 336 337 dc@54200000 { 338 compatible = "nvidia,tegra20-dc"; 339 reg = <0x54200000 0x00040000>; 340 interrupts = <0 73 0x04>; 341 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 342 <&tegra_car TEGRA20_CLK_PLL_P>; 343 clock-names = "dc", "parent"; 344 resets = <&tegra_car 27>; 345 reset-names = "dc"; 346 347 rgb { 348 status = "disabled"; 349 }; 350 }; 351 352 dc@54240000 { 353 compatible = "nvidia,tegra20-dc"; 354 reg = <0x54240000 0x00040000>; 355 interrupts = <0 74 0x04>; 356 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 357 <&tegra_car TEGRA20_CLK_PLL_P>; 358 clock-names = "dc", "parent"; 359 resets = <&tegra_car 26>; 360 reset-names = "dc"; 361 362 rgb { 363 status = "disabled"; 364 }; 365 }; 366 367 hdmi { 368 compatible = "nvidia,tegra20-hdmi"; 369 reg = <0x54280000 0x00040000>; 370 interrupts = <0 75 0x04>; 371 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 372 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 373 clock-names = "hdmi", "parent"; 374 resets = <&tegra_car 51>; 375 reset-names = "hdmi"; 376 status = "disabled"; 377 }; 378 379 tvo { 380 compatible = "nvidia,tegra20-tvo"; 381 reg = <0x542c0000 0x00040000>; 382 interrupts = <0 76 0x04>; 383 clocks = <&tegra_car TEGRA20_CLK_TVO>; 384 status = "disabled"; 385 }; 386 387 dsi { 388 compatible = "nvidia,tegra20-dsi"; 389 reg = <0x54300000 0x00040000>; 390 clocks = <&tegra_car TEGRA20_CLK_DSI>, 391 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 392 clock-names = "dsi", "parent"; 393 resets = <&tegra_car 48>; 394 reset-names = "dsi"; 395 status = "disabled"; 396 }; 397 }; 398 399 ... 400}; 401