1/* 2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10/include/ "skeleton_hs_idu.dtsi" 11 12/ { 13 model = "snps,nsim_hs-smp"; 14 compatible = "snps,nsim_hs"; 15 interrupt-parent = <&core_intc>; 16 17 chosen { 18 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; 19 }; 20 21 aliases { 22 serial0 = &arcuart0; 23 }; 24 25 fpga { 26 compatible = "simple-bus"; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 /* child and parent address space 1:1 mapped */ 31 ranges; 32 33 core_clk: core_clk { 34 #clock-cells = <0>; 35 compatible = "fixed-clock"; 36 clock-frequency = <80000000>; 37 }; 38 39 core_intc: core-interrupt-controller { 40 compatible = "snps,archs-intc"; 41 interrupt-controller; 42 #interrupt-cells = <1>; 43 }; 44 45 idu_intc: idu-interrupt-controller { 46 compatible = "snps,archs-idu-intc"; 47 interrupt-controller; 48 interrupt-parent = <&core_intc>; 49 #interrupt-cells = <1>; 50 }; 51 52 arcuart0: serial@c0fc1000 { 53 compatible = "snps,arc-uart"; 54 reg = <0xc0fc1000 0x100>; 55 interrupt-parent = <&idu_intc>; 56 interrupts = <0>; 57 clock-frequency = <80000000>; 58 current-speed = <115200>; 59 status = "okay"; 60 }; 61 62 arcpct0: pct { 63 compatible = "snps,archs-pct"; 64 #interrupt-cells = <1>; 65 interrupts = <20>; 66 }; 67 }; 68}; 69