1 /*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
11
12 /* Build Configuration Registers */
13 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
14 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
15 #define ARC_REG_CRC_BCR 0x62
16 #define ARC_REG_VECBASE_BCR 0x68
17 #define ARC_REG_PERIBASE_BCR 0x69
18 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
19 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
20 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
21 #define ARC_REG_SLC_BCR 0xce
22 #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
23 #define ARC_REG_AP_BCR 0x76
24 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
25 #define ARC_REG_XY_MEM_BCR 0x79
26 #define ARC_REG_MAC_BCR 0x7a
27 #define ARC_REG_MUL_BCR 0x7b
28 #define ARC_REG_SWAP_BCR 0x7c
29 #define ARC_REG_NORM_BCR 0x7d
30 #define ARC_REG_MIXMAX_BCR 0x7e
31 #define ARC_REG_BARREL_BCR 0x7f
32 #define ARC_REG_D_UNCACH_BCR 0x6A
33 #define ARC_REG_BPU_BCR 0xc0
34 #define ARC_REG_ISA_CFG_BCR 0xc1
35 #define ARC_REG_RTT_BCR 0xF2
36 #define ARC_REG_IRQ_BCR 0xF3
37 #define ARC_REG_SMART_BCR 0xFF
38 #define ARC_REG_CLUSTER_BCR 0xcf
39 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
40
41 /* Common for ARCompact and ARCv2 status register */
42 #define ARC_REG_STATUS32 0x0A
43
44 /* status32 Bits Positions */
45 #define STATUS_AE_BIT 5 /* Exception active */
46 #define STATUS_DE_BIT 6 /* PC is in delay slot */
47 #define STATUS_U_BIT 7 /* User/Kernel mode */
48 #define STATUS_Z_BIT 11
49 #define STATUS_L_BIT 12 /* Loop inhibit */
50
51 /* These masks correspond to the status word(STATUS_32) bits */
52 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
53 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
54 #define STATUS_U_MASK (1<<STATUS_U_BIT)
55 #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
56 #define STATUS_L_MASK (1<<STATUS_L_BIT)
57
58 /*
59 * ECR: Exception Cause Reg bits-n-pieces
60 * [23:16] = Exception Vector
61 * [15: 8] = Exception Cause Code
62 * [ 7: 0] = Exception Parameters (for certain types only)
63 */
64 #ifdef CONFIG_ISA_ARCOMPACT
65 #define ECR_V_MEM_ERR 0x01
66 #define ECR_V_INSN_ERR 0x02
67 #define ECR_V_MACH_CHK 0x20
68 #define ECR_V_ITLB_MISS 0x21
69 #define ECR_V_DTLB_MISS 0x22
70 #define ECR_V_PROTV 0x23
71 #define ECR_V_TRAP 0x25
72 #else
73 #define ECR_V_MEM_ERR 0x01
74 #define ECR_V_INSN_ERR 0x02
75 #define ECR_V_MACH_CHK 0x03
76 #define ECR_V_ITLB_MISS 0x04
77 #define ECR_V_DTLB_MISS 0x05
78 #define ECR_V_PROTV 0x06
79 #define ECR_V_TRAP 0x09
80 #endif
81
82 /* DTLB Miss and Protection Violation Cause Codes */
83
84 #define ECR_C_PROTV_INST_FETCH 0x00
85 #define ECR_C_PROTV_LOAD 0x01
86 #define ECR_C_PROTV_STORE 0x02
87 #define ECR_C_PROTV_XCHG 0x03
88 #define ECR_C_PROTV_MISALIG_DATA 0x04
89
90 #define ECR_C_BIT_PROTV_MISALIG_DATA 10
91
92 /* Machine Check Cause Code Values */
93 #define ECR_C_MCHK_DUP_TLB 0x01
94
95 /* DTLB Miss Exception Cause Code Values */
96 #define ECR_C_BIT_DTLB_LD_MISS 8
97 #define ECR_C_BIT_DTLB_ST_MISS 9
98
99 /* Auxiliary registers */
100 #define AUX_IDENTITY 4
101 #define AUX_EXEC_CTRL 8
102 #define AUX_INTR_VEC_BASE 0x25
103 #define AUX_VOL 0x5e
104
105 /*
106 * Floating Pt Registers
107 * Status regs are read-only (build-time) so need not be saved/restored
108 */
109 #define ARC_AUX_FP_STAT 0x300
110 #define ARC_AUX_DPFP_1L 0x301
111 #define ARC_AUX_DPFP_1H 0x302
112 #define ARC_AUX_DPFP_2L 0x303
113 #define ARC_AUX_DPFP_2H 0x304
114 #define ARC_AUX_DPFP_STAT 0x305
115
116 #ifndef __ASSEMBLY__
117
118 #include <soc/arc/aux.h>
119
120 /* Helpers */
121 #define TO_KB(bytes) ((bytes) >> 10)
122 #define TO_MB(bytes) (TO_KB(bytes) >> 10)
123 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
124 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
125
126
127 /*
128 ***************************************************************
129 * Build Configuration Registers, with encoded hardware config
130 */
131 struct bcr_identity {
132 #ifdef CONFIG_CPU_BIG_ENDIAN
133 unsigned int chip_id:16, cpu_id:8, family:8;
134 #else
135 unsigned int family:8, cpu_id:8, chip_id:16;
136 #endif
137 };
138
139 struct bcr_isa_arcv2 {
140 #ifdef CONFIG_CPU_BIG_ENDIAN
141 unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
142 pad1:12, ver:8;
143 #else
144 unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
145 ldd:1, pad2:4, div_rem:4;
146 #endif
147 };
148
149 struct bcr_mpy {
150 #ifdef CONFIG_CPU_BIG_ENDIAN
151 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
152 #else
153 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
154 #endif
155 };
156
157 struct bcr_extn_xymem {
158 #ifdef CONFIG_CPU_BIG_ENDIAN
159 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
160 #else
161 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
162 #endif
163 };
164
165 struct bcr_iccm_arcompact {
166 #ifdef CONFIG_CPU_BIG_ENDIAN
167 unsigned int base:16, pad:5, sz:3, ver:8;
168 #else
169 unsigned int ver:8, sz:3, pad:5, base:16;
170 #endif
171 };
172
173 struct bcr_iccm_arcv2 {
174 #ifdef CONFIG_CPU_BIG_ENDIAN
175 unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
176 #else
177 unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
178 #endif
179 };
180
181 struct bcr_dccm_arcompact {
182 #ifdef CONFIG_CPU_BIG_ENDIAN
183 unsigned int res:21, sz:3, ver:8;
184 #else
185 unsigned int ver:8, sz:3, res:21;
186 #endif
187 };
188
189 struct bcr_dccm_arcv2 {
190 #ifdef CONFIG_CPU_BIG_ENDIAN
191 unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
192 #else
193 unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
194 #endif
195 };
196
197 /* ARCompact: Both SP and DP FPU BCRs have same format */
198 struct bcr_fp_arcompact {
199 #ifdef CONFIG_CPU_BIG_ENDIAN
200 unsigned int fast:1, ver:8;
201 #else
202 unsigned int ver:8, fast:1;
203 #endif
204 };
205
206 struct bcr_fp_arcv2 {
207 #ifdef CONFIG_CPU_BIG_ENDIAN
208 unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
209 #else
210 unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
211 #endif
212 };
213
214 #include <soc/arc/timers.h>
215
216 struct bcr_bpu_arcompact {
217 #ifdef CONFIG_CPU_BIG_ENDIAN
218 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
219 #else
220 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
221 #endif
222 };
223
224 struct bcr_bpu_arcv2 {
225 #ifdef CONFIG_CPU_BIG_ENDIAN
226 unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
227 #else
228 unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
229 #endif
230 };
231
232 struct bcr_generic {
233 #ifdef CONFIG_CPU_BIG_ENDIAN
234 unsigned int info:24, ver:8;
235 #else
236 unsigned int ver:8, info:24;
237 #endif
238 };
239
240 /*
241 *******************************************************************
242 * Generic structures to hold build configuration used at runtime
243 */
244
245 struct cpuinfo_arc_mmu {
246 unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
247 unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
248 };
249
250 struct cpuinfo_arc_cache {
251 unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
252 };
253
254 struct cpuinfo_arc_bpu {
255 unsigned int ver, full, num_cache, num_pred;
256 };
257
258 struct cpuinfo_arc_ccm {
259 unsigned int base_addr, sz;
260 };
261
262 struct cpuinfo_arc {
263 struct cpuinfo_arc_cache icache, dcache, slc;
264 struct cpuinfo_arc_mmu mmu;
265 struct cpuinfo_arc_bpu bpu;
266 struct bcr_identity core;
267 struct bcr_isa_arcv2 isa;
268 const char *details, *name;
269 unsigned int vec_base;
270 struct cpuinfo_arc_ccm iccm, dccm;
271 struct {
272 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
273 fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
274 debug:1, ap:1, smart:1, rtt:1, pad3:4,
275 timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
276 } extn;
277 struct bcr_mpy extn_mpy;
278 struct bcr_extn_xymem extn_xymem;
279 };
280
281 extern struct cpuinfo_arc cpuinfo_arc700[];
282
is_isa_arcv2(void)283 static inline int is_isa_arcv2(void)
284 {
285 return IS_ENABLED(CONFIG_ISA_ARCV2);
286 }
287
is_isa_arcompact(void)288 static inline int is_isa_arcompact(void)
289 {
290 return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
291 }
292
293 #endif /* __ASEMBLY__ */
294
295 #endif /* _ASM_ARC_ARCREGS_H */
296