1/* 2 * Device Tree Include file for Marvell Armada 370 family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively, 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use, 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 * 48 * Contains definitions specific to the Armada 370 SoC that are not 49 * common to all Armada SoCs. 50 */ 51 52#include "armada-370-xp.dtsi" 53 54/ { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 model = "Marvell Armada 370 family SoC"; 59 compatible = "marvell,armada370", "marvell,armada-370-xp"; 60 61 aliases { 62 gpio0 = &gpio0; 63 gpio1 = &gpio1; 64 gpio2 = &gpio2; 65 }; 66 67 soc { 68 compatible = "marvell,armada370-mbus", "simple-bus"; 69 70 bootrom { 71 compatible = "marvell,bootrom"; 72 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; 73 }; 74 75 pciec: pcie@82000000 { 76 compatible = "marvell,armada-370-pcie"; 77 status = "disabled"; 78 device_type = "pci"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 83 msi-parent = <&mpic>; 84 bus-range = <0x00 0xff>; 85 86 ranges = 87 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 88 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 89 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 90 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 91 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 92 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 93 94 pcie0: pcie@1,0 { 95 device_type = "pci"; 96 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 97 reg = <0x0800 0 0 0 0>; 98 #address-cells = <3>; 99 #size-cells = <2>; 100 #interrupt-cells = <1>; 101 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 102 0x81000000 0 0 0x81000000 0x1 0 1 0>; 103 bus-range = <0x00 0xff>; 104 interrupt-map-mask = <0 0 0 0>; 105 interrupt-map = <0 0 0 0 &mpic 58>; 106 marvell,pcie-port = <0>; 107 marvell,pcie-lane = <0>; 108 clocks = <&gateclk 5>; 109 status = "disabled"; 110 }; 111 112 pcie2: pcie@2,0 { 113 device_type = "pci"; 114 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 115 reg = <0x1000 0 0 0 0>; 116 #address-cells = <3>; 117 #size-cells = <2>; 118 #interrupt-cells = <1>; 119 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 120 0x81000000 0 0 0x81000000 0x2 0 1 0>; 121 bus-range = <0x00 0xff>; 122 interrupt-map-mask = <0 0 0 0>; 123 interrupt-map = <0 0 0 0 &mpic 62>; 124 marvell,pcie-port = <1>; 125 marvell,pcie-lane = <0>; 126 clocks = <&gateclk 9>; 127 status = "disabled"; 128 }; 129 }; 130 131 internal-regs { 132 L2: l2-cache@8000 { 133 compatible = "marvell,aurora-outer-cache"; 134 reg = <0x08000 0x1000>; 135 cache-id-part = <0x100>; 136 cache-level = <2>; 137 cache-unified; 138 wt-override; 139 }; 140 141 gpio0: gpio@18100 { 142 compatible = "marvell,armada-370-gpio", 143 "marvell,orion-gpio"; 144 reg = <0x18100 0x40>, <0x181c0 0x08>; 145 reg-names = "gpio", "pwm"; 146 ngpios = <32>; 147 gpio-controller; 148 #gpio-cells = <2>; 149 #pwm-cells = <2>; 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 interrupts = <82>, <83>, <84>, <85>; 153 clocks = <&coreclk 0>; 154 }; 155 156 gpio1: gpio@18140 { 157 compatible = "marvell,armada-370-gpio", 158 "marvell,orion-gpio"; 159 reg = <0x18140 0x40>, <0x181c8 0x08>; 160 reg-names = "gpio", "pwm"; 161 ngpios = <32>; 162 gpio-controller; 163 #gpio-cells = <2>; 164 #pwm-cells = <2>; 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 interrupts = <87>, <88>, <89>, <90>; 168 clocks = <&coreclk 0>; 169 }; 170 171 gpio2: gpio@18180 { 172 compatible = "marvell,armada-370-gpio", 173 "marvell,orion-gpio"; 174 reg = <0x18180 0x40>; 175 ngpios = <2>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 interrupts = <91>; 181 }; 182 183 184 systemc: system-controller@18200 { 185 compatible = "marvell,armada-370-xp-system-controller"; 186 reg = <0x18200 0x100>; 187 }; 188 189 gateclk: clock-gating-control@18220 { 190 compatible = "marvell,armada-370-gating-clock"; 191 reg = <0x18220 0x4>; 192 clocks = <&coreclk 0>; 193 #clock-cells = <1>; 194 }; 195 196 coreclk: mvebu-sar@18230 { 197 compatible = "marvell,armada-370-core-clock"; 198 reg = <0x18230 0x08>; 199 #clock-cells = <1>; 200 }; 201 202 thermal: thermal@18300 { 203 compatible = "marvell,armada370-thermal"; 204 reg = <0x18300 0x4 205 0x18304 0x4>; 206 status = "okay"; 207 }; 208 209 sscg: sscg@18330 { 210 reg = <0x18330 0x4>; 211 }; 212 213 cpuconf: cpu-config@21000 { 214 compatible = "marvell,armada-370-cpu-config"; 215 reg = <0x21000 0x8>; 216 }; 217 218 audio_controller: audio-controller@30000 { 219 #sound-dai-cells = <1>; 220 compatible = "marvell,armada370-audio"; 221 reg = <0x30000 0x4000>; 222 interrupts = <93>; 223 clocks = <&gateclk 0>; 224 clock-names = "internal"; 225 status = "disabled"; 226 }; 227 228 xor0: xor@60800 { 229 compatible = "marvell,orion-xor"; 230 reg = <0x60800 0x100 231 0x60A00 0x100>; 232 status = "okay"; 233 234 xor00 { 235 interrupts = <51>; 236 dmacap,memcpy; 237 dmacap,xor; 238 }; 239 xor01 { 240 interrupts = <52>; 241 dmacap,memcpy; 242 dmacap,xor; 243 dmacap,memset; 244 }; 245 }; 246 247 xor1: xor@60900 { 248 compatible = "marvell,orion-xor"; 249 reg = <0x60900 0x100 250 0x60b00 0x100>; 251 status = "okay"; 252 253 xor10 { 254 interrupts = <94>; 255 dmacap,memcpy; 256 dmacap,xor; 257 }; 258 xor11 { 259 interrupts = <95>; 260 dmacap,memcpy; 261 dmacap,xor; 262 dmacap,memset; 263 }; 264 }; 265 266 cesa: crypto@90000 { 267 compatible = "marvell,armada-370-crypto"; 268 reg = <0x90000 0x10000>; 269 reg-names = "regs"; 270 interrupts = <48>; 271 clocks = <&gateclk 23>; 272 clock-names = "cesa0"; 273 marvell,crypto-srams = <&crypto_sram>; 274 marvell,crypto-sram-size = <0x7e0>; 275 }; 276 }; 277 278 crypto_sram: sa-sram { 279 compatible = "mmio-sram"; 280 reg = <MBUS_ID(0x09, 0x01) 0 0x800>; 281 reg-names = "sram"; 282 clocks = <&gateclk 23>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; 286 287 /* 288 * The Armada 370 has an erratum preventing the use of 289 * the standard workflow for CPU idle support (relying 290 * on the BootROM code to enter/exit idle state). 291 * Reserve some amount of the crypto SRAM to put the 292 * cpuidle workaround. 293 */ 294 idle-sram@0 { 295 reg = <0x0 0x20>; 296 }; 297 }; 298 }; 299}; 300 301/* 302 * Default UART pinctrl setting without RTS/CTS, can be overwritten on 303 * board level if a different configuration is used. 304 */ 305 306&uart0 { 307 pinctrl-0 = <&uart0_pins>; 308 pinctrl-names = "default"; 309}; 310 311&uart1 { 312 pinctrl-0 = <&uart1_pins>; 313 pinctrl-names = "default"; 314}; 315 316&i2c0 { 317 reg = <0x11000 0x20>; 318}; 319 320&i2c1 { 321 reg = <0x11100 0x20>; 322}; 323 324&mpic { 325 reg = <0x20a00 0x1d0>, <0x21870 0x58>; 326}; 327 328&timer { 329 compatible = "marvell,armada-370-timer"; 330 clocks = <&coreclk 2>; 331}; 332 333&watchdog { 334 compatible = "marvell,armada-370-wdt"; 335 clocks = <&coreclk 2>; 336}; 337 338&usb0 { 339 clocks = <&coreclk 0>; 340}; 341 342&usb1 { 343 clocks = <&coreclk 0>; 344}; 345 346ð0 { 347 compatible = "marvell,armada-370-neta"; 348}; 349 350ð1 { 351 compatible = "marvell,armada-370-neta"; 352}; 353 354&pinctrl { 355 compatible = "marvell,mv88f6710-pinctrl"; 356 357 spi0_pins1: spi0-pins1 { 358 marvell,pins = "mpp33", "mpp34", 359 "mpp35", "mpp36"; 360 marvell,function = "spi0"; 361 }; 362 363 spi0_pins2: spi0_pins2 { 364 marvell,pins = "mpp32", "mpp63", 365 "mpp64", "mpp65"; 366 marvell,function = "spi0"; 367 }; 368 369 spi1_pins: spi1-pins { 370 marvell,pins = "mpp49", "mpp50", 371 "mpp51", "mpp52"; 372 marvell,function = "spi1"; 373 }; 374 375 uart0_pins: uart0-pins { 376 marvell,pins = "mpp0", "mpp1"; 377 marvell,function = "uart0"; 378 }; 379 380 uart1_pins: uart1-pins { 381 marvell,pins = "mpp41", "mpp42"; 382 marvell,function = "uart1"; 383 }; 384 385 sdio_pins1: sdio-pins1 { 386 marvell,pins = "mpp9", "mpp11", "mpp12", 387 "mpp13", "mpp14", "mpp15"; 388 marvell,function = "sd0"; 389 }; 390 391 sdio_pins2: sdio-pins2 { 392 marvell,pins = "mpp47", "mpp48", "mpp49", 393 "mpp50", "mpp51", "mpp52"; 394 marvell,function = "sd0"; 395 }; 396 397 sdio_pins3: sdio-pins3 { 398 marvell,pins = "mpp48", "mpp49", "mpp50", 399 "mpp51", "mpp52", "mpp53"; 400 marvell,function = "sd0"; 401 }; 402 403 i2c0_pins: i2c0-pins { 404 marvell,pins = "mpp2", "mpp3"; 405 marvell,function = "i2c0"; 406 }; 407 408 i2s_pins1: i2s-pins1 { 409 marvell,pins = "mpp5", "mpp6", "mpp7", 410 "mpp8", "mpp9", "mpp10", 411 "mpp12", "mpp13"; 412 marvell,function = "audio"; 413 }; 414 415 i2s_pins2: i2s-pins2 { 416 marvell,pins = "mpp49", "mpp47", "mpp50", 417 "mpp59", "mpp57", "mpp61", 418 "mpp62", "mpp60", "mpp58"; 419 marvell,function = "audio"; 420 }; 421 422 mdio_pins: mdio-pins { 423 marvell,pins = "mpp17", "mpp18"; 424 marvell,function = "ge"; 425 }; 426 427 ge0_rgmii_pins: ge0-rgmii-pins { 428 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", 429 "mpp9", "mpp10", "mpp11", "mpp12", 430 "mpp13", "mpp14", "mpp15", "mpp16"; 431 marvell,function = "ge0"; 432 }; 433 434 ge1_rgmii_pins: ge1-rgmii-pins { 435 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", 436 "mpp23", "mpp24", "mpp25", "mpp26", 437 "mpp27", "mpp28", "mpp29", "mpp30"; 438 marvell,function = "ge1"; 439 }; 440}; 441 442/* 443 * Default SPI pinctrl setting, can be overwritten on 444 * board level if a different configuration is used. 445 */ 446&spi0 { 447 compatible = "marvell,armada-370-spi", "marvell,orion-spi"; 448 pinctrl-0 = <&spi0_pins1>; 449 pinctrl-names = "default"; 450}; 451 452&spi1 { 453 compatible = "marvell,armada-370-spi", "marvell,orion-spi"; 454 pinctrl-0 = <&spi1_pins>; 455 pinctrl-names = "default"; 456}; 457