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1// SPDX-License-Identifier: GPL-2.0
2#include "skeleton.dtsi"
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2500";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			compatible = "arm,arm1176jzf-s";
17			device_type = "cpu";
18			reg = <0>;
19		};
20	};
21
22	ahb {
23		compatible = "simple-bus";
24		#address-cells = <1>;
25		#size-cells = <1>;
26		ranges;
27
28		fmc: flash-controller@1e620000 {
29			reg = < 0x1e620000 0xc4
30				0x20000000 0x10000000 >;
31			#address-cells = <1>;
32			#size-cells = <0>;
33			compatible = "aspeed,ast2500-fmc";
34			status = "disabled";
35			interrupts = <19>;
36			flash@0 {
37				reg = < 0 >;
38				compatible = "jedec,spi-nor";
39				status = "disabled";
40			};
41			flash@1 {
42				reg = < 1 >;
43				compatible = "jedec,spi-nor";
44				status = "disabled";
45			};
46			flash@2 {
47				reg = < 2 >;
48				compatible = "jedec,spi-nor";
49				status = "disabled";
50			};
51		};
52
53		spi1: flash-controller@1e630000 {
54			reg = < 0x1e630000 0xc4
55				0x30000000 0x08000000 >;
56			#address-cells = <1>;
57			#size-cells = <0>;
58			compatible = "aspeed,ast2500-spi";
59			status = "disabled";
60			flash@0 {
61				reg = < 0 >;
62				compatible = "jedec,spi-nor";
63				status = "disabled";
64			};
65			flash@1 {
66				reg = < 1 >;
67				compatible = "jedec,spi-nor";
68				status = "disabled";
69			};
70		};
71
72		spi2: flash-controller@1e631000 {
73			reg = < 0x1e631000 0xc4
74				0x38000000 0x08000000 >;
75			#address-cells = <1>;
76			#size-cells = <0>;
77			compatible = "aspeed,ast2500-spi";
78			status = "disabled";
79			flash@0 {
80				reg = < 0 >;
81				compatible = "jedec,spi-nor";
82				status = "disabled";
83			};
84			flash@1 {
85				reg = < 1 >;
86				compatible = "jedec,spi-nor";
87				status = "disabled";
88			};
89		};
90
91		vic: interrupt-controller@1e6c0080 {
92			compatible = "aspeed,ast2400-vic";
93			interrupt-controller;
94			#interrupt-cells = <1>;
95			valid-sources = <0xfefff7ff 0x0807ffff>;
96			reg = <0x1e6c0080 0x80>;
97		};
98
99		mac0: ethernet@1e660000 {
100			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
101			reg = <0x1e660000 0x180>;
102			interrupts = <2>;
103			status = "disabled";
104		};
105
106		mac1: ethernet@1e680000 {
107			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
108			reg = <0x1e680000 0x180>;
109			interrupts = <3>;
110			status = "disabled";
111		};
112
113		apb {
114			compatible = "simple-bus";
115			#address-cells = <1>;
116			#size-cells = <1>;
117			ranges;
118
119			syscon: syscon@1e6e2000 {
120				compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
121				reg = <0x1e6e2000 0x1a8>;
122				#address-cells = <1>;
123				#size-cells = <0>;
124
125				clk_clkin: clk_clkin@70 {
126					#clock-cells = <0>;
127					compatible = "aspeed,g5-clkin-clock", "fixed-clock";
128					reg = <0x70>;
129					clock-frequency = <24000000>;
130				};
131
132				clk_hpll: clk_hpll@24 {
133					#clock-cells = <0>;
134					compatible = "aspeed,g5-hpll-clock", "fixed-clock";
135					reg = <0x24>;
136					clocks = <&clk_clkin>;
137					clock-frequency = <792000000>;
138				};
139
140				clk_ahb: clk_ahb@70 {
141					#clock-cells = <0>;
142					compatible = "aspeed,g5-ahb-clock", "fixed-clock";
143					reg = <0x70>;
144					clocks = <&clk_hpll>;
145					clock-frequency = <198000000>;
146				};
147
148				clk_apb: clk_apb@08 {
149					#clock-cells = <0>;
150					compatible = "aspeed,g5-apb-clock", "fixed-clock";
151					reg = <0x08>;
152					clocks = <&clk_hpll>;
153					clock-frequency = <24750000>;
154				};
155
156				clk_uart: clk_uart@2c {
157					#clock-cells = <0>;
158					compatible = "aspeed,uart-clock", "fixed-clock";
159					reg = <0x2c>;
160					clock-frequency = <24000000>;
161				};
162
163				pinctrl: pinctrl {
164					compatible = "aspeed,g5-pinctrl";
165					aspeed,external-nodes = <&gfx &lhc>;
166
167					pinctrl_acpi_default: acpi_default {
168						function = "ACPI";
169						groups = "ACPI";
170					};
171
172					pinctrl_adc0_default: adc0_default {
173						function = "ADC0";
174						groups = "ADC0";
175					};
176
177					pinctrl_adc1_default: adc1_default {
178						function = "ADC1";
179						groups = "ADC1";
180					};
181
182					pinctrl_adc10_default: adc10_default {
183						function = "ADC10";
184						groups = "ADC10";
185					};
186
187					pinctrl_adc11_default: adc11_default {
188						function = "ADC11";
189						groups = "ADC11";
190					};
191
192					pinctrl_adc12_default: adc12_default {
193						function = "ADC12";
194						groups = "ADC12";
195					};
196
197					pinctrl_adc13_default: adc13_default {
198						function = "ADC13";
199						groups = "ADC13";
200					};
201
202					pinctrl_adc14_default: adc14_default {
203						function = "ADC14";
204						groups = "ADC14";
205					};
206
207					pinctrl_adc15_default: adc15_default {
208						function = "ADC15";
209						groups = "ADC15";
210					};
211
212					pinctrl_adc2_default: adc2_default {
213						function = "ADC2";
214						groups = "ADC2";
215					};
216
217					pinctrl_adc3_default: adc3_default {
218						function = "ADC3";
219						groups = "ADC3";
220					};
221
222					pinctrl_adc4_default: adc4_default {
223						function = "ADC4";
224						groups = "ADC4";
225					};
226
227					pinctrl_adc5_default: adc5_default {
228						function = "ADC5";
229						groups = "ADC5";
230					};
231
232					pinctrl_adc6_default: adc6_default {
233						function = "ADC6";
234						groups = "ADC6";
235					};
236
237					pinctrl_adc7_default: adc7_default {
238						function = "ADC7";
239						groups = "ADC7";
240					};
241
242					pinctrl_adc8_default: adc8_default {
243						function = "ADC8";
244						groups = "ADC8";
245					};
246
247					pinctrl_adc9_default: adc9_default {
248						function = "ADC9";
249						groups = "ADC9";
250					};
251
252					pinctrl_bmcint_default: bmcint_default {
253						function = "BMCINT";
254						groups = "BMCINT";
255					};
256
257					pinctrl_ddcclk_default: ddcclk_default {
258						function = "DDCCLK";
259						groups = "DDCCLK";
260					};
261
262					pinctrl_ddcdat_default: ddcdat_default {
263						function = "DDCDAT";
264						groups = "DDCDAT";
265					};
266
267					pinctrl_espi_default: espi_default {
268						function = "ESPI";
269						groups = "ESPI";
270					};
271
272					pinctrl_fwspics1_default: fwspics1_default {
273						function = "FWSPICS1";
274						groups = "FWSPICS1";
275					};
276
277					pinctrl_fwspics2_default: fwspics2_default {
278						function = "FWSPICS2";
279						groups = "FWSPICS2";
280					};
281
282					pinctrl_gpid0_default: gpid0_default {
283						function = "GPID0";
284						groups = "GPID0";
285					};
286
287					pinctrl_gpid2_default: gpid2_default {
288						function = "GPID2";
289						groups = "GPID2";
290					};
291
292					pinctrl_gpid4_default: gpid4_default {
293						function = "GPID4";
294						groups = "GPID4";
295					};
296
297					pinctrl_gpid6_default: gpid6_default {
298						function = "GPID6";
299						groups = "GPID6";
300					};
301
302					pinctrl_gpie0_default: gpie0_default {
303						function = "GPIE0";
304						groups = "GPIE0";
305					};
306
307					pinctrl_gpie2_default: gpie2_default {
308						function = "GPIE2";
309						groups = "GPIE2";
310					};
311
312					pinctrl_gpie4_default: gpie4_default {
313						function = "GPIE4";
314						groups = "GPIE4";
315					};
316
317					pinctrl_gpie6_default: gpie6_default {
318						function = "GPIE6";
319						groups = "GPIE6";
320					};
321
322					pinctrl_i2c10_default: i2c10_default {
323						function = "I2C10";
324						groups = "I2C10";
325					};
326
327					pinctrl_i2c11_default: i2c11_default {
328						function = "I2C11";
329						groups = "I2C11";
330					};
331
332					pinctrl_i2c12_default: i2c12_default {
333						function = "I2C12";
334						groups = "I2C12";
335					};
336
337					pinctrl_i2c13_default: i2c13_default {
338						function = "I2C13";
339						groups = "I2C13";
340					};
341
342					pinctrl_i2c14_default: i2c14_default {
343						function = "I2C14";
344						groups = "I2C14";
345					};
346
347					pinctrl_i2c3_default: i2c3_default {
348						function = "I2C3";
349						groups = "I2C3";
350					};
351
352					pinctrl_i2c4_default: i2c4_default {
353						function = "I2C4";
354						groups = "I2C4";
355					};
356
357					pinctrl_i2c5_default: i2c5_default {
358						function = "I2C5";
359						groups = "I2C5";
360					};
361
362					pinctrl_i2c6_default: i2c6_default {
363						function = "I2C6";
364						groups = "I2C6";
365					};
366
367					pinctrl_i2c7_default: i2c7_default {
368						function = "I2C7";
369						groups = "I2C7";
370					};
371
372					pinctrl_i2c8_default: i2c8_default {
373						function = "I2C8";
374						groups = "I2C8";
375					};
376
377					pinctrl_i2c9_default: i2c9_default {
378						function = "I2C9";
379						groups = "I2C9";
380					};
381
382					pinctrl_lad0_default: lad0_default {
383						function = "LAD0";
384						groups = "LAD0";
385					};
386					pinctrl_lad1_default: lad1_default {
387						function = "LAD1";
388						groups = "LAD1";
389					};
390
391					pinctrl_lad2_default: lad2_default {
392						function = "LAD2";
393						groups = "LAD2";
394					};
395
396					pinctrl_lad3_default: lad3_default {
397						function = "LAD3";
398						groups = "LAD3";
399					};
400
401					pinctrl_lclk_default: lclk_default {
402						function = "LCLK";
403						groups = "LCLK";
404					};
405
406					pinctrl_lframe_default: lframe_default {
407						function = "LFRAME";
408						groups = "LFRAME";
409					};
410
411					pinctrl_lpchc_default: lpchc_default {
412						function = "LPCHC";
413						groups = "LPCHC";
414					};
415
416					pinctrl_lpcpd_default: lpcpd_default {
417						function = "LPCPD";
418						groups = "LPCPD";
419					};
420
421					pinctrl_lpcplus_default: lpcplus_default {
422						function = "LPCPLUS";
423						groups = "LPCPLUS";
424					};
425
426					pinctrl_lpcpme_default: lpcpme_default {
427						function = "LPCPME";
428						groups = "LPCPME";
429					};
430
431					pinctrl_lpcrst_default: lpcrst_default {
432						function = "LPCRST";
433						groups = "LPCRST";
434					};
435
436					pinctrl_lpcsmi_default: lpcsmi_default {
437						function = "LPCSMI";
438						groups = "LPCSMI";
439					};
440
441					pinctrl_lsirq_default: lsirq_default {
442						function = "LSIRQ";
443						groups = "LSIRQ";
444					};
445
446					pinctrl_mac1link_default: mac1link_default {
447						function = "MAC1LINK";
448						groups = "MAC1LINK";
449					};
450
451					pinctrl_mac2link_default: mac2link_default {
452						function = "MAC2LINK";
453						groups = "MAC2LINK";
454					};
455
456					pinctrl_mdio1_default: mdio1_default {
457						function = "MDIO1";
458						groups = "MDIO1";
459					};
460
461					pinctrl_mdio2_default: mdio2_default {
462						function = "MDIO2";
463						groups = "MDIO2";
464					};
465
466					pinctrl_ncts1_default: ncts1_default {
467						function = "NCTS1";
468						groups = "NCTS1";
469					};
470
471					pinctrl_ncts2_default: ncts2_default {
472						function = "NCTS2";
473						groups = "NCTS2";
474					};
475
476					pinctrl_ncts3_default: ncts3_default {
477						function = "NCTS3";
478						groups = "NCTS3";
479					};
480
481					pinctrl_ncts4_default: ncts4_default {
482						function = "NCTS4";
483						groups = "NCTS4";
484					};
485
486					pinctrl_ndcd1_default: ndcd1_default {
487						function = "NDCD1";
488						groups = "NDCD1";
489					};
490
491					pinctrl_ndcd2_default: ndcd2_default {
492						function = "NDCD2";
493						groups = "NDCD2";
494					};
495
496					pinctrl_ndcd3_default: ndcd3_default {
497						function = "NDCD3";
498						groups = "NDCD3";
499					};
500
501					pinctrl_ndcd4_default: ndcd4_default {
502						function = "NDCD4";
503						groups = "NDCD4";
504					};
505
506					pinctrl_ndsr1_default: ndsr1_default {
507						function = "NDSR1";
508						groups = "NDSR1";
509					};
510
511					pinctrl_ndsr2_default: ndsr2_default {
512						function = "NDSR2";
513						groups = "NDSR2";
514					};
515
516					pinctrl_ndsr3_default: ndsr3_default {
517						function = "NDSR3";
518						groups = "NDSR3";
519					};
520
521					pinctrl_ndsr4_default: ndsr4_default {
522						function = "NDSR4";
523						groups = "NDSR4";
524					};
525
526					pinctrl_ndtr1_default: ndtr1_default {
527						function = "NDTR1";
528						groups = "NDTR1";
529					};
530
531					pinctrl_ndtr2_default: ndtr2_default {
532						function = "NDTR2";
533						groups = "NDTR2";
534					};
535
536					pinctrl_ndtr3_default: ndtr3_default {
537						function = "NDTR3";
538						groups = "NDTR3";
539					};
540
541					pinctrl_ndtr4_default: ndtr4_default {
542						function = "NDTR4";
543						groups = "NDTR4";
544					};
545
546					pinctrl_nri1_default: nri1_default {
547						function = "NRI1";
548						groups = "NRI1";
549					};
550
551					pinctrl_nri2_default: nri2_default {
552						function = "NRI2";
553						groups = "NRI2";
554					};
555
556					pinctrl_nri3_default: nri3_default {
557						function = "NRI3";
558						groups = "NRI3";
559					};
560
561					pinctrl_nri4_default: nri4_default {
562						function = "NRI4";
563						groups = "NRI4";
564					};
565
566					pinctrl_nrts1_default: nrts1_default {
567						function = "NRTS1";
568						groups = "NRTS1";
569					};
570
571					pinctrl_nrts2_default: nrts2_default {
572						function = "NRTS2";
573						groups = "NRTS2";
574					};
575
576					pinctrl_nrts3_default: nrts3_default {
577						function = "NRTS3";
578						groups = "NRTS3";
579					};
580
581					pinctrl_nrts4_default: nrts4_default {
582						function = "NRTS4";
583						groups = "NRTS4";
584					};
585
586					pinctrl_oscclk_default: oscclk_default {
587						function = "OSCCLK";
588						groups = "OSCCLK";
589					};
590
591					pinctrl_pewake_default: pewake_default {
592						function = "PEWAKE";
593						groups = "PEWAKE";
594					};
595
596					pinctrl_pnor_default: pnor_default {
597						function = "PNOR";
598						groups = "PNOR";
599					};
600
601					pinctrl_pwm0_default: pwm0_default {
602						function = "PWM0";
603						groups = "PWM0";
604					};
605
606					pinctrl_pwm1_default: pwm1_default {
607						function = "PWM1";
608						groups = "PWM1";
609					};
610
611					pinctrl_pwm2_default: pwm2_default {
612						function = "PWM2";
613						groups = "PWM2";
614					};
615
616					pinctrl_pwm3_default: pwm3_default {
617						function = "PWM3";
618						groups = "PWM3";
619					};
620
621					pinctrl_pwm4_default: pwm4_default {
622						function = "PWM4";
623						groups = "PWM4";
624					};
625
626					pinctrl_pwm5_default: pwm5_default {
627						function = "PWM5";
628						groups = "PWM5";
629					};
630
631					pinctrl_pwm6_default: pwm6_default {
632						function = "PWM6";
633						groups = "PWM6";
634					};
635
636					pinctrl_pwm7_default: pwm7_default {
637						function = "PWM7";
638						groups = "PWM7";
639					};
640
641					pinctrl_rgmii1_default: rgmii1_default {
642						function = "RGMII1";
643						groups = "RGMII1";
644					};
645
646					pinctrl_rgmii2_default: rgmii2_default {
647						function = "RGMII2";
648						groups = "RGMII2";
649					};
650
651					pinctrl_rmii1_default: rmii1_default {
652						function = "RMII1";
653						groups = "RMII1";
654					};
655
656					pinctrl_rmii2_default: rmii2_default {
657						function = "RMII2";
658						groups = "RMII2";
659					};
660
661					pinctrl_rxd1_default: rxd1_default {
662						function = "RXD1";
663						groups = "RXD1";
664					};
665
666					pinctrl_rxd2_default: rxd2_default {
667						function = "RXD2";
668						groups = "RXD2";
669					};
670
671					pinctrl_rxd3_default: rxd3_default {
672						function = "RXD3";
673						groups = "RXD3";
674					};
675
676					pinctrl_rxd4_default: rxd4_default {
677						function = "RXD4";
678						groups = "RXD4";
679					};
680
681					pinctrl_salt1_default: salt1_default {
682						function = "SALT1";
683						groups = "SALT1";
684					};
685
686					pinctrl_salt10_default: salt10_default {
687						function = "SALT10";
688						groups = "SALT10";
689					};
690
691					pinctrl_salt11_default: salt11_default {
692						function = "SALT11";
693						groups = "SALT11";
694					};
695
696					pinctrl_salt12_default: salt12_default {
697						function = "SALT12";
698						groups = "SALT12";
699					};
700
701					pinctrl_salt13_default: salt13_default {
702						function = "SALT13";
703						groups = "SALT13";
704					};
705
706					pinctrl_salt14_default: salt14_default {
707						function = "SALT14";
708						groups = "SALT14";
709					};
710
711					pinctrl_salt2_default: salt2_default {
712						function = "SALT2";
713						groups = "SALT2";
714					};
715
716					pinctrl_salt3_default: salt3_default {
717						function = "SALT3";
718						groups = "SALT3";
719					};
720
721					pinctrl_salt4_default: salt4_default {
722						function = "SALT4";
723						groups = "SALT4";
724					};
725
726					pinctrl_salt5_default: salt5_default {
727						function = "SALT5";
728						groups = "SALT5";
729					};
730
731					pinctrl_salt6_default: salt6_default {
732						function = "SALT6";
733						groups = "SALT6";
734					};
735
736					pinctrl_salt7_default: salt7_default {
737						function = "SALT7";
738						groups = "SALT7";
739					};
740
741					pinctrl_salt8_default: salt8_default {
742						function = "SALT8";
743						groups = "SALT8";
744					};
745
746					pinctrl_salt9_default: salt9_default {
747						function = "SALT9";
748						groups = "SALT9";
749					};
750
751					pinctrl_scl1_default: scl1_default {
752						function = "SCL1";
753						groups = "SCL1";
754					};
755
756					pinctrl_scl2_default: scl2_default {
757						function = "SCL2";
758						groups = "SCL2";
759					};
760
761					pinctrl_sd1_default: sd1_default {
762						function = "SD1";
763						groups = "SD1";
764					};
765
766					pinctrl_sd2_default: sd2_default {
767						function = "SD2";
768						groups = "SD2";
769					};
770
771					pinctrl_sda1_default: sda1_default {
772						function = "SDA1";
773						groups = "SDA1";
774					};
775
776					pinctrl_sda2_default: sda2_default {
777						function = "SDA2";
778						groups = "SDA2";
779					};
780
781					pinctrl_sgps1_default: sgps1_default {
782						function = "SGPS1";
783						groups = "SGPS1";
784					};
785
786					pinctrl_sgps2_default: sgps2_default {
787						function = "SGPS2";
788						groups = "SGPS2";
789					};
790
791					pinctrl_sioonctrl_default: sioonctrl_default {
792						function = "SIOONCTRL";
793						groups = "SIOONCTRL";
794					};
795
796					pinctrl_siopbi_default: siopbi_default {
797						function = "SIOPBI";
798						groups = "SIOPBI";
799					};
800
801					pinctrl_siopbo_default: siopbo_default {
802						function = "SIOPBO";
803						groups = "SIOPBO";
804					};
805
806					pinctrl_siopwreq_default: siopwreq_default {
807						function = "SIOPWREQ";
808						groups = "SIOPWREQ";
809					};
810
811					pinctrl_siopwrgd_default: siopwrgd_default {
812						function = "SIOPWRGD";
813						groups = "SIOPWRGD";
814					};
815
816					pinctrl_sios3_default: sios3_default {
817						function = "SIOS3";
818						groups = "SIOS3";
819					};
820
821					pinctrl_sios5_default: sios5_default {
822						function = "SIOS5";
823						groups = "SIOS5";
824					};
825
826					pinctrl_siosci_default: siosci_default {
827						function = "SIOSCI";
828						groups = "SIOSCI";
829					};
830
831					pinctrl_spi1_default: spi1_default {
832						function = "SPI1";
833						groups = "SPI1";
834					};
835
836					pinctrl_spi1cs1_default: spi1cs1_default {
837						function = "SPI1CS1";
838						groups = "SPI1CS1";
839					};
840
841					pinctrl_spi1debug_default: spi1debug_default {
842						function = "SPI1DEBUG";
843						groups = "SPI1DEBUG";
844					};
845
846					pinctrl_spi1passthru_default: spi1passthru_default {
847						function = "SPI1PASSTHRU";
848						groups = "SPI1PASSTHRU";
849					};
850
851					pinctrl_spi2ck_default: spi2ck_default {
852						function = "SPI2CK";
853						groups = "SPI2CK";
854					};
855
856					pinctrl_spi2cs0_default: spi2cs0_default {
857						function = "SPI2CS0";
858						groups = "SPI2CS0";
859					};
860
861					pinctrl_spi2cs1_default: spi2cs1_default {
862						function = "SPI2CS1";
863						groups = "SPI2CS1";
864					};
865
866					pinctrl_spi2miso_default: spi2miso_default {
867						function = "SPI2MISO";
868						groups = "SPI2MISO";
869					};
870
871					pinctrl_spi2mosi_default: spi2mosi_default {
872						function = "SPI2MOSI";
873						groups = "SPI2MOSI";
874					};
875
876					pinctrl_timer3_default: timer3_default {
877						function = "TIMER3";
878						groups = "TIMER3";
879					};
880
881					pinctrl_timer4_default: timer4_default {
882						function = "TIMER4";
883						groups = "TIMER4";
884					};
885
886					pinctrl_timer5_default: timer5_default {
887						function = "TIMER5";
888						groups = "TIMER5";
889					};
890
891					pinctrl_timer6_default: timer6_default {
892						function = "TIMER6";
893						groups = "TIMER6";
894					};
895
896					pinctrl_timer7_default: timer7_default {
897						function = "TIMER7";
898						groups = "TIMER7";
899					};
900
901					pinctrl_timer8_default: timer8_default {
902						function = "TIMER8";
903						groups = "TIMER8";
904					};
905
906					pinctrl_txd1_default: txd1_default {
907						function = "TXD1";
908						groups = "TXD1";
909					};
910
911					pinctrl_txd2_default: txd2_default {
912						function = "TXD2";
913						groups = "TXD2";
914					};
915
916					pinctrl_txd3_default: txd3_default {
917						function = "TXD3";
918						groups = "TXD3";
919					};
920
921					pinctrl_txd4_default: txd4_default {
922						function = "TXD4";
923						groups = "TXD4";
924					};
925
926					pinctrl_uart6_default: uart6_default {
927						function = "UART6";
928						groups = "UART6";
929					};
930
931					pinctrl_usbcki_default: usbcki_default {
932						function = "USBCKI";
933						groups = "USBCKI";
934					};
935
936					pinctrl_vgabiosrom_default: vgabiosrom_default {
937						function = "VGABIOSROM";
938						groups = "VGABIOSROM";
939					};
940
941					pinctrl_vgahs_default: vgahs_default {
942						function = "VGAHS";
943						groups = "VGAHS";
944					};
945
946					pinctrl_vgavs_default: vgavs_default {
947						function = "VGAVS";
948						groups = "VGAVS";
949					};
950
951					pinctrl_vpi24_default: vpi24_default {
952						function = "VPI24";
953						groups = "VPI24";
954					};
955
956					pinctrl_vpo_default: vpo_default {
957						function = "VPO";
958						groups = "VPO";
959					};
960
961					pinctrl_wdtrst1_default: wdtrst1_default {
962						function = "WDTRST1";
963						groups = "WDTRST1";
964					};
965
966					pinctrl_wdtrst2_default: wdtrst2_default {
967						function = "WDTRST2";
968						groups = "WDTRST2";
969					};
970
971				};
972
973			};
974
975			gfx: display@1e6e6000 {
976				compatible = "aspeed,ast2500-gfx", "syscon";
977				reg = <0x1e6e6000 0x1000>;
978				reg-io-width = <4>;
979			};
980
981			sram@1e720000 {
982				compatible = "mmio-sram";
983				reg = <0x1e720000 0x9000>;	// 36K
984			};
985
986			gpio: gpio@1e780000 {
987				#gpio-cells = <2>;
988				gpio-controller;
989				compatible = "aspeed,ast2500-gpio";
990				reg = <0x1e780000 0x1000>;
991				interrupts = <20>;
992				gpio-ranges = <&pinctrl 0 0 220>;
993				interrupt-controller;
994			};
995
996			timer: timer@1e782000 {
997				/* This timer is a Faraday FTTMR010 derivative */
998				compatible = "aspeed,ast2400-timer";
999				reg = <0x1e782000 0x90>;
1000				interrupts = <16 17 18 35 36 37 38 39>;
1001				clocks = <&clk_apb>;
1002				clock-names = "PCLK";
1003			};
1004
1005
1006			wdt1: wdt@1e785000 {
1007				compatible = "aspeed,ast2500-wdt";
1008				reg = <0x1e785000 0x20>;
1009				interrupts = <27>;
1010			};
1011
1012			wdt2: wdt@1e785020 {
1013				compatible = "aspeed,ast2500-wdt";
1014				reg = <0x1e785020 0x20>;
1015				interrupts = <27>;
1016				status = "disabled";
1017			};
1018
1019			wdt3: wdt@1e785040 {
1020				compatible = "aspeed,ast2500-wdt";
1021				reg = <0x1e785040 0x20>;
1022				status = "disabled";
1023			};
1024
1025			uart1: serial@1e783000 {
1026				compatible = "ns16550a";
1027				reg = <0x1e783000 0x1000>;
1028				reg-shift = <2>;
1029				interrupts = <9>;
1030				clocks = <&clk_uart>;
1031				no-loopback-test;
1032				status = "disabled";
1033			};
1034
1035			lpc: lpc@1e789000 {
1036				compatible = "aspeed,ast2500-lpc", "simple-mfd";
1037				reg = <0x1e789000 0x1000>;
1038
1039				#address-cells = <1>;
1040				#size-cells = <1>;
1041				ranges = <0 0x1e789000 0x1000>;
1042
1043				lpc_bmc: lpc-bmc@0 {
1044					compatible = "aspeed,ast2500-lpc-bmc";
1045					reg = <0x0 0x80>;
1046				};
1047
1048				lpc_host: lpc-host@80 {
1049					compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
1050					reg = <0x80 0x1e0>;
1051
1052					#address-cells = <1>;
1053					#size-cells = <1>;
1054					ranges = <0 0x80 0x1e0>;
1055
1056					reg-io-width = <4>;
1057
1058					lhc: lhc@20 {
1059						compatible = "aspeed,ast2500-lhc";
1060						reg = <0x20 0x24 0x48 0x8>;
1061					};
1062				};
1063			};
1064
1065			uart2: serial@1e78d000 {
1066				compatible = "ns16550a";
1067				reg = <0x1e78d000 0x1000>;
1068				reg-shift = <2>;
1069				interrupts = <32>;
1070				clocks = <&clk_uart>;
1071				no-loopback-test;
1072				status = "disabled";
1073			};
1074
1075			uart3: serial@1e78e000 {
1076				compatible = "ns16550a";
1077				reg = <0x1e78e000 0x1000>;
1078				reg-shift = <2>;
1079				interrupts = <33>;
1080				clocks = <&clk_uart>;
1081				no-loopback-test;
1082				status = "disabled";
1083			};
1084
1085			uart4: serial@1e78f000 {
1086				compatible = "ns16550a";
1087				reg = <0x1e78f000 0x1000>;
1088				reg-shift = <2>;
1089				interrupts = <34>;
1090				clocks = <&clk_uart>;
1091				no-loopback-test;
1092				status = "disabled";
1093			};
1094
1095			uart5: serial@1e784000 {
1096				compatible = "ns16550a";
1097				reg = <0x1e784000 0x1000>;
1098				reg-shift = <2>;
1099				interrupts = <10>;
1100				clocks = <&clk_uart>;
1101				current-speed = <38400>;
1102				no-loopback-test;
1103				status = "disabled";
1104			};
1105
1106			uart6: serial@1e787000 {
1107				compatible = "ns16550a";
1108				reg = <0x1e787000 0x1000>;
1109				reg-shift = <2>;
1110				interrupts = <10>;
1111				clocks = <&clk_uart>;
1112				no-loopback-test;
1113				status = "disabled";
1114			};
1115
1116			adc: adc@1e6e9000 {
1117				compatible = "aspeed,ast2500-adc";
1118				reg = <0x1e6e9000 0xb0>;
1119				clocks = <&clk_apb>;
1120				#io-channel-cells = <1>;
1121				status = "disabled";
1122			};
1123		};
1124	};
1125};
1126