1/* 2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC 3 * applies to AT91SAM9G45, AT91SAM9M10, 4 * AT91SAM9G46, AT91SAM9M11 SoC 5 * 6 * Copyright (C) 2011 Atmel, 7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> 8 * 9 * Licensed under GPLv2 or later. 10 */ 11 12#include "skeleton.dtsi" 13#include <dt-bindings/dma/at91.h> 14#include <dt-bindings/pinctrl/at91.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/clock/at91.h> 18 19/ { 20 model = "Atmel AT91SAM9G45 family SoC"; 21 compatible = "atmel,at91sam9g45"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 serial1 = &usart0; 27 serial2 = &usart1; 28 serial3 = &usart2; 29 serial4 = &usart3; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 tcb0 = &tcb0; 36 tcb1 = &tcb1; 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 ssc0 = &ssc0; 40 ssc1 = &ssc1; 41 pwm0 = &pwm0; 42 }; 43 cpus { 44 #address-cells = <0>; 45 #size-cells = <0>; 46 47 cpu { 48 compatible = "arm,arm926ej-s"; 49 device_type = "cpu"; 50 }; 51 }; 52 53 memory { 54 reg = <0x70000000 0x10000000>; 55 }; 56 57 clocks { 58 slow_xtal: slow_xtal { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 62 }; 63 64 main_xtal: main_xtal { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <0>; 68 }; 69 70 adc_op_clk: adc_op_clk{ 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <300000>; 74 }; 75 }; 76 77 sram: sram@00300000 { 78 compatible = "mmio-sram"; 79 reg = <0x00300000 0x10000>; 80 }; 81 82 ahb { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 88 apb { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 94 aic: interrupt-controller@fffff000 { 95 #interrupt-cells = <3>; 96 compatible = "atmel,at91rm9200-aic"; 97 interrupt-controller; 98 reg = <0xfffff000 0x200>; 99 atmel,external-irqs = <31>; 100 }; 101 102 ramc0: ramc@ffffe400 { 103 compatible = "atmel,at91sam9g45-ddramc"; 104 reg = <0xffffe400 0x200>; 105 clocks = <&ddrck>; 106 clock-names = "ddrck"; 107 }; 108 109 ramc1: ramc@ffffe600 { 110 compatible = "atmel,at91sam9g45-ddramc"; 111 reg = <0xffffe600 0x200>; 112 clocks = <&ddrck>; 113 clock-names = "ddrck"; 114 }; 115 116 smc: smc@ffffe800 { 117 compatible = "atmel,at91sam9260-smc", "syscon"; 118 reg = <0xffffe800 0x200>; 119 }; 120 121 matrix: matrix@ffffea00 { 122 compatible = "atmel,at91sam9g45-matrix", "syscon"; 123 reg = <0xffffea00 0x200>; 124 }; 125 126 pmc: pmc@fffffc00 { 127 compatible = "atmel,at91sam9g45-pmc", "syscon"; 128 reg = <0xfffffc00 0x100>; 129 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 130 interrupt-controller; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 #interrupt-cells = <1>; 134 135 main_osc: main_osc { 136 compatible = "atmel,at91rm9200-clk-main-osc"; 137 #clock-cells = <0>; 138 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 139 clocks = <&main_xtal>; 140 }; 141 142 main: mainck { 143 compatible = "atmel,at91rm9200-clk-main"; 144 #clock-cells = <0>; 145 clocks = <&main_osc>; 146 }; 147 148 plla: pllack { 149 compatible = "atmel,at91rm9200-clk-pll"; 150 #clock-cells = <0>; 151 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 152 clocks = <&main>; 153 reg = <0>; 154 atmel,clk-input-range = <2000000 32000000>; 155 #atmel,pll-clk-output-range-cells = <4>; 156 atmel,pll-clk-output-ranges = <745000000 800000000 0 0 157 695000000 750000000 1 0 158 645000000 700000000 2 0 159 595000000 650000000 3 0 160 545000000 600000000 0 1 161 495000000 555000000 1 1 162 445000000 500000000 2 1 163 400000000 450000000 3 1>; 164 }; 165 166 plladiv: plladivck { 167 compatible = "atmel,at91sam9x5-clk-plldiv"; 168 #clock-cells = <0>; 169 clocks = <&plla>; 170 }; 171 172 utmi: utmick { 173 compatible = "atmel,at91sam9x5-clk-utmi"; 174 #clock-cells = <0>; 175 interrupts-extended = <&pmc AT91_PMC_LOCKU>; 176 clocks = <&main>; 177 }; 178 179 mck: masterck { 180 compatible = "atmel,at91rm9200-clk-master"; 181 #clock-cells = <0>; 182 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 183 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 184 atmel,clk-output-range = <0 133333333>; 185 atmel,clk-divisors = <1 2 4 3>; 186 }; 187 188 usb: usbck { 189 compatible = "atmel,at91sam9x5-clk-usb"; 190 #clock-cells = <0>; 191 clocks = <&plladiv>, <&utmi>; 192 }; 193 194 prog: progck { 195 compatible = "atmel,at91sam9g45-clk-programmable"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 interrupt-parent = <&pmc>; 199 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 200 201 prog0: prog0 { 202 #clock-cells = <0>; 203 reg = <0>; 204 interrupts = <AT91_PMC_PCKRDY(0)>; 205 }; 206 207 prog1: prog1 { 208 #clock-cells = <0>; 209 reg = <1>; 210 interrupts = <AT91_PMC_PCKRDY(1)>; 211 }; 212 }; 213 214 systemck { 215 compatible = "atmel,at91rm9200-clk-system"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 ddrck: ddrck { 220 #clock-cells = <0>; 221 reg = <2>; 222 clocks = <&mck>; 223 }; 224 225 uhpck: uhpck { 226 #clock-cells = <0>; 227 reg = <6>; 228 clocks = <&usb>; 229 }; 230 231 pck0: pck0 { 232 #clock-cells = <0>; 233 reg = <8>; 234 clocks = <&prog0>; 235 }; 236 237 pck1: pck1 { 238 #clock-cells = <0>; 239 reg = <9>; 240 clocks = <&prog1>; 241 }; 242 }; 243 244 periphck { 245 compatible = "atmel,at91rm9200-clk-peripheral"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 clocks = <&mck>; 249 250 pioA_clk: pioA_clk { 251 #clock-cells = <0>; 252 reg = <2>; 253 }; 254 255 pioB_clk: pioB_clk { 256 #clock-cells = <0>; 257 reg = <3>; 258 }; 259 260 pioC_clk: pioC_clk { 261 #clock-cells = <0>; 262 reg = <4>; 263 }; 264 265 pioDE_clk: pioDE_clk { 266 #clock-cells = <0>; 267 reg = <5>; 268 }; 269 270 trng_clk: trng_clk { 271 #clock-cells = <0>; 272 reg = <6>; 273 }; 274 275 usart0_clk: usart0_clk { 276 #clock-cells = <0>; 277 reg = <7>; 278 }; 279 280 usart1_clk: usart1_clk { 281 #clock-cells = <0>; 282 reg = <8>; 283 }; 284 285 usart2_clk: usart2_clk { 286 #clock-cells = <0>; 287 reg = <9>; 288 }; 289 290 usart3_clk: usart3_clk { 291 #clock-cells = <0>; 292 reg = <10>; 293 }; 294 295 mci0_clk: mci0_clk { 296 #clock-cells = <0>; 297 reg = <11>; 298 }; 299 300 twi0_clk: twi0_clk { 301 #clock-cells = <0>; 302 reg = <12>; 303 }; 304 305 twi1_clk: twi1_clk { 306 #clock-cells = <0>; 307 reg = <13>; 308 }; 309 310 spi0_clk: spi0_clk { 311 #clock-cells = <0>; 312 reg = <14>; 313 }; 314 315 spi1_clk: spi1_clk { 316 #clock-cells = <0>; 317 reg = <15>; 318 }; 319 320 ssc0_clk: ssc0_clk { 321 #clock-cells = <0>; 322 reg = <16>; 323 }; 324 325 ssc1_clk: ssc1_clk { 326 #clock-cells = <0>; 327 reg = <17>; 328 }; 329 330 tcb0_clk: tcb0_clk { 331 #clock-cells = <0>; 332 reg = <18>; 333 }; 334 335 pwm_clk: pwm_clk { 336 #clock-cells = <0>; 337 reg = <19>; 338 }; 339 340 adc_clk: adc_clk { 341 #clock-cells = <0>; 342 reg = <20>; 343 }; 344 345 dma0_clk: dma0_clk { 346 #clock-cells = <0>; 347 reg = <21>; 348 }; 349 350 uhphs_clk: uhphs_clk { 351 #clock-cells = <0>; 352 reg = <22>; 353 }; 354 355 lcd_clk: lcd_clk { 356 #clock-cells = <0>; 357 reg = <23>; 358 }; 359 360 ac97_clk: ac97_clk { 361 #clock-cells = <0>; 362 reg = <24>; 363 }; 364 365 macb0_clk: macb0_clk { 366 #clock-cells = <0>; 367 reg = <25>; 368 }; 369 370 isi_clk: isi_clk { 371 #clock-cells = <0>; 372 reg = <26>; 373 }; 374 375 udphs_clk: udphs_clk { 376 #clock-cells = <0>; 377 reg = <27>; 378 }; 379 380 aestdessha_clk: aestdessha_clk { 381 #clock-cells = <0>; 382 reg = <28>; 383 }; 384 385 mci1_clk: mci1_clk { 386 #clock-cells = <0>; 387 reg = <29>; 388 }; 389 390 vdec_clk: vdec_clk { 391 #clock-cells = <0>; 392 reg = <30>; 393 }; 394 }; 395 }; 396 397 rstc@fffffd00 { 398 compatible = "atmel,at91sam9g45-rstc"; 399 reg = <0xfffffd00 0x10>; 400 clocks = <&clk32k>; 401 }; 402 403 pit: timer@fffffd30 { 404 compatible = "atmel,at91sam9260-pit"; 405 reg = <0xfffffd30 0xf>; 406 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 407 clocks = <&mck>; 408 }; 409 410 411 shdwc@fffffd10 { 412 compatible = "atmel,at91sam9rl-shdwc"; 413 reg = <0xfffffd10 0x10>; 414 clocks = <&clk32k>; 415 }; 416 417 tcb0: timer@fff7c000 { 418 compatible = "atmel,at91rm9200-tcb"; 419 reg = <0xfff7c000 0x100>; 420 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 421 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; 422 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 423 }; 424 425 tcb1: timer@fffd4000 { 426 compatible = "atmel,at91rm9200-tcb"; 427 reg = <0xfffd4000 0x100>; 428 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 429 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; 430 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 431 }; 432 433 dma: dma-controller@ffffec00 { 434 compatible = "atmel,at91sam9g45-dma"; 435 reg = <0xffffec00 0x200>; 436 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 437 #dma-cells = <2>; 438 clocks = <&dma0_clk>; 439 clock-names = "dma_clk"; 440 }; 441 442 pinctrl@fffff200 { 443 #address-cells = <1>; 444 #size-cells = <1>; 445 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 446 ranges = <0xfffff200 0xfffff200 0xa00>; 447 448 atmel,mux-mask = < 449 /* A B */ 450 0xffffffff 0xffc003ff /* pioA */ 451 0xffffffff 0x800f8f00 /* pioB */ 452 0xffffffff 0x00000e00 /* pioC */ 453 0xffffffff 0xff0c1381 /* pioD */ 454 0xffffffff 0x81ffff81 /* pioE */ 455 >; 456 457 /* shared pinctrl settings */ 458 ac97 { 459 pinctrl_ac97: ac97-0 { 460 atmel,pins = 461 <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97RX */ 462 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97TX */ 463 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97FS */ 464 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* AC97CK */ 465 }; 466 }; 467 468 adc0 { 469 pinctrl_adc0_adtrg: adc0_adtrg { 470 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 471 }; 472 pinctrl_adc0_ad0: adc0_ad0 { 473 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 474 }; 475 pinctrl_adc0_ad1: adc0_ad1 { 476 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 477 }; 478 pinctrl_adc0_ad2: adc0_ad2 { 479 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 480 }; 481 pinctrl_adc0_ad3: adc0_ad3 { 482 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 483 }; 484 pinctrl_adc0_ad4: adc0_ad4 { 485 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 486 }; 487 pinctrl_adc0_ad5: adc0_ad5 { 488 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 489 }; 490 pinctrl_adc0_ad6: adc0_ad6 { 491 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 492 }; 493 pinctrl_adc0_ad7: adc0_ad7 { 494 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 495 }; 496 }; 497 498 dbgu { 499 pinctrl_dbgu: dbgu-0 { 500 atmel,pins = 501 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 502 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 503 }; 504 }; 505 506 i2c0 { 507 pinctrl_i2c0: i2c0-0 { 508 atmel,pins = 509 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ 510 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ 511 }; 512 }; 513 514 i2c1 { 515 pinctrl_i2c1: i2c1-0 { 516 atmel,pins = 517 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ 518 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ 519 }; 520 }; 521 522 isi { 523 pinctrl_isi_data_0_7: isi-0-data-0-7 { 524 atmel,pins = 525 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ 526 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ 527 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ 528 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ 529 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ 530 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ 531 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ 532 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ 533 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ 534 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ 535 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */ 536 }; 537 538 pinctrl_isi_data_8_9: isi-0-data-8-9 { 539 atmel,pins = 540 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ 541 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */ 542 }; 543 544 pinctrl_isi_data_10_11: isi-0-data-10-11 { 545 atmel,pins = 546 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ 547 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */ 548 }; 549 }; 550 551 usart0 { 552 pinctrl_usart0: usart0-0 { 553 atmel,pins = 554 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ 555 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 556 }; 557 558 pinctrl_usart0_rts: usart0_rts-0 { 559 atmel,pins = 560 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ 561 }; 562 563 pinctrl_usart0_cts: usart0_cts-0 { 564 atmel,pins = 565 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ 566 }; 567 }; 568 569 usart1 { 570 pinctrl_usart1: usart1-0 { 571 atmel,pins = 572 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ 573 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 574 }; 575 576 pinctrl_usart1_rts: usart1_rts-0 { 577 atmel,pins = 578 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ 579 }; 580 581 pinctrl_usart1_cts: usart1_cts-0 { 582 atmel,pins = 583 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ 584 }; 585 }; 586 587 usart2 { 588 pinctrl_usart2: usart2-0 { 589 atmel,pins = 590 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ 591 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ 592 }; 593 594 pinctrl_usart2_rts: usart2_rts-0 { 595 atmel,pins = 596 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ 597 }; 598 599 pinctrl_usart2_cts: usart2_cts-0 { 600 atmel,pins = 601 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ 602 }; 603 }; 604 605 usart3 { 606 pinctrl_usart3: usart3-0 { 607 atmel,pins = 608 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ 609 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 610 }; 611 612 pinctrl_usart3_rts: usart3_rts-0 { 613 atmel,pins = 614 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ 615 }; 616 617 pinctrl_usart3_cts: usart3_cts-0 { 618 atmel,pins = 619 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ 620 }; 621 }; 622 623 nand { 624 pinctrl_nand_rb: nand-rb-0 { 625 atmel,pins = 626 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 627 }; 628 629 pinctrl_nand_cs: nand-cs-0 { 630 atmel,pins = 631 <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 632 }; 633 }; 634 635 macb { 636 pinctrl_macb_rmii: macb_rmii-0 { 637 atmel,pins = 638 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 639 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 640 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 641 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 642 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 643 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 644 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 645 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 646 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 647 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ 648 }; 649 650 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 651 atmel,pins = 652 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ 653 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ 654 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ 655 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ 656 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 657 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 658 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ 659 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 660 }; 661 }; 662 663 mmc0 { 664 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 665 atmel,pins = 666 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ 667 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 668 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ 669 }; 670 671 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 672 atmel,pins = 673 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ 674 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ 675 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ 676 }; 677 678 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { 679 atmel,pins = 680 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ 681 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 682 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ 683 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ 684 }; 685 }; 686 687 mmc1 { 688 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { 689 atmel,pins = 690 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ 691 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ 692 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ 693 }; 694 695 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { 696 atmel,pins = 697 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ 698 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ 699 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ 700 }; 701 702 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { 703 atmel,pins = 704 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ 705 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 706 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ 707 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ 708 }; 709 }; 710 711 ssc0 { 712 pinctrl_ssc0_tx: ssc0_tx-0 { 713 atmel,pins = 714 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ 715 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ 716 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ 717 }; 718 719 pinctrl_ssc0_rx: ssc0_rx-0 { 720 atmel,pins = 721 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ 722 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ 723 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ 724 }; 725 }; 726 727 ssc1 { 728 pinctrl_ssc1_tx: ssc1_tx-0 { 729 atmel,pins = 730 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ 731 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ 732 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ 733 }; 734 735 pinctrl_ssc1_rx: ssc1_rx-0 { 736 atmel,pins = 737 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ 738 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ 739 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ 740 }; 741 }; 742 743 spi0 { 744 pinctrl_spi0: spi0-0 { 745 atmel,pins = 746 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ 747 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ 748 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ 749 }; 750 }; 751 752 spi1 { 753 pinctrl_spi1: spi1-0 { 754 atmel,pins = 755 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ 756 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ 757 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ 758 }; 759 }; 760 761 tcb0 { 762 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 763 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 764 }; 765 766 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 767 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 768 }; 769 770 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 771 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 772 }; 773 774 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 775 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 776 }; 777 778 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 779 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 780 }; 781 782 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 783 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 784 }; 785 786 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 787 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 788 }; 789 790 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 791 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 792 }; 793 794 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 795 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; 796 }; 797 }; 798 799 tcb1 { 800 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 801 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 802 }; 803 804 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 805 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 806 }; 807 808 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 809 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 810 }; 811 812 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 813 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 814 }; 815 816 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 817 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 818 }; 819 820 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 821 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 822 }; 823 824 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 825 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 826 }; 827 828 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 829 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 830 }; 831 832 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 833 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 834 }; 835 }; 836 837 fb { 838 pinctrl_fb: fb-0 { 839 atmel,pins = 840 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ 841 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ 842 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ 843 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ 844 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ 845 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ 846 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ 847 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ 848 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ 849 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ 850 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ 851 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ 852 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ 853 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ 854 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ 855 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ 856 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ 857 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ 858 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ 859 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ 860 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ 861 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ 862 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ 863 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ 864 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ 865 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ 866 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ 867 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ 868 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ 869 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ 870 }; 871 }; 872 873 pioA: gpio@fffff200 { 874 compatible = "atmel,at91rm9200-gpio"; 875 reg = <0xfffff200 0x200>; 876 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 877 #gpio-cells = <2>; 878 gpio-controller; 879 interrupt-controller; 880 #interrupt-cells = <2>; 881 clocks = <&pioA_clk>; 882 }; 883 884 pioB: gpio@fffff400 { 885 compatible = "atmel,at91rm9200-gpio"; 886 reg = <0xfffff400 0x200>; 887 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 888 #gpio-cells = <2>; 889 gpio-controller; 890 interrupt-controller; 891 #interrupt-cells = <2>; 892 clocks = <&pioB_clk>; 893 }; 894 895 pioC: gpio@fffff600 { 896 compatible = "atmel,at91rm9200-gpio"; 897 reg = <0xfffff600 0x200>; 898 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 899 #gpio-cells = <2>; 900 gpio-controller; 901 interrupt-controller; 902 #interrupt-cells = <2>; 903 clocks = <&pioC_clk>; 904 }; 905 906 pioD: gpio@fffff800 { 907 compatible = "atmel,at91rm9200-gpio"; 908 reg = <0xfffff800 0x200>; 909 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 910 #gpio-cells = <2>; 911 gpio-controller; 912 interrupt-controller; 913 #interrupt-cells = <2>; 914 clocks = <&pioDE_clk>; 915 }; 916 917 pioE: gpio@fffffa00 { 918 compatible = "atmel,at91rm9200-gpio"; 919 reg = <0xfffffa00 0x200>; 920 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 921 #gpio-cells = <2>; 922 gpio-controller; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 clocks = <&pioDE_clk>; 926 }; 927 }; 928 929 dbgu: serial@ffffee00 { 930 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 931 reg = <0xffffee00 0x200>; 932 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&pinctrl_dbgu>; 935 clocks = <&mck>; 936 clock-names = "usart"; 937 status = "disabled"; 938 }; 939 940 usart0: serial@fff8c000 { 941 compatible = "atmel,at91sam9260-usart"; 942 reg = <0xfff8c000 0x200>; 943 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 944 atmel,use-dma-rx; 945 atmel,use-dma-tx; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&pinctrl_usart0>; 948 clocks = <&usart0_clk>; 949 clock-names = "usart"; 950 status = "disabled"; 951 }; 952 953 usart1: serial@fff90000 { 954 compatible = "atmel,at91sam9260-usart"; 955 reg = <0xfff90000 0x200>; 956 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 957 atmel,use-dma-rx; 958 atmel,use-dma-tx; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&pinctrl_usart1>; 961 clocks = <&usart1_clk>; 962 clock-names = "usart"; 963 status = "disabled"; 964 }; 965 966 usart2: serial@fff94000 { 967 compatible = "atmel,at91sam9260-usart"; 968 reg = <0xfff94000 0x200>; 969 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 970 atmel,use-dma-rx; 971 atmel,use-dma-tx; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&pinctrl_usart2>; 974 clocks = <&usart2_clk>; 975 clock-names = "usart"; 976 status = "disabled"; 977 }; 978 979 usart3: serial@fff98000 { 980 compatible = "atmel,at91sam9260-usart"; 981 reg = <0xfff98000 0x200>; 982 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; 983 atmel,use-dma-rx; 984 atmel,use-dma-tx; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&pinctrl_usart3>; 987 clocks = <&usart3_clk>; 988 clock-names = "usart"; 989 status = "disabled"; 990 }; 991 992 macb0: ethernet@fffbc000 { 993 compatible = "cdns,at91sam9260-macb", "cdns,macb"; 994 reg = <0xfffbc000 0x100>; 995 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&pinctrl_macb_rmii>; 998 clocks = <&macb0_clk>, <&macb0_clk>; 999 clock-names = "hclk", "pclk"; 1000 status = "disabled"; 1001 }; 1002 1003 trng@fffcc000 { 1004 compatible = "atmel,at91sam9g45-trng"; 1005 reg = <0xfffcc000 0x100>; 1006 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 1007 clocks = <&trng_clk>; 1008 }; 1009 1010 i2c0: i2c@fff84000 { 1011 compatible = "atmel,at91sam9g10-i2c"; 1012 reg = <0xfff84000 0x100>; 1013 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&pinctrl_i2c0>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 clocks = <&twi0_clk>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c1: i2c@fff88000 { 1023 compatible = "atmel,at91sam9g10-i2c"; 1024 reg = <0xfff88000 0x100>; 1025 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&pinctrl_i2c1>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 clocks = <&twi1_clk>; 1031 status = "disabled"; 1032 }; 1033 1034 ssc0: ssc@fff9c000 { 1035 compatible = "atmel,at91sam9g45-ssc"; 1036 reg = <0xfff9c000 0x4000>; 1037 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 1040 clocks = <&ssc0_clk>; 1041 clock-names = "pclk"; 1042 status = "disabled"; 1043 }; 1044 1045 ssc1: ssc@fffa0000 { 1046 compatible = "atmel,at91sam9g45-ssc"; 1047 reg = <0xfffa0000 0x4000>; 1048 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 1049 pinctrl-names = "default"; 1050 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 1051 clocks = <&ssc1_clk>; 1052 clock-names = "pclk"; 1053 status = "disabled"; 1054 }; 1055 1056 ac97: sound@fffac000 { 1057 compatible = "atmel,at91sam9263-ac97c"; 1058 reg = <0xfffac000 0x4000>; 1059 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&pinctrl_ac97>; 1062 clocks = <&ac97_clk>; 1063 clock-names = "ac97_clk"; 1064 status = "disabled"; 1065 }; 1066 1067 adc0: adc@fffb0000 { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 compatible = "atmel,at91sam9g45-adc"; 1071 reg = <0xfffb0000 0x100>; 1072 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 1073 clocks = <&adc_clk>, <&adc_op_clk>; 1074 clock-names = "adc_clk", "adc_op_clk"; 1075 atmel,adc-channels-used = <0xff>; 1076 atmel,adc-vref = <3300>; 1077 atmel,adc-startup-time = <40>; 1078 atmel,adc-res = <8 10>; 1079 atmel,adc-res-names = "lowres", "highres"; 1080 atmel,adc-use-res = "highres"; 1081 1082 trigger0 { 1083 trigger-name = "external-rising"; 1084 trigger-value = <0x1>; 1085 trigger-external; 1086 }; 1087 trigger1 { 1088 trigger-name = "external-falling"; 1089 trigger-value = <0x2>; 1090 trigger-external; 1091 }; 1092 1093 trigger2 { 1094 trigger-name = "external-any"; 1095 trigger-value = <0x3>; 1096 trigger-external; 1097 }; 1098 1099 trigger3 { 1100 trigger-name = "continuous"; 1101 trigger-value = <0x6>; 1102 }; 1103 }; 1104 1105 isi@fffb4000 { 1106 compatible = "atmel,at91sam9g45-isi"; 1107 reg = <0xfffb4000 0x4000>; 1108 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; 1109 clocks = <&isi_clk>; 1110 clock-names = "isi_clk"; 1111 status = "disabled"; 1112 port { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 }; 1116 }; 1117 1118 pwm0: pwm@fffb8000 { 1119 compatible = "atmel,at91sam9rl-pwm"; 1120 reg = <0xfffb8000 0x300>; 1121 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 1122 #pwm-cells = <3>; 1123 clocks = <&pwm_clk>; 1124 status = "disabled"; 1125 }; 1126 1127 mmc0: mmc@fff80000 { 1128 compatible = "atmel,hsmci"; 1129 reg = <0xfff80000 0x600>; 1130 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1131 pinctrl-names = "default"; 1132 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 1133 dma-names = "rxtx"; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 clocks = <&mci0_clk>; 1137 clock-names = "mci_clk"; 1138 status = "disabled"; 1139 }; 1140 1141 mmc1: mmc@fffd0000 { 1142 compatible = "atmel,hsmci"; 1143 reg = <0xfffd0000 0x600>; 1144 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; 1145 pinctrl-names = "default"; 1146 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; 1147 dma-names = "rxtx"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 clocks = <&mci1_clk>; 1151 clock-names = "mci_clk"; 1152 status = "disabled"; 1153 }; 1154 1155 watchdog@fffffd40 { 1156 compatible = "atmel,at91sam9260-wdt"; 1157 reg = <0xfffffd40 0x10>; 1158 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1159 clocks = <&clk32k>; 1160 atmel,watchdog-type = "hardware"; 1161 atmel,reset-type = "all"; 1162 atmel,dbg-halt; 1163 status = "disabled"; 1164 }; 1165 1166 spi0: spi@fffa4000 { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 compatible = "atmel,at91rm9200-spi"; 1170 reg = <0xfffa4000 0x200>; 1171 interrupts = <14 4 3>; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&pinctrl_spi0>; 1174 clocks = <&spi0_clk>; 1175 clock-names = "spi_clk"; 1176 status = "disabled"; 1177 }; 1178 1179 spi1: spi@fffa8000 { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 compatible = "atmel,at91rm9200-spi"; 1183 reg = <0xfffa8000 0x200>; 1184 interrupts = <15 4 3>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&pinctrl_spi1>; 1187 clocks = <&spi1_clk>; 1188 clock-names = "spi_clk"; 1189 status = "disabled"; 1190 }; 1191 1192 usb2: gadget@fff78000 { 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 compatible = "atmel,at91sam9g45-udc"; 1196 reg = <0x00600000 0x80000 1197 0xfff78000 0x400>; 1198 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 1199 clocks = <&udphs_clk>, <&utmi>; 1200 clock-names = "pclk", "hclk"; 1201 status = "disabled"; 1202 1203 ep@0 { 1204 reg = <0>; 1205 atmel,fifo-size = <64>; 1206 atmel,nb-banks = <1>; 1207 }; 1208 1209 ep@1 { 1210 reg = <1>; 1211 atmel,fifo-size = <1024>; 1212 atmel,nb-banks = <2>; 1213 atmel,can-dma; 1214 atmel,can-isoc; 1215 }; 1216 1217 ep@2 { 1218 reg = <2>; 1219 atmel,fifo-size = <1024>; 1220 atmel,nb-banks = <2>; 1221 atmel,can-dma; 1222 atmel,can-isoc; 1223 }; 1224 1225 ep@3 { 1226 reg = <3>; 1227 atmel,fifo-size = <1024>; 1228 atmel,nb-banks = <3>; 1229 atmel,can-dma; 1230 }; 1231 1232 ep@4 { 1233 reg = <4>; 1234 atmel,fifo-size = <1024>; 1235 atmel,nb-banks = <3>; 1236 atmel,can-dma; 1237 }; 1238 1239 ep@5 { 1240 reg = <5>; 1241 atmel,fifo-size = <1024>; 1242 atmel,nb-banks = <3>; 1243 atmel,can-dma; 1244 atmel,can-isoc; 1245 }; 1246 1247 ep@6 { 1248 reg = <6>; 1249 atmel,fifo-size = <1024>; 1250 atmel,nb-banks = <3>; 1251 atmel,can-dma; 1252 atmel,can-isoc; 1253 }; 1254 }; 1255 1256 sckc@fffffd50 { 1257 compatible = "atmel,at91sam9x5-sckc"; 1258 reg = <0xfffffd50 0x4>; 1259 1260 slow_osc: slow_osc { 1261 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1262 #clock-cells = <0>; 1263 atmel,startup-time-usec = <1200000>; 1264 clocks = <&slow_xtal>; 1265 }; 1266 1267 slow_rc_osc: slow_rc_osc { 1268 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1269 #clock-cells = <0>; 1270 atmel,startup-time-usec = <75>; 1271 clock-frequency = <32768>; 1272 clock-accuracy = <50000000>; 1273 }; 1274 1275 clk32k: slck { 1276 compatible = "atmel,at91sam9x5-clk-slow"; 1277 #clock-cells = <0>; 1278 clocks = <&slow_rc_osc &slow_osc>; 1279 }; 1280 }; 1281 1282 rtc@fffffd20 { 1283 compatible = "atmel,at91sam9260-rtt"; 1284 reg = <0xfffffd20 0x10>; 1285 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1286 clocks = <&clk32k>; 1287 status = "disabled"; 1288 }; 1289 1290 rtc@fffffdb0 { 1291 compatible = "atmel,at91rm9200-rtc"; 1292 reg = <0xfffffdb0 0x30>; 1293 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1294 clocks = <&clk32k>; 1295 status = "disabled"; 1296 }; 1297 1298 gpbr: syscon@fffffd60 { 1299 compatible = "atmel,at91sam9260-gpbr", "syscon"; 1300 reg = <0xfffffd60 0x10>; 1301 status = "disabled"; 1302 }; 1303 }; 1304 1305 fb0: fb@0x00500000 { 1306 compatible = "atmel,at91sam9g45-lcdc"; 1307 reg = <0x00500000 0x1000>; 1308 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&pinctrl_fb>; 1311 clocks = <&lcd_clk>, <&lcd_clk>; 1312 clock-names = "hclk", "lcdc_clk"; 1313 status = "disabled"; 1314 }; 1315 1316 usb0: ohci@00700000 { 1317 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1318 reg = <0x00700000 0x100000>; 1319 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1320 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1321 clock-names = "ohci_clk", "hclk", "uhpck"; 1322 status = "disabled"; 1323 }; 1324 1325 usb1: ehci@00800000 { 1326 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1327 reg = <0x00800000 0x100000>; 1328 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1329 clocks = <&utmi>, <&uhphs_clk>; 1330 clock-names = "usb_clk", "ehci_clk"; 1331 status = "disabled"; 1332 }; 1333 1334 ebi: ebi@10000000 { 1335 compatible = "atmel,at91sam9g45-ebi"; 1336 #address-cells = <2>; 1337 #size-cells = <1>; 1338 atmel,smc = <&smc>; 1339 atmel,matrix = <&matrix>; 1340 reg = <0x10000000 0x80000000>; 1341 ranges = <0x0 0x0 0x10000000 0x10000000 1342 0x1 0x0 0x20000000 0x10000000 1343 0x2 0x0 0x30000000 0x10000000 1344 0x3 0x0 0x40000000 0x10000000 1345 0x4 0x0 0x50000000 0x10000000 1346 0x5 0x0 0x60000000 0x10000000>; 1347 clocks = <&mck>; 1348 status = "disabled"; 1349 1350 nand_controller: nand-controller { 1351 compatible = "atmel,at91sam9g45-nand-controller"; 1352 #address-cells = <2>; 1353 #size-cells = <1>; 1354 ranges; 1355 status = "disabled"; 1356 }; 1357 }; 1358 }; 1359 1360 i2c-gpio-0 { 1361 compatible = "i2c-gpio"; 1362 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ 1363 &pioA 21 GPIO_ACTIVE_HIGH /* scl */ 1364 >; 1365 i2c-gpio,sda-open-drain; 1366 i2c-gpio,scl-open-drain; 1367 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372}; 1373