1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4#include "skeleton.dtsi" 5 6/ { 7 #address-cells = <2>; 8 #size-cells = <2>; 9 model = "Broadcom STB (bcm7445)"; 10 compatible = "brcm,bcm7445", "brcm,brcmstb"; 11 interrupt-parent = <&gic>; 12 13 chosen { 14 bootargs = "console=ttyS0,115200 earlyprintk"; 15 }; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 compatible = "brcm,brahma-b15"; 23 device_type = "cpu"; 24 enable-method = "brcm,brahma-b15"; 25 reg = <0>; 26 }; 27 28 cpu@1 { 29 compatible = "brcm,brahma-b15"; 30 device_type = "cpu"; 31 enable-method = "brcm,brahma-b15"; 32 reg = <1>; 33 }; 34 35 cpu@2 { 36 compatible = "brcm,brahma-b15"; 37 device_type = "cpu"; 38 enable-method = "brcm,brahma-b15"; 39 reg = <2>; 40 }; 41 42 cpu@3 { 43 compatible = "brcm,brahma-b15"; 44 device_type = "cpu"; 45 enable-method = "brcm,brahma-b15"; 46 reg = <3>; 47 }; 48 }; 49 50 gic: interrupt-controller@ffd00000 { 51 compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; 52 reg = <0x00 0xffd01000 0x00 0x1000>, 53 <0x00 0xffd02000 0x00 0x2000>, 54 <0x00 0xffd04000 0x00 0x2000>, 55 <0x00 0xffd06000 0x00 0x2000>; 56 interrupt-controller; 57 #interrupt-cells = <3>; 58 }; 59 60 timer { 61 compatible = "arm,armv7-timer"; 62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 63 <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 64 <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 66 }; 67 68 rdb { 69 #address-cells = <1>; 70 #size-cells = <1>; 71 compatible = "simple-bus"; 72 ranges = <0 0x00 0xf0000000 0x1000000>; 73 74 serial@40ab00 { 75 compatible = "ns16550a"; 76 reg = <0x40ab00 0x20>; 77 reg-shift = <2>; 78 reg-io-width = <4>; 79 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 80 clock-frequency = <81000000>; 81 }; 82 83 sun_top_ctrl: syscon@404000 { 84 compatible = "brcm,bcm7445-sun-top-ctrl", 85 "syscon"; 86 reg = <0x404000 0x51c>; 87 }; 88 89 hif_cpubiuctrl: syscon@3e2400 { 90 compatible = "brcm,bcm7445-hif-cpubiuctrl", 91 "syscon"; 92 reg = <0x3e2400 0x5b4>; 93 }; 94 95 hif_continuation: syscon@452000 { 96 compatible = "brcm,bcm7445-hif-continuation", 97 "syscon"; 98 reg = <0x452000 0x100>; 99 }; 100 101 irq0_intc: interrupt-controller@40a780 { 102 compatible = "brcm,bcm7120-l2-intc"; 103 interrupt-parent = <&gic>; 104 #interrupt-cells = <1>; 105 reg = <0x40a780 0x8>; 106 interrupt-controller; 107 interrupts = <GIC_SPI 0x45 0x0>, 108 <GIC_SPI 0x43 0x0>; 109 brcm,int-map-mask = <0x25c>, <0x7000000>; 110 brcm,int-fwd-mask = <0x70000>; 111 }; 112 113 irq0_aon_intc: interrupt-controller@417280 { 114 compatible = "brcm,bcm7120-l2-intc"; 115 reg = <0x417280 0x8>; 116 interrupt-parent = <&gic>; 117 #interrupt-cells = <1>; 118 interrupt-controller; 119 interrupts = <GIC_SPI 0x46 0x0>, 120 <GIC_SPI 0x44 0x0>, 121 <GIC_SPI 0x49 0x0>; 122 brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; 123 brcm,int-fwd-mask = <0x0>; 124 brcm,irq-can-wake; 125 }; 126 127 hif_intr2_intc: interrupt-controller@3e1000 { 128 compatible = "brcm,l2-intc"; 129 reg = <0x3e1000 0x30>; 130 interrupt-controller; 131 #interrupt-cells = <1>; 132 interrupts = <GIC_SPI 0x20 0x0>; 133 interrupt-parent = <&gic>; 134 interrupt-names = "hif"; 135 }; 136 137 aon_pm_l2_intc: interrupt-controller@410640 { 138 compatible = "brcm,l2-intc"; 139 reg = <0x410640 0x30>; 140 interrupt-controller; 141 #interrupt-cells = <1>; 142 interrupts = <GIC_SPI 0x40 0x0>; 143 interrupt-parent = <&gic>; 144 brcm,irq-can-wake; 145 }; 146 147 aon-ctrl@410000 { 148 compatible = "brcm,brcmstb-aon-ctrl"; 149 reg = <0x410000 0x200>, <0x410200 0x400>; 150 reg-names = "aon-ctrl", "aon-sram"; 151 }; 152 153 nand: nand@3e2800 { 154 status = "disabled"; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; 158 reg-names = "nand", "flash-dma"; 159 reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; 160 interrupt-parent = <&hif_intr2_intc>; 161 interrupts = <24>, <4>; 162 interrupt-names = "nand_ctlrdy", "flash_dma_done"; 163 }; 164 165 sata@45a000 { 166 compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; 167 reg-names = "ahci", "top-ctrl"; 168 reg = <0x45a000 0xa9c>, <0x458040 0x24>; 169 interrupts = <GIC_SPI 30 0>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 173 sata0: sata-port@0 { 174 reg = <0>; 175 phys = <&sata_phy0>; 176 }; 177 178 sata1: sata-port@1 { 179 reg = <1>; 180 phys = <&sata_phy1>; 181 }; 182 }; 183 184 sata_phy: sata-phy@458100 { 185 compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; 186 reg = <0x458100 0x1f00>; 187 reg-names = "phy"; 188 #address-cells = <0x1>; 189 #size-cells = <0x0>; 190 191 sata_phy0: sata-phy@0 { 192 reg = <0>; 193 #phy-cells = <0>; 194 }; 195 196 sata_phy1: sata-phy@1 { 197 reg = <1>; 198 #phy-cells = <0>; 199 }; 200 }; 201 202 upg_gio: gpio@40a700 { 203 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 204 reg = <0x40a700 0x80>; 205 #gpio-cells = <2>; 206 #interrupt-cells = <2>; 207 gpio-controller; 208 interrupt-controller; 209 interrupt-parent = <&irq0_intc>; 210 interrupts = <6>; 211 brcm,gpio-bank-widths = <32 32 32 24>; 212 }; 213 214 upg_gio_aon: gpio@4172c0 { 215 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 216 reg = <0x4172c0 0x40>; 217 #gpio-cells = <2>; 218 #interrupt-cells = <2>; 219 gpio-controller; 220 interrupt-controller; 221 interrupts-extended = <&irq0_aon_intc 0x6>, 222 <&aon_pm_l2_intc 0x5>; 223 wakeup-source; 224 brcm,gpio-bank-widths = <18 4>; 225 }; 226 227 }; 228 229 memory_controllers { 230 compatible = "simple-bus"; 231 ranges = <0x0 0x0 0xf1100000 0x200000>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 235 memc@0 { 236 compatible = "brcm,brcmstb-memc", "simple-bus"; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 ranges = <0x0 0x0 0x80000>; 240 241 memc-ddr@2000 { 242 compatible = "brcm,brcmstb-memc-ddr"; 243 reg = <0x2000 0x800>; 244 }; 245 246 ddr-phy@6000 { 247 compatible = "brcm,brcmstb-ddr-phy-v240.1"; 248 reg = <0x6000 0x21c>; 249 }; 250 251 shimphy@8000 { 252 compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; 253 reg = <0x8000 0xe4>; 254 }; 255 }; 256 257 memc@1 { 258 compatible = "brcm,brcmstb-memc", "simple-bus"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges = <0x0 0x80000 0x80000>; 262 263 memc-ddr@2000 { 264 compatible = "brcm,brcmstb-memc-ddr"; 265 reg = <0x2000 0x800>; 266 }; 267 268 ddr-phy@6000 { 269 compatible = "brcm,brcmstb-ddr-phy-v240.1"; 270 reg = <0x6000 0x21c>; 271 }; 272 273 shimphy@8000 { 274 compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; 275 reg = <0x8000 0xe4>; 276 }; 277 }; 278 279 memc@2 { 280 compatible = "brcm,brcmstb-memc", "simple-bus"; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 ranges = <0x0 0x100000 0x80000>; 284 285 memc-ddr@2000 { 286 compatible = "brcm,brcmstb-memc-ddr"; 287 reg = <0x2000 0x800>; 288 }; 289 290 ddr-phy@6000 { 291 compatible = "brcm,brcmstb-ddr-phy-v240.1"; 292 reg = <0x6000 0x21c>; 293 }; 294 295 shimphy@8000 { 296 compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; 297 reg = <0x8000 0xe4>; 298 }; 299 }; 300 }; 301 302 sram@ffe00000 { 303 compatible = "brcm,boot-sram", "mmio-sram"; 304 reg = <0x0 0xffe00000 0x0 0x10000>; 305 }; 306 307 smpboot { 308 compatible = "brcm,brcmstb-smpboot"; 309 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; 310 syscon-cont = <&hif_continuation>; 311 }; 312 313 reboot { 314 compatible = "brcm,brcmstb-reboot"; 315 syscon = <&sun_top_ctrl 0x304 0x308>; 316 }; 317}; 318