1/* 2 * Samsung's Exynos4412 SoC device tree source 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 8 * based board files can include this file and provide values for board specfic 9 * bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional 13 * nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18*/ 19 20#include "exynos4.dtsi" 21#include "exynos4412-pinctrl.dtsi" 22#include "exynos4-cpu-thermal.dtsi" 23 24/ { 25 compatible = "samsung,exynos4412", "samsung,exynos4"; 26 27 aliases { 28 pinctrl0 = &pinctrl_0; 29 pinctrl1 = &pinctrl_1; 30 pinctrl2 = &pinctrl_2; 31 pinctrl3 = &pinctrl_3; 32 fimc-lite0 = &fimc_lite_0; 33 fimc-lite1 = &fimc_lite_1; 34 mshc0 = &mshc_0; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu0: cpu@A00 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a9"; 44 reg = <0xA00>; 45 clocks = <&clock CLK_ARM_CLK>; 46 clock-names = "cpu"; 47 operating-points-v2 = <&cpu0_opp_table>; 48 #cooling-cells = <2>; /* min followed by max */ 49 }; 50 51 cpu@A01 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a9"; 54 reg = <0xA01>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 }; 57 58 cpu@A02 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a9"; 61 reg = <0xA02>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 }; 64 65 cpu@A03 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a9"; 68 reg = <0xA03>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 }; 71 }; 72 73 cpu0_opp_table: opp_table0 { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 opp-microvolt = <900000>; 80 clock-latency-ns = <200000>; 81 }; 82 opp-300000000 { 83 opp-hz = /bits/ 64 <300000000>; 84 opp-microvolt = <900000>; 85 clock-latency-ns = <200000>; 86 }; 87 opp-400000000 { 88 opp-hz = /bits/ 64 <400000000>; 89 opp-microvolt = <925000>; 90 clock-latency-ns = <200000>; 91 }; 92 opp-500000000 { 93 opp-hz = /bits/ 64 <500000000>; 94 opp-microvolt = <950000>; 95 clock-latency-ns = <200000>; 96 }; 97 opp-600000000 { 98 opp-hz = /bits/ 64 <600000000>; 99 opp-microvolt = <975000>; 100 clock-latency-ns = <200000>; 101 }; 102 opp-700000000 { 103 opp-hz = /bits/ 64 <700000000>; 104 opp-microvolt = <987500>; 105 clock-latency-ns = <200000>; 106 }; 107 opp-800000000 { 108 opp-hz = /bits/ 64 <800000000>; 109 opp-microvolt = <1000000>; 110 clock-latency-ns = <200000>; 111 opp-suspend; 112 }; 113 opp-900000000 { 114 opp-hz = /bits/ 64 <900000000>; 115 opp-microvolt = <1037500>; 116 clock-latency-ns = <200000>; 117 }; 118 opp-1000000000 { 119 opp-hz = /bits/ 64 <1000000000>; 120 opp-microvolt = <1087500>; 121 clock-latency-ns = <200000>; 122 }; 123 opp-1100000000 { 124 opp-hz = /bits/ 64 <1100000000>; 125 opp-microvolt = <1137500>; 126 clock-latency-ns = <200000>; 127 }; 128 opp-1200000000 { 129 opp-hz = /bits/ 64 <1200000000>; 130 opp-microvolt = <1187500>; 131 clock-latency-ns = <200000>; 132 }; 133 opp-1300000000 { 134 opp-hz = /bits/ 64 <1300000000>; 135 opp-microvolt = <1250000>; 136 clock-latency-ns = <200000>; 137 }; 138 opp-1400000000 { 139 opp-hz = /bits/ 64 <1400000000>; 140 opp-microvolt = <1287500>; 141 clock-latency-ns = <200000>; 142 }; 143 cpu0_opp_1500: opp-1500000000 { 144 opp-hz = /bits/ 64 <1500000000>; 145 opp-microvolt = <1350000>; 146 clock-latency-ns = <200000>; 147 turbo-mode; 148 }; 149 }; 150 151 sysram@02020000 { 152 compatible = "mmio-sram"; 153 reg = <0x02020000 0x40000>; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges = <0 0x02020000 0x40000>; 157 158 smp-sysram@0 { 159 compatible = "samsung,exynos4210-sysram"; 160 reg = <0x0 0x1000>; 161 }; 162 163 smp-sysram@2f000 { 164 compatible = "samsung,exynos4210-sysram-ns"; 165 reg = <0x2f000 0x1000>; 166 }; 167 }; 168 169 pd_isp: isp-power-domain@10023CA0 { 170 compatible = "samsung,exynos4210-pd"; 171 reg = <0x10023CA0 0x20>; 172 #power-domain-cells = <0>; 173 label = "ISP"; 174 }; 175 176 l2c: l2-cache-controller@10502000 { 177 compatible = "arm,pl310-cache"; 178 reg = <0x10502000 0x1000>; 179 cache-unified; 180 cache-level = <2>; 181 arm,tag-latency = <2 2 1>; 182 arm,data-latency = <3 2 1>; 183 arm,double-linefill = <1>; 184 arm,double-linefill-incr = <0>; 185 arm,double-linefill-wrap = <1>; 186 arm,prefetch-drop = <1>; 187 arm,prefetch-offset = <7>; 188 }; 189 190 clock: clock-controller@10030000 { 191 compatible = "samsung,exynos4412-clock"; 192 reg = <0x10030000 0x20000>; 193 #clock-cells = <1>; 194 }; 195 196 mct@10050000 { 197 compatible = "samsung,exynos4412-mct"; 198 reg = <0x10050000 0x800>; 199 interrupt-parent = <&mct_map>; 200 interrupts = <0>, <1>, <2>, <3>, <4>; 201 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 202 clock-names = "fin_pll", "mct"; 203 204 mct_map: mct-map { 205 #interrupt-cells = <1>; 206 #address-cells = <0>; 207 #size-cells = <0>; 208 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 209 <1 &combiner 12 5>, 210 <2 &combiner 12 6>, 211 <3 &combiner 12 7>, 212 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 }; 215 216 watchdog: watchdog@10060000 { 217 compatible = "samsung,exynos5250-wdt"; 218 reg = <0x10060000 0x100>; 219 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&clock CLK_WDT>; 221 clock-names = "watchdog"; 222 samsung,syscon-phandle = <&pmu_system_controller>; 223 }; 224 225 adc: adc@126C0000 { 226 compatible = "samsung,exynos-adc-v1"; 227 reg = <0x126C0000 0x100>; 228 interrupt-parent = <&combiner>; 229 interrupts = <10 3>; 230 clocks = <&clock CLK_TSADC>; 231 clock-names = "adc"; 232 #io-channel-cells = <1>; 233 io-channel-ranges; 234 samsung,syscon-phandle = <&pmu_system_controller>; 235 status = "disabled"; 236 }; 237 238 g2d: g2d@10800000 { 239 compatible = "samsung,exynos4212-g2d"; 240 reg = <0x10800000 0x1000>; 241 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 243 clock-names = "sclk_fimg2d", "fimg2d"; 244 iommus = <&sysmmu_g2d>; 245 }; 246 247 camera { 248 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 249 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 250 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 251 252 /* fimc_[0-3] are configured outside, under phandles */ 253 fimc_lite_0: fimc-lite@12390000 { 254 compatible = "samsung,exynos4212-fimc-lite"; 255 reg = <0x12390000 0x1000>; 256 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 257 power-domains = <&pd_isp>; 258 clocks = <&clock CLK_FIMC_LITE0>; 259 clock-names = "flite"; 260 iommus = <&sysmmu_fimc_lite0>; 261 status = "disabled"; 262 }; 263 264 fimc_lite_1: fimc-lite@123A0000 { 265 compatible = "samsung,exynos4212-fimc-lite"; 266 reg = <0x123A0000 0x1000>; 267 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 268 power-domains = <&pd_isp>; 269 clocks = <&clock CLK_FIMC_LITE1>; 270 clock-names = "flite"; 271 iommus = <&sysmmu_fimc_lite1>; 272 status = "disabled"; 273 }; 274 275 fimc_is: fimc-is@12000000 { 276 compatible = "samsung,exynos4212-fimc-is"; 277 reg = <0x12000000 0x260000>; 278 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 280 power-domains = <&pd_isp>; 281 clocks = <&clock CLK_FIMC_LITE0>, 282 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 283 <&clock CLK_PPMUISPMX>, 284 <&clock CLK_MOUT_MPLL_USER_T>, 285 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, 286 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, 287 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, 288 <&clock CLK_PWM_ISP>, 289 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, 290 <&clock CLK_DIV_MCUISP0>, 291 <&clock CLK_DIV_MCUISP1>, 292 <&clock CLK_UART_ISP_SCLK>, 293 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, 294 <&clock CLK_ACLK400_MCUISP>, 295 <&clock CLK_DIV_ACLK400_MCUISP>; 296 clock-names = "lite0", "lite1", "ppmuispx", 297 "ppmuispmx", "mpll", "isp", 298 "drc", "fd", "mcuisp", 299 "gicisp", "mcuctl_isp", "pwm_isp", 300 "ispdiv0", "ispdiv1", "mcuispdiv0", 301 "mcuispdiv1", "uart", "aclk200", 302 "div_aclk200", "aclk400mcuisp", 303 "div_aclk400mcuisp"; 304 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 305 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 306 iommu-names = "isp", "drc", "fd", "mcuctl"; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 ranges; 310 status = "disabled"; 311 312 pmu@10020000 { 313 reg = <0x10020000 0x3000>; 314 }; 315 316 i2c1_isp: i2c-isp@12140000 { 317 compatible = "samsung,exynos4212-i2c-isp"; 318 reg = <0x12140000 0x100>; 319 clocks = <&clock CLK_I2C1_ISP>; 320 clock-names = "i2c_isp"; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 }; 324 }; 325 }; 326 327 mshc_0: mmc@12550000 { 328 compatible = "samsung,exynos4412-dw-mshc"; 329 reg = <0x12550000 0x1000>; 330 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 fifo-depth = <0x80>; 334 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 335 clock-names = "biu", "ciu"; 336 status = "disabled"; 337 }; 338 339 sysmmu_g2d: sysmmu@10A40000{ 340 compatible = "samsung,exynos-sysmmu"; 341 reg = <0x10A40000 0x1000>; 342 interrupt-parent = <&combiner>; 343 interrupts = <4 7>; 344 clock-names = "sysmmu", "master"; 345 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 346 #iommu-cells = <0>; 347 }; 348 349 sysmmu_fimc_isp: sysmmu@12260000 { 350 compatible = "samsung,exynos-sysmmu"; 351 reg = <0x12260000 0x1000>; 352 interrupt-parent = <&combiner>; 353 interrupts = <16 2>; 354 power-domains = <&pd_isp>; 355 clock-names = "sysmmu"; 356 clocks = <&clock CLK_SMMU_ISP>; 357 #iommu-cells = <0>; 358 }; 359 360 sysmmu_fimc_drc: sysmmu@12270000 { 361 compatible = "samsung,exynos-sysmmu"; 362 reg = <0x12270000 0x1000>; 363 interrupt-parent = <&combiner>; 364 interrupts = <16 3>; 365 power-domains = <&pd_isp>; 366 clock-names = "sysmmu"; 367 clocks = <&clock CLK_SMMU_DRC>; 368 #iommu-cells = <0>; 369 }; 370 371 sysmmu_fimc_fd: sysmmu@122A0000 { 372 compatible = "samsung,exynos-sysmmu"; 373 reg = <0x122A0000 0x1000>; 374 interrupt-parent = <&combiner>; 375 interrupts = <16 4>; 376 power-domains = <&pd_isp>; 377 clock-names = "sysmmu"; 378 clocks = <&clock CLK_SMMU_FD>; 379 #iommu-cells = <0>; 380 }; 381 382 sysmmu_fimc_mcuctl: sysmmu@122B0000 { 383 compatible = "samsung,exynos-sysmmu"; 384 reg = <0x122B0000 0x1000>; 385 interrupt-parent = <&combiner>; 386 interrupts = <16 5>; 387 power-domains = <&pd_isp>; 388 clock-names = "sysmmu"; 389 clocks = <&clock CLK_SMMU_ISPCX>; 390 #iommu-cells = <0>; 391 }; 392 393 sysmmu_fimc_lite0: sysmmu@123B0000 { 394 compatible = "samsung,exynos-sysmmu"; 395 reg = <0x123B0000 0x1000>; 396 interrupt-parent = <&combiner>; 397 interrupts = <16 0>; 398 power-domains = <&pd_isp>; 399 clock-names = "sysmmu", "master"; 400 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; 401 #iommu-cells = <0>; 402 }; 403 404 sysmmu_fimc_lite1: sysmmu@123C0000 { 405 compatible = "samsung,exynos-sysmmu"; 406 reg = <0x123C0000 0x1000>; 407 interrupt-parent = <&combiner>; 408 interrupts = <16 1>; 409 power-domains = <&pd_isp>; 410 clock-names = "sysmmu", "master"; 411 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; 412 #iommu-cells = <0>; 413 }; 414 415 bus_dmc: bus_dmc { 416 compatible = "samsung,exynos-bus"; 417 clocks = <&clock CLK_DIV_DMC>; 418 clock-names = "bus"; 419 operating-points-v2 = <&bus_dmc_opp_table>; 420 status = "disabled"; 421 }; 422 423 bus_acp: bus_acp { 424 compatible = "samsung,exynos-bus"; 425 clocks = <&clock CLK_DIV_ACP>; 426 clock-names = "bus"; 427 operating-points-v2 = <&bus_acp_opp_table>; 428 status = "disabled"; 429 }; 430 431 bus_c2c: bus_c2c { 432 compatible = "samsung,exynos-bus"; 433 clocks = <&clock CLK_DIV_C2C>; 434 clock-names = "bus"; 435 operating-points-v2 = <&bus_dmc_opp_table>; 436 status = "disabled"; 437 }; 438 439 bus_dmc_opp_table: opp_table1 { 440 compatible = "operating-points-v2"; 441 opp-shared; 442 443 opp-100000000 { 444 opp-hz = /bits/ 64 <100000000>; 445 opp-microvolt = <900000>; 446 }; 447 opp-134000000 { 448 opp-hz = /bits/ 64 <134000000>; 449 opp-microvolt = <900000>; 450 }; 451 opp-160000000 { 452 opp-hz = /bits/ 64 <160000000>; 453 opp-microvolt = <900000>; 454 }; 455 opp-267000000 { 456 opp-hz = /bits/ 64 <267000000>; 457 opp-microvolt = <950000>; 458 }; 459 opp-400000000 { 460 opp-hz = /bits/ 64 <400000000>; 461 opp-microvolt = <1050000>; 462 }; 463 }; 464 465 bus_acp_opp_table: opp_table2 { 466 compatible = "operating-points-v2"; 467 opp-shared; 468 469 opp-100000000 { 470 opp-hz = /bits/ 64 <100000000>; 471 }; 472 opp-134000000 { 473 opp-hz = /bits/ 64 <134000000>; 474 }; 475 opp-160000000 { 476 opp-hz = /bits/ 64 <160000000>; 477 }; 478 opp-267000000 { 479 opp-hz = /bits/ 64 <267000000>; 480 }; 481 }; 482 483 bus_leftbus: bus_leftbus { 484 compatible = "samsung,exynos-bus"; 485 clocks = <&clock CLK_DIV_GDL>; 486 clock-names = "bus"; 487 operating-points-v2 = <&bus_leftbus_opp_table>; 488 status = "disabled"; 489 }; 490 491 bus_rightbus: bus_rightbus { 492 compatible = "samsung,exynos-bus"; 493 clocks = <&clock CLK_DIV_GDR>; 494 clock-names = "bus"; 495 operating-points-v2 = <&bus_leftbus_opp_table>; 496 status = "disabled"; 497 }; 498 499 bus_display: bus_display { 500 compatible = "samsung,exynos-bus"; 501 clocks = <&clock CLK_ACLK160>; 502 clock-names = "bus"; 503 operating-points-v2 = <&bus_display_opp_table>; 504 status = "disabled"; 505 }; 506 507 bus_fsys: bus_fsys { 508 compatible = "samsung,exynos-bus"; 509 clocks = <&clock CLK_ACLK133>; 510 clock-names = "bus"; 511 operating-points-v2 = <&bus_fsys_opp_table>; 512 status = "disabled"; 513 }; 514 515 bus_peri: bus_peri { 516 compatible = "samsung,exynos-bus"; 517 clocks = <&clock CLK_ACLK100>; 518 clock-names = "bus"; 519 operating-points-v2 = <&bus_peri_opp_table>; 520 status = "disabled"; 521 }; 522 523 bus_mfc: bus_mfc { 524 compatible = "samsung,exynos-bus"; 525 clocks = <&clock CLK_SCLK_MFC>; 526 clock-names = "bus"; 527 operating-points-v2 = <&bus_leftbus_opp_table>; 528 status = "disabled"; 529 }; 530 531 bus_leftbus_opp_table: opp_table3 { 532 compatible = "operating-points-v2"; 533 opp-shared; 534 535 opp-100000000 { 536 opp-hz = /bits/ 64 <100000000>; 537 opp-microvolt = <900000>; 538 }; 539 opp-134000000 { 540 opp-hz = /bits/ 64 <134000000>; 541 opp-microvolt = <925000>; 542 }; 543 opp-160000000 { 544 opp-hz = /bits/ 64 <160000000>; 545 opp-microvolt = <950000>; 546 }; 547 opp-200000000 { 548 opp-hz = /bits/ 64 <200000000>; 549 opp-microvolt = <1000000>; 550 }; 551 }; 552 553 bus_display_opp_table: opp_table4 { 554 compatible = "operating-points-v2"; 555 opp-shared; 556 557 opp-160000000 { 558 opp-hz = /bits/ 64 <160000000>; 559 }; 560 opp-200000000 { 561 opp-hz = /bits/ 64 <200000000>; 562 }; 563 }; 564 565 bus_fsys_opp_table: opp_table5 { 566 compatible = "operating-points-v2"; 567 opp-shared; 568 569 opp-100000000 { 570 opp-hz = /bits/ 64 <100000000>; 571 }; 572 opp-134000000 { 573 opp-hz = /bits/ 64 <134000000>; 574 }; 575 }; 576 577 bus_peri_opp_table: opp_table6 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 opp-50000000 { 582 opp-hz = /bits/ 64 <50000000>; 583 }; 584 opp-100000000 { 585 opp-hz = /bits/ 64 <100000000>; 586 }; 587 }; 588 589 pmu { 590 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 591 }; 592}; 593 594&combiner { 595 samsung,combiner-nr = <20>; 596 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 616}; 617 618&exynos_usbphy { 619 compatible = "samsung,exynos4x12-usb2-phy"; 620 samsung,sysreg-phandle = <&sys_reg>; 621}; 622 623&fimc_0 { 624 compatible = "samsung,exynos4212-fimc"; 625 samsung,pix-limits = <4224 8192 1920 4224>; 626 samsung,mainscaler-ext; 627 samsung,isp-wb; 628 samsung,cam-if; 629}; 630 631&fimc_1 { 632 compatible = "samsung,exynos4212-fimc"; 633 samsung,pix-limits = <4224 8192 1920 4224>; 634 samsung,mainscaler-ext; 635 samsung,isp-wb; 636 samsung,cam-if; 637}; 638 639&fimc_2 { 640 compatible = "samsung,exynos4212-fimc"; 641 samsung,pix-limits = <4224 8192 1920 4224>; 642 samsung,mainscaler-ext; 643 samsung,isp-wb; 644 samsung,lcd-wb; 645 samsung,cam-if; 646}; 647 648&fimc_3 { 649 compatible = "samsung,exynos4212-fimc"; 650 samsung,pix-limits = <1920 8192 1366 1920>; 651 samsung,rotators = <0>; 652 samsung,mainscaler-ext; 653 samsung,isp-wb; 654 samsung,lcd-wb; 655}; 656 657&gic { 658 cpu-offset = <0x4000>; 659}; 660 661&hdmi { 662 compatible = "samsung,exynos4212-hdmi"; 663}; 664 665&jpeg_codec { 666 compatible = "samsung,exynos4212-jpeg"; 667}; 668 669&rotator { 670 compatible = "samsung,exynos4212-rotator"; 671}; 672 673&mixer { 674 compatible = "samsung,exynos4212-mixer"; 675 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 676 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 677 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 678}; 679 680&pinctrl_0 { 681 compatible = "samsung,exynos4x12-pinctrl"; 682 reg = <0x11400000 0x1000>; 683 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 684}; 685 686&pinctrl_1 { 687 compatible = "samsung,exynos4x12-pinctrl"; 688 reg = <0x11000000 0x1000>; 689 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 690 691 wakup_eint: wakeup-interrupt-controller { 692 compatible = "samsung,exynos4210-wakeup-eint"; 693 interrupt-parent = <&gic>; 694 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 695 }; 696}; 697 698&pinctrl_2 { 699 compatible = "samsung,exynos4x12-pinctrl"; 700 reg = <0x03860000 0x1000>; 701 interrupt-parent = <&combiner>; 702 interrupts = <10 0>; 703}; 704 705&pinctrl_3 { 706 compatible = "samsung,exynos4x12-pinctrl"; 707 reg = <0x106E0000 0x1000>; 708 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 709}; 710 711&pmu_system_controller { 712 compatible = "samsung,exynos4412-pmu", "syscon"; 713 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 714 "clkout4", "clkout8", "clkout9"; 715 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 716 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 717 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 718 #clock-cells = <1>; 719}; 720 721&tmu { 722 compatible = "samsung,exynos4412-tmu"; 723 interrupt-parent = <&combiner>; 724 interrupts = <2 4>; 725 reg = <0x100C0000 0x100>; 726 clocks = <&clock 383>; 727 clock-names = "tmu_apbif"; 728 status = "disabled"; 729}; 730