1/* 2 * SAMSUNG EXYNOS5250 SoC device tree source 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. 8 * EXYNOS5250 based board files can include this file and provide 9 * values for board specfic bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, 13 * additional nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18*/ 19 20#include <dt-bindings/clock/exynos5250.h> 21#include "exynos5.dtsi" 22#include "exynos4-cpu-thermal.dtsi" 23#include <dt-bindings/clock/exynos-audss-clk.h> 24 25/ { 26 compatible = "samsung,exynos5250", "samsung,exynos5"; 27 28 aliases { 29 spi0 = &spi_0; 30 spi1 = &spi_1; 31 spi2 = &spi_2; 32 gsc0 = &gsc_0; 33 gsc1 = &gsc_1; 34 gsc2 = &gsc_2; 35 gsc3 = &gsc_3; 36 mshc0 = &mmc_0; 37 mshc1 = &mmc_1; 38 mshc2 = &mmc_2; 39 mshc3 = &mmc_3; 40 i2c4 = &i2c_4; 41 i2c5 = &i2c_5; 42 i2c6 = &i2c_6; 43 i2c7 = &i2c_7; 44 i2c8 = &i2c_8; 45 i2c9 = &i2c_9; 46 pinctrl0 = &pinctrl_0; 47 pinctrl1 = &pinctrl_1; 48 pinctrl2 = &pinctrl_2; 49 pinctrl3 = &pinctrl_3; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 cpu0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a15"; 59 reg = <0>; 60 clocks = <&clock CLK_ARM_CLK>; 61 clock-names = "cpu"; 62 operating-points-v2 = <&cpu0_opp_table>; 63 #cooling-cells = <2>; /* min followed by max */ 64 }; 65 cpu@1 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a15"; 68 reg = <1>; 69 clocks = <&clock CLK_ARM_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu0_opp_table>; 72 #cooling-cells = <2>; /* min followed by max */ 73 }; 74 }; 75 76 cpu0_opp_table: opp_table0 { 77 compatible = "operating-points-v2"; 78 opp-shared; 79 80 opp-200000000 { 81 opp-hz = /bits/ 64 <200000000>; 82 opp-microvolt = <925000>; 83 clock-latency-ns = <140000>; 84 }; 85 opp-300000000 { 86 opp-hz = /bits/ 64 <300000000>; 87 opp-microvolt = <937500>; 88 clock-latency-ns = <140000>; 89 }; 90 opp-400000000 { 91 opp-hz = /bits/ 64 <400000000>; 92 opp-microvolt = <950000>; 93 clock-latency-ns = <140000>; 94 }; 95 opp-500000000 { 96 opp-hz = /bits/ 64 <500000000>; 97 opp-microvolt = <975000>; 98 clock-latency-ns = <140000>; 99 }; 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <1000000>; 103 clock-latency-ns = <140000>; 104 }; 105 opp-700000000 { 106 opp-hz = /bits/ 64 <700000000>; 107 opp-microvolt = <1012500>; 108 clock-latency-ns = <140000>; 109 }; 110 opp-800000000 { 111 opp-hz = /bits/ 64 <800000000>; 112 opp-microvolt = <1025000>; 113 clock-latency-ns = <140000>; 114 }; 115 opp-900000000 { 116 opp-hz = /bits/ 64 <900000000>; 117 opp-microvolt = <1050000>; 118 clock-latency-ns = <140000>; 119 }; 120 opp-1000000000 { 121 opp-hz = /bits/ 64 <1000000000>; 122 opp-microvolt = <1075000>; 123 clock-latency-ns = <140000>; 124 opp-suspend; 125 }; 126 opp-1100000000 { 127 opp-hz = /bits/ 64 <1100000000>; 128 opp-microvolt = <1100000>; 129 clock-latency-ns = <140000>; 130 }; 131 opp-1200000000 { 132 opp-hz = /bits/ 64 <1200000000>; 133 opp-microvolt = <1125000>; 134 clock-latency-ns = <140000>; 135 }; 136 opp-1300000000 { 137 opp-hz = /bits/ 64 <1300000000>; 138 opp-microvolt = <1150000>; 139 clock-latency-ns = <140000>; 140 }; 141 opp-1400000000 { 142 opp-hz = /bits/ 64 <1400000000>; 143 opp-microvolt = <1200000>; 144 clock-latency-ns = <140000>; 145 }; 146 opp-1500000000 { 147 opp-hz = /bits/ 64 <1500000000>; 148 opp-microvolt = <1225000>; 149 clock-latency-ns = <140000>; 150 }; 151 opp-1600000000 { 152 opp-hz = /bits/ 64 <1600000000>; 153 opp-microvolt = <1250000>; 154 clock-latency-ns = <140000>; 155 }; 156 opp-1700000000 { 157 opp-hz = /bits/ 64 <1700000000>; 158 opp-microvolt = <1300000>; 159 clock-latency-ns = <140000>; 160 }; 161 }; 162 163 soc: soc { 164 sysram@02020000 { 165 compatible = "mmio-sram"; 166 reg = <0x02020000 0x30000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges = <0 0x02020000 0x30000>; 170 171 smp-sysram@0 { 172 compatible = "samsung,exynos4210-sysram"; 173 reg = <0x0 0x1000>; 174 }; 175 176 smp-sysram@2f000 { 177 compatible = "samsung,exynos4210-sysram-ns"; 178 reg = <0x2f000 0x1000>; 179 }; 180 }; 181 182 pd_gsc: gsc-power-domain@10044000 { 183 compatible = "samsung,exynos4210-pd"; 184 reg = <0x10044000 0x20>; 185 #power-domain-cells = <0>; 186 label = "GSC"; 187 }; 188 189 pd_mfc: mfc-power-domain@10044040 { 190 compatible = "samsung,exynos4210-pd"; 191 reg = <0x10044040 0x20>; 192 #power-domain-cells = <0>; 193 label = "MFC"; 194 }; 195 196 pd_disp1: disp1-power-domain@100440A0 { 197 compatible = "samsung,exynos4210-pd"; 198 reg = <0x100440A0 0x20>; 199 #power-domain-cells = <0>; 200 label = "DISP1"; 201 clocks = <&clock CLK_FIN_PLL>, 202 <&clock CLK_MOUT_ACLK200_DISP1_SUB>, 203 <&clock CLK_MOUT_ACLK300_DISP1_SUB>; 204 clock-names = "oscclk", "clk0", "clk1"; 205 }; 206 207 clock: clock-controller@10010000 { 208 compatible = "samsung,exynos5250-clock"; 209 reg = <0x10010000 0x30000>; 210 #clock-cells = <1>; 211 }; 212 213 clock_audss: audss-clock-controller@3810000 { 214 compatible = "samsung,exynos5250-audss-clock"; 215 reg = <0x03810000 0x0C>; 216 #clock-cells = <1>; 217 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 218 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 219 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 220 }; 221 222 timer { 223 compatible = "arm,armv7-timer"; 224 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 225 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 226 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 227 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 228 /* 229 * Unfortunately we need this since some versions 230 * of U-Boot on Exynos don't set the CNTFRQ register, 231 * so we need the value from DT. 232 */ 233 clock-frequency = <24000000>; 234 }; 235 236 mct@101C0000 { 237 compatible = "samsung,exynos4210-mct"; 238 reg = <0x101C0000 0x800>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupt-parent = <&mct_map>; 242 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 243 <4 0>, <5 0>; 244 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 245 clock-names = "fin_pll", "mct"; 246 247 mct_map: mct-map { 248 #interrupt-cells = <2>; 249 #address-cells = <0>; 250 #size-cells = <0>; 251 interrupt-map = <0x0 0 &combiner 23 3>, 252 <0x1 0 &combiner 23 4>, 253 <0x2 0 &combiner 25 2>, 254 <0x3 0 &combiner 25 3>, 255 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, 256 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; 257 }; 258 }; 259 260 pmu { 261 compatible = "arm,cortex-a15-pmu"; 262 interrupt-parent = <&combiner>; 263 interrupts = <1 2>, <22 4>; 264 }; 265 266 pinctrl_0: pinctrl@11400000 { 267 compatible = "samsung,exynos5250-pinctrl"; 268 reg = <0x11400000 0x1000>; 269 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 270 271 wakup_eint: wakeup-interrupt-controller { 272 compatible = "samsung,exynos4210-wakeup-eint"; 273 interrupt-parent = <&gic>; 274 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 275 }; 276 }; 277 278 pinctrl_1: pinctrl@13400000 { 279 compatible = "samsung,exynos5250-pinctrl"; 280 reg = <0x13400000 0x1000>; 281 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 282 }; 283 284 pinctrl_2: pinctrl@10d10000 { 285 compatible = "samsung,exynos5250-pinctrl"; 286 reg = <0x10d10000 0x1000>; 287 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 pinctrl_3: pinctrl@03860000 { 291 compatible = "samsung,exynos5250-pinctrl"; 292 reg = <0x03860000 0x1000>; 293 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 pmu_system_controller: system-controller@10040000 { 297 compatible = "samsung,exynos5250-pmu", "syscon"; 298 reg = <0x10040000 0x5000>; 299 clock-names = "clkout16"; 300 clocks = <&clock CLK_FIN_PLL>; 301 #clock-cells = <1>; 302 interrupt-controller; 303 #interrupt-cells = <3>; 304 interrupt-parent = <&gic>; 305 }; 306 307 watchdog@101D0000 { 308 compatible = "samsung,exynos5250-wdt"; 309 reg = <0x101D0000 0x100>; 310 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clock CLK_WDT>; 312 clock-names = "watchdog"; 313 samsung,syscon-phandle = <&pmu_system_controller>; 314 }; 315 316 g2d@10850000 { 317 compatible = "samsung,exynos5250-g2d"; 318 reg = <0x10850000 0x1000>; 319 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&clock CLK_G2D>; 321 clock-names = "fimg2d"; 322 iommus = <&sysmmu_g2d>; 323 }; 324 325 mfc: codec@11000000 { 326 compatible = "samsung,mfc-v6"; 327 reg = <0x11000000 0x10000>; 328 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 329 power-domains = <&pd_mfc>; 330 clocks = <&clock CLK_MFC>; 331 clock-names = "mfc"; 332 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 333 iommu-names = "left", "right"; 334 }; 335 336 rotator: rotator@11C00000 { 337 compatible = "samsung,exynos5250-rotator"; 338 reg = <0x11C00000 0x64>; 339 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clock CLK_ROTATOR>; 341 clock-names = "rotator"; 342 iommus = <&sysmmu_rotator>; 343 }; 344 345 tmu: tmu@10060000 { 346 compatible = "samsung,exynos5250-tmu"; 347 reg = <0x10060000 0x100>; 348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clock CLK_TMU>; 350 clock-names = "tmu_apbif"; 351 #include "exynos4412-tmu-sensor-conf.dtsi" 352 }; 353 354 sata: sata@122F0000 { 355 compatible = "snps,dwc-ahci"; 356 samsung,sata-freq = <66>; 357 reg = <0x122F0000 0x1ff>; 358 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 360 clock-names = "sata", "sclk_sata"; 361 phys = <&sata_phy>; 362 phy-names = "sata-phy"; 363 status = "disabled"; 364 }; 365 366 sata_phy: sata-phy@12170000 { 367 compatible = "samsung,exynos5250-sata-phy"; 368 reg = <0x12170000 0x1ff>; 369 clocks = <&clock CLK_SATA_PHYCTRL>; 370 clock-names = "sata_phyctrl"; 371 #phy-cells = <0>; 372 samsung,syscon-phandle = <&pmu_system_controller>; 373 status = "disabled"; 374 }; 375 376 /* i2c_0-3 are defined in exynos5.dtsi */ 377 i2c_4: i2c@12CA0000 { 378 compatible = "samsung,s3c2440-i2c"; 379 reg = <0x12CA0000 0x100>; 380 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&clock CLK_I2C4>; 384 clock-names = "i2c"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&i2c4_bus>; 387 status = "disabled"; 388 }; 389 390 i2c_5: i2c@12CB0000 { 391 compatible = "samsung,s3c2440-i2c"; 392 reg = <0x12CB0000 0x100>; 393 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&clock CLK_I2C5>; 397 clock-names = "i2c"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&i2c5_bus>; 400 status = "disabled"; 401 }; 402 403 i2c_6: i2c@12CC0000 { 404 compatible = "samsung,s3c2440-i2c"; 405 reg = <0x12CC0000 0x100>; 406 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 clocks = <&clock CLK_I2C6>; 410 clock-names = "i2c"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&i2c6_bus>; 413 status = "disabled"; 414 }; 415 416 i2c_7: i2c@12CD0000 { 417 compatible = "samsung,s3c2440-i2c"; 418 reg = <0x12CD0000 0x100>; 419 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 clocks = <&clock CLK_I2C7>; 423 clock-names = "i2c"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c7_bus>; 426 status = "disabled"; 427 }; 428 429 i2c_8: i2c@12CE0000 { 430 compatible = "samsung,s3c2440-hdmiphy-i2c"; 431 reg = <0x12CE0000 0x1000>; 432 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&clock CLK_I2C_HDMI>; 436 clock-names = "i2c"; 437 status = "disabled"; 438 }; 439 440 i2c_9: i2c@121D0000 { 441 compatible = "samsung,exynos5-sata-phy-i2c"; 442 reg = <0x121D0000 0x100>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&clock CLK_SATA_PHYI2C>; 446 clock-names = "i2c"; 447 status = "disabled"; 448 }; 449 450 spi_0: spi@12d20000 { 451 compatible = "samsung,exynos4210-spi"; 452 status = "disabled"; 453 reg = <0x12d20000 0x100>; 454 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 455 dmas = <&pdma0 5 456 &pdma0 4>; 457 dma-names = "tx", "rx"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 461 clock-names = "spi", "spi_busclk0"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&spi0_bus>; 464 }; 465 466 spi_1: spi@12d30000 { 467 compatible = "samsung,exynos4210-spi"; 468 status = "disabled"; 469 reg = <0x12d30000 0x100>; 470 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 471 dmas = <&pdma1 5 472 &pdma1 4>; 473 dma-names = "tx", "rx"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 477 clock-names = "spi", "spi_busclk0"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&spi1_bus>; 480 }; 481 482 spi_2: spi@12d40000 { 483 compatible = "samsung,exynos4210-spi"; 484 status = "disabled"; 485 reg = <0x12d40000 0x100>; 486 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 487 dmas = <&pdma0 7 488 &pdma0 6>; 489 dma-names = "tx", "rx"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 493 clock-names = "spi", "spi_busclk0"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&spi2_bus>; 496 }; 497 498 mmc_0: mmc@12200000 { 499 compatible = "samsung,exynos5250-dw-mshc"; 500 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0x12200000 0x1000>; 504 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 505 clock-names = "biu", "ciu"; 506 fifo-depth = <0x80>; 507 status = "disabled"; 508 }; 509 510 mmc_1: mmc@12210000 { 511 compatible = "samsung,exynos5250-dw-mshc"; 512 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0x12210000 0x1000>; 516 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 517 clock-names = "biu", "ciu"; 518 fifo-depth = <0x80>; 519 status = "disabled"; 520 }; 521 522 mmc_2: mmc@12220000 { 523 compatible = "samsung,exynos5250-dw-mshc"; 524 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 reg = <0x12220000 0x1000>; 528 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 529 clock-names = "biu", "ciu"; 530 fifo-depth = <0x80>; 531 status = "disabled"; 532 }; 533 534 mmc_3: mmc@12230000 { 535 compatible = "samsung,exynos5250-dw-mshc"; 536 reg = <0x12230000 0x1000>; 537 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 541 clock-names = "biu", "ciu"; 542 fifo-depth = <0x80>; 543 status = "disabled"; 544 }; 545 546 i2s0: i2s@03830000 { 547 compatible = "samsung,s5pv210-i2s"; 548 status = "disabled"; 549 reg = <0x03830000 0x100>; 550 dmas = <&pdma0 10 551 &pdma0 9 552 &pdma0 8>; 553 dma-names = "tx", "rx", "tx-sec"; 554 clocks = <&clock_audss EXYNOS_I2S_BUS>, 555 <&clock_audss EXYNOS_I2S_BUS>, 556 <&clock_audss EXYNOS_SCLK_I2S>; 557 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 558 samsung,idma-addr = <0x03000000>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2s0_bus>; 561 }; 562 563 i2s1: i2s@12D60000 { 564 compatible = "samsung,s3c6410-i2s"; 565 status = "disabled"; 566 reg = <0x12D60000 0x100>; 567 dmas = <&pdma1 12 568 &pdma1 11>; 569 dma-names = "tx", "rx"; 570 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 571 clock-names = "iis", "i2s_opclk0"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2s1_bus>; 574 }; 575 576 i2s2: i2s@12D70000 { 577 compatible = "samsung,s3c6410-i2s"; 578 status = "disabled"; 579 reg = <0x12D70000 0x100>; 580 dmas = <&pdma0 12 581 &pdma0 11>; 582 dma-names = "tx", "rx"; 583 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 584 clock-names = "iis", "i2s_opclk0"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2s2_bus>; 587 }; 588 589 usb_dwc3 { 590 compatible = "samsung,exynos5250-dwusb3"; 591 clocks = <&clock CLK_USB3>; 592 clock-names = "usbdrd30"; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges; 596 597 usbdrd_dwc3: dwc3@12000000 { 598 compatible = "synopsys,dwc3"; 599 reg = <0x12000000 0x10000>; 600 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 601 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 602 phy-names = "usb2-phy", "usb3-phy"; 603 }; 604 }; 605 606 usbdrd_phy: phy@12100000 { 607 compatible = "samsung,exynos5250-usbdrd-phy"; 608 reg = <0x12100000 0x100>; 609 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 610 clock-names = "phy", "ref"; 611 samsung,pmu-syscon = <&pmu_system_controller>; 612 #phy-cells = <1>; 613 }; 614 615 ehci: usb@12110000 { 616 compatible = "samsung,exynos4210-ehci"; 617 reg = <0x12110000 0x100>; 618 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 619 620 clocks = <&clock CLK_USB2>; 621 clock-names = "usbhost"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 port@0 { 625 reg = <0>; 626 phys = <&usb2_phy_gen 1>; 627 }; 628 }; 629 630 ohci: usb@12120000 { 631 compatible = "samsung,exynos4210-ohci"; 632 reg = <0x12120000 0x100>; 633 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 634 635 clocks = <&clock CLK_USB2>; 636 clock-names = "usbhost"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 port@0 { 640 reg = <0>; 641 phys = <&usb2_phy_gen 1>; 642 }; 643 }; 644 645 usb2_phy_gen: phy@12130000 { 646 compatible = "samsung,exynos5250-usb2-phy"; 647 reg = <0x12130000 0x100>; 648 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 649 clock-names = "phy", "ref"; 650 #phy-cells = <1>; 651 samsung,sysreg-phandle = <&sysreg_system_controller>; 652 samsung,pmureg-phandle = <&pmu_system_controller>; 653 }; 654 655 amba { 656 #address-cells = <1>; 657 #size-cells = <1>; 658 compatible = "simple-bus"; 659 interrupt-parent = <&gic>; 660 ranges; 661 662 pdma0: pdma@121A0000 { 663 compatible = "arm,pl330", "arm,primecell"; 664 reg = <0x121A0000 0x1000>; 665 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clock CLK_PDMA0>; 667 clock-names = "apb_pclk"; 668 #dma-cells = <1>; 669 #dma-channels = <8>; 670 #dma-requests = <32>; 671 }; 672 673 pdma1: pdma@121B0000 { 674 compatible = "arm,pl330", "arm,primecell"; 675 reg = <0x121B0000 0x1000>; 676 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clock CLK_PDMA1>; 678 clock-names = "apb_pclk"; 679 #dma-cells = <1>; 680 #dma-channels = <8>; 681 #dma-requests = <32>; 682 }; 683 684 mdma0: mdma@10800000 { 685 compatible = "arm,pl330", "arm,primecell"; 686 reg = <0x10800000 0x1000>; 687 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&clock CLK_MDMA0>; 689 clock-names = "apb_pclk"; 690 #dma-cells = <1>; 691 #dma-channels = <8>; 692 #dma-requests = <1>; 693 }; 694 695 mdma1: mdma@11C10000 { 696 compatible = "arm,pl330", "arm,primecell"; 697 reg = <0x11C10000 0x1000>; 698 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&clock CLK_MDMA1>; 700 clock-names = "apb_pclk"; 701 #dma-cells = <1>; 702 #dma-channels = <8>; 703 #dma-requests = <1>; 704 }; 705 }; 706 707 gsc_0: gsc@13e00000 { 708 compatible = "samsung,exynos5-gsc"; 709 reg = <0x13e00000 0x1000>; 710 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 711 power-domains = <&pd_gsc>; 712 clocks = <&clock CLK_GSCL0>; 713 clock-names = "gscl"; 714 iommus = <&sysmmu_gsc0>; 715 }; 716 717 gsc_1: gsc@13e10000 { 718 compatible = "samsung,exynos5-gsc"; 719 reg = <0x13e10000 0x1000>; 720 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 721 power-domains = <&pd_gsc>; 722 clocks = <&clock CLK_GSCL1>; 723 clock-names = "gscl"; 724 iommus = <&sysmmu_gsc1>; 725 }; 726 727 gsc_2: gsc@13e20000 { 728 compatible = "samsung,exynos5-gsc"; 729 reg = <0x13e20000 0x1000>; 730 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 731 power-domains = <&pd_gsc>; 732 clocks = <&clock CLK_GSCL2>; 733 clock-names = "gscl"; 734 iommus = <&sysmmu_gsc2>; 735 }; 736 737 gsc_3: gsc@13e30000 { 738 compatible = "samsung,exynos5-gsc"; 739 reg = <0x13e30000 0x1000>; 740 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 741 power-domains = <&pd_gsc>; 742 clocks = <&clock CLK_GSCL3>; 743 clock-names = "gscl"; 744 iommus = <&sysmmu_gsc3>; 745 }; 746 747 hdmi: hdmi@14530000 { 748 compatible = "samsung,exynos4212-hdmi"; 749 reg = <0x14530000 0x70000>; 750 power-domains = <&pd_disp1>; 751 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 753 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 754 <&clock CLK_MOUT_HDMI>; 755 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 756 "sclk_hdmiphy", "mout_hdmi"; 757 samsung,syscon-phandle = <&pmu_system_controller>; 758 }; 759 760 hdmicec: cec@101B0000 { 761 compatible = "samsung,s5p-cec"; 762 reg = <0x101B0000 0x200>; 763 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&clock CLK_HDMI_CEC>; 765 clock-names = "hdmicec"; 766 samsung,syscon-phandle = <&pmu_system_controller>; 767 hdmi-phandle = <&hdmi>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&hdmi_cec>; 770 status = "disabled"; 771 }; 772 773 mixer@14450000 { 774 compatible = "samsung,exynos5250-mixer"; 775 reg = <0x14450000 0x10000>; 776 power-domains = <&pd_disp1>; 777 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 779 <&clock CLK_SCLK_HDMI>; 780 clock-names = "mixer", "hdmi", "sclk_hdmi"; 781 iommus = <&sysmmu_tv>; 782 }; 783 784 dp_phy: video-phy { 785 compatible = "samsung,exynos5250-dp-video-phy"; 786 samsung,pmu-syscon = <&pmu_system_controller>; 787 #phy-cells = <0>; 788 }; 789 790 adc: adc@12D10000 { 791 compatible = "samsung,exynos-adc-v1"; 792 reg = <0x12D10000 0x100>; 793 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&clock CLK_ADC>; 795 clock-names = "adc"; 796 #io-channel-cells = <1>; 797 io-channel-ranges; 798 samsung,syscon-phandle = <&pmu_system_controller>; 799 status = "disabled"; 800 }; 801 802 sss@10830000 { 803 compatible = "samsung,exynos4210-secss"; 804 reg = <0x10830000 0x300>; 805 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&clock CLK_SSS>; 807 clock-names = "secss"; 808 }; 809 810 sysmmu_g2d: sysmmu@10A60000 { 811 compatible = "samsung,exynos-sysmmu"; 812 reg = <0x10A60000 0x1000>; 813 interrupt-parent = <&combiner>; 814 interrupts = <24 5>; 815 clock-names = "sysmmu", "master"; 816 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 817 #iommu-cells = <0>; 818 }; 819 820 sysmmu_mfc_r: sysmmu@11200000 { 821 compatible = "samsung,exynos-sysmmu"; 822 reg = <0x11200000 0x1000>; 823 interrupt-parent = <&combiner>; 824 interrupts = <6 2>; 825 power-domains = <&pd_mfc>; 826 clock-names = "sysmmu", "master"; 827 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 828 #iommu-cells = <0>; 829 }; 830 831 sysmmu_mfc_l: sysmmu@11210000 { 832 compatible = "samsung,exynos-sysmmu"; 833 reg = <0x11210000 0x1000>; 834 interrupt-parent = <&combiner>; 835 interrupts = <8 5>; 836 power-domains = <&pd_mfc>; 837 clock-names = "sysmmu", "master"; 838 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 839 #iommu-cells = <0>; 840 }; 841 842 sysmmu_rotator: sysmmu@11D40000 { 843 compatible = "samsung,exynos-sysmmu"; 844 reg = <0x11D40000 0x1000>; 845 interrupt-parent = <&combiner>; 846 interrupts = <4 0>; 847 clock-names = "sysmmu", "master"; 848 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 849 #iommu-cells = <0>; 850 }; 851 852 sysmmu_jpeg: sysmmu@11F20000 { 853 compatible = "samsung,exynos-sysmmu"; 854 reg = <0x11F20000 0x1000>; 855 interrupt-parent = <&combiner>; 856 interrupts = <4 2>; 857 power-domains = <&pd_gsc>; 858 clock-names = "sysmmu", "master"; 859 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 860 #iommu-cells = <0>; 861 }; 862 863 sysmmu_fimc_isp: sysmmu@13260000 { 864 compatible = "samsung,exynos-sysmmu"; 865 reg = <0x13260000 0x1000>; 866 interrupt-parent = <&combiner>; 867 interrupts = <10 6>; 868 clock-names = "sysmmu"; 869 clocks = <&clock CLK_SMMU_FIMC_ISP>; 870 #iommu-cells = <0>; 871 }; 872 873 sysmmu_fimc_drc: sysmmu@13270000 { 874 compatible = "samsung,exynos-sysmmu"; 875 reg = <0x13270000 0x1000>; 876 interrupt-parent = <&combiner>; 877 interrupts = <11 6>; 878 clock-names = "sysmmu"; 879 clocks = <&clock CLK_SMMU_FIMC_DRC>; 880 #iommu-cells = <0>; 881 }; 882 883 sysmmu_fimc_fd: sysmmu@132A0000 { 884 compatible = "samsung,exynos-sysmmu"; 885 reg = <0x132A0000 0x1000>; 886 interrupt-parent = <&combiner>; 887 interrupts = <5 0>; 888 clock-names = "sysmmu"; 889 clocks = <&clock CLK_SMMU_FIMC_FD>; 890 #iommu-cells = <0>; 891 }; 892 893 sysmmu_fimc_scc: sysmmu@13280000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x13280000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <5 2>; 898 clock-names = "sysmmu"; 899 clocks = <&clock CLK_SMMU_FIMC_SCC>; 900 #iommu-cells = <0>; 901 }; 902 903 sysmmu_fimc_scp: sysmmu@13290000 { 904 compatible = "samsung,exynos-sysmmu"; 905 reg = <0x13290000 0x1000>; 906 interrupt-parent = <&combiner>; 907 interrupts = <3 6>; 908 clock-names = "sysmmu"; 909 clocks = <&clock CLK_SMMU_FIMC_SCP>; 910 #iommu-cells = <0>; 911 }; 912 913 sysmmu_fimc_mcuctl: sysmmu@132B0000 { 914 compatible = "samsung,exynos-sysmmu"; 915 reg = <0x132B0000 0x1000>; 916 interrupt-parent = <&combiner>; 917 interrupts = <5 4>; 918 clock-names = "sysmmu"; 919 clocks = <&clock CLK_SMMU_FIMC_MCU>; 920 #iommu-cells = <0>; 921 }; 922 923 sysmmu_fimc_odc: sysmmu@132C0000 { 924 compatible = "samsung,exynos-sysmmu"; 925 reg = <0x132C0000 0x1000>; 926 interrupt-parent = <&combiner>; 927 interrupts = <11 0>; 928 clock-names = "sysmmu"; 929 clocks = <&clock CLK_SMMU_FIMC_ODC>; 930 #iommu-cells = <0>; 931 }; 932 933 sysmmu_fimc_dis0: sysmmu@132D0000 { 934 compatible = "samsung,exynos-sysmmu"; 935 reg = <0x132D0000 0x1000>; 936 interrupt-parent = <&combiner>; 937 interrupts = <10 4>; 938 clock-names = "sysmmu"; 939 clocks = <&clock CLK_SMMU_FIMC_DIS0>; 940 #iommu-cells = <0>; 941 }; 942 943 sysmmu_fimc_dis1: sysmmu@132E0000{ 944 compatible = "samsung,exynos-sysmmu"; 945 reg = <0x132E0000 0x1000>; 946 interrupt-parent = <&combiner>; 947 interrupts = <9 4>; 948 clock-names = "sysmmu"; 949 clocks = <&clock CLK_SMMU_FIMC_DIS1>; 950 #iommu-cells = <0>; 951 }; 952 953 sysmmu_fimc_3dnr: sysmmu@132F0000 { 954 compatible = "samsung,exynos-sysmmu"; 955 reg = <0x132F0000 0x1000>; 956 interrupt-parent = <&combiner>; 957 interrupts = <5 6>; 958 clock-names = "sysmmu"; 959 clocks = <&clock CLK_SMMU_FIMC_3DNR>; 960 #iommu-cells = <0>; 961 }; 962 963 sysmmu_fimc_lite0: sysmmu@13C40000 { 964 compatible = "samsung,exynos-sysmmu"; 965 reg = <0x13C40000 0x1000>; 966 interrupt-parent = <&combiner>; 967 interrupts = <3 4>; 968 power-domains = <&pd_gsc>; 969 clock-names = "sysmmu", "master"; 970 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 971 #iommu-cells = <0>; 972 }; 973 974 sysmmu_fimc_lite1: sysmmu@13C50000 { 975 compatible = "samsung,exynos-sysmmu"; 976 reg = <0x13C50000 0x1000>; 977 interrupt-parent = <&combiner>; 978 interrupts = <24 1>; 979 power-domains = <&pd_gsc>; 980 clock-names = "sysmmu", "master"; 981 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 982 #iommu-cells = <0>; 983 }; 984 985 sysmmu_gsc0: sysmmu@13E80000 { 986 compatible = "samsung,exynos-sysmmu"; 987 reg = <0x13E80000 0x1000>; 988 interrupt-parent = <&combiner>; 989 interrupts = <2 0>; 990 power-domains = <&pd_gsc>; 991 clock-names = "sysmmu", "master"; 992 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 993 #iommu-cells = <0>; 994 }; 995 996 sysmmu_gsc1: sysmmu@13E90000 { 997 compatible = "samsung,exynos-sysmmu"; 998 reg = <0x13E90000 0x1000>; 999 interrupt-parent = <&combiner>; 1000 interrupts = <2 2>; 1001 power-domains = <&pd_gsc>; 1002 clock-names = "sysmmu", "master"; 1003 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1004 #iommu-cells = <0>; 1005 }; 1006 1007 sysmmu_gsc2: sysmmu@13EA0000 { 1008 compatible = "samsung,exynos-sysmmu"; 1009 reg = <0x13EA0000 0x1000>; 1010 interrupt-parent = <&combiner>; 1011 interrupts = <2 4>; 1012 power-domains = <&pd_gsc>; 1013 clock-names = "sysmmu", "master"; 1014 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 1015 #iommu-cells = <0>; 1016 }; 1017 1018 sysmmu_gsc3: sysmmu@13EB0000 { 1019 compatible = "samsung,exynos-sysmmu"; 1020 reg = <0x13EB0000 0x1000>; 1021 interrupt-parent = <&combiner>; 1022 interrupts = <2 6>; 1023 power-domains = <&pd_gsc>; 1024 clock-names = "sysmmu", "master"; 1025 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 1026 #iommu-cells = <0>; 1027 }; 1028 1029 sysmmu_fimd1: sysmmu@14640000 { 1030 compatible = "samsung,exynos-sysmmu"; 1031 reg = <0x14640000 0x1000>; 1032 interrupt-parent = <&combiner>; 1033 interrupts = <3 2>; 1034 power-domains = <&pd_disp1>; 1035 clock-names = "sysmmu", "master"; 1036 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 1037 #iommu-cells = <0>; 1038 }; 1039 1040 sysmmu_tv: sysmmu@14650000 { 1041 compatible = "samsung,exynos-sysmmu"; 1042 reg = <0x14650000 0x1000>; 1043 interrupt-parent = <&combiner>; 1044 interrupts = <7 4>; 1045 power-domains = <&pd_disp1>; 1046 clock-names = "sysmmu", "master"; 1047 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1048 #iommu-cells = <0>; 1049 }; 1050 }; 1051 1052 thermal-zones { 1053 cpu_thermal: cpu-thermal { 1054 polling-delay-passive = <0>; 1055 polling-delay = <0>; 1056 thermal-sensors = <&tmu 0>; 1057 1058 cooling-maps { 1059 map0 { 1060 /* Corresponds to 800MHz at freq_table */ 1061 cooling-device = <&cpu0 9 9>; 1062 }; 1063 map1 { 1064 /* Corresponds to 200MHz at freq_table */ 1065 cooling-device = <&cpu0 15 15>; 1066 }; 1067 }; 1068 }; 1069 }; 1070}; 1071 1072&dp { 1073 power-domains = <&pd_disp1>; 1074 clocks = <&clock CLK_DP>; 1075 clock-names = "dp"; 1076 phys = <&dp_phy>; 1077 phy-names = "dp"; 1078}; 1079 1080&fimd { 1081 power-domains = <&pd_disp1>; 1082 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1083 clock-names = "sclk_fimd", "fimd"; 1084 iommus = <&sysmmu_fimd1>; 1085}; 1086 1087&i2c_0 { 1088 clocks = <&clock CLK_I2C0>; 1089 clock-names = "i2c"; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&i2c0_bus>; 1092}; 1093 1094&i2c_1 { 1095 clocks = <&clock CLK_I2C1>; 1096 clock-names = "i2c"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&i2c1_bus>; 1099}; 1100 1101&i2c_2 { 1102 clocks = <&clock CLK_I2C2>; 1103 clock-names = "i2c"; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&i2c2_bus>; 1106}; 1107 1108&i2c_3 { 1109 clocks = <&clock CLK_I2C3>; 1110 clock-names = "i2c"; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&i2c3_bus>; 1113}; 1114 1115&pwm { 1116 clocks = <&clock CLK_PWM>; 1117 clock-names = "timers"; 1118}; 1119 1120&rtc { 1121 clocks = <&clock CLK_RTC>; 1122 clock-names = "rtc"; 1123 interrupt-parent = <&pmu_system_controller>; 1124 status = "disabled"; 1125}; 1126 1127&serial_0 { 1128 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1129 clock-names = "uart", "clk_uart_baud0"; 1130 dmas = <&pdma0 13>, <&pdma0 14>; 1131 dma-names = "rx", "tx"; 1132}; 1133 1134&serial_1 { 1135 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1136 clock-names = "uart", "clk_uart_baud0"; 1137 dmas = <&pdma1 15>, <&pdma1 16>; 1138 dma-names = "rx", "tx"; 1139}; 1140 1141&serial_2 { 1142 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1143 clock-names = "uart", "clk_uart_baud0"; 1144 dmas = <&pdma0 15>, <&pdma0 16>; 1145 dma-names = "rx", "tx"; 1146}; 1147 1148&serial_3 { 1149 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1150 clock-names = "uart", "clk_uart_baud0"; 1151 dmas = <&pdma1 17>, <&pdma1 18>; 1152 dma-names = "rx", "tx"; 1153}; 1154 1155#include "exynos5250-pinctrl.dtsi" 1156