1/* 2 * SAMSUNG EXYNOS5260 SoC device tree source 3 * 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10*/ 11 12#include <dt-bindings/clock/exynos5260-clk.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16/ { 17 compatible = "samsung,exynos5260", "samsung,exynos5"; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 pinctrl0 = &pinctrl_0; 24 pinctrl1 = &pinctrl_1; 25 pinctrl2 = &pinctrl_2; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a15"; 39 reg = <0x0>; 40 cci-control-port = <&cci_control1>; 41 }; 42 43 cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a15"; 46 reg = <0x1>; 47 cci-control-port = <&cci_control1>; 48 }; 49 50 cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a7"; 53 reg = <0x100>; 54 cci-control-port = <&cci_control0>; 55 }; 56 57 cpu@101 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x101>; 61 cci-control-port = <&cci_control0>; 62 }; 63 64 cpu@102 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a7"; 67 reg = <0x102>; 68 cci-control-port = <&cci_control0>; 69 }; 70 71 cpu@103 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a7"; 74 reg = <0x103>; 75 cci-control-port = <&cci_control0>; 76 }; 77 }; 78 79 soc: soc { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 clock_top: clock-controller@10010000 { 86 compatible = "samsung,exynos5260-clock-top"; 87 reg = <0x10010000 0x10000>; 88 #clock-cells = <1>; 89 }; 90 91 clock_peri: clock-controller@10200000 { 92 compatible = "samsung,exynos5260-clock-peri"; 93 reg = <0x10200000 0x10000>; 94 #clock-cells = <1>; 95 }; 96 97 clock_egl: clock-controller@10600000 { 98 compatible = "samsung,exynos5260-clock-egl"; 99 reg = <0x10600000 0x10000>; 100 #clock-cells = <1>; 101 }; 102 103 clock_kfc: clock-controller@10700000 { 104 compatible = "samsung,exynos5260-clock-kfc"; 105 reg = <0x10700000 0x10000>; 106 #clock-cells = <1>; 107 }; 108 109 clock_g2d: clock-controller@10A00000 { 110 compatible = "samsung,exynos5260-clock-g2d"; 111 reg = <0x10A00000 0x10000>; 112 #clock-cells = <1>; 113 }; 114 115 clock_mif: clock-controller@10CE0000 { 116 compatible = "samsung,exynos5260-clock-mif"; 117 reg = <0x10CE0000 0x10000>; 118 #clock-cells = <1>; 119 }; 120 121 clock_mfc: clock-controller@11090000 { 122 compatible = "samsung,exynos5260-clock-mfc"; 123 reg = <0x11090000 0x10000>; 124 #clock-cells = <1>; 125 }; 126 127 clock_g3d: clock-controller@11830000 { 128 compatible = "samsung,exynos5260-clock-g3d"; 129 reg = <0x11830000 0x10000>; 130 #clock-cells = <1>; 131 }; 132 133 clock_fsys: clock-controller@122E0000 { 134 compatible = "samsung,exynos5260-clock-fsys"; 135 reg = <0x122E0000 0x10000>; 136 #clock-cells = <1>; 137 }; 138 139 clock_aud: clock-controller@128C0000 { 140 compatible = "samsung,exynos5260-clock-aud"; 141 reg = <0x128C0000 0x10000>; 142 #clock-cells = <1>; 143 }; 144 145 clock_isp: clock-controller@133C0000 { 146 compatible = "samsung,exynos5260-clock-isp"; 147 reg = <0x133C0000 0x10000>; 148 #clock-cells = <1>; 149 }; 150 151 clock_gscl: clock-controller@13F00000 { 152 compatible = "samsung,exynos5260-clock-gscl"; 153 reg = <0x13F00000 0x10000>; 154 #clock-cells = <1>; 155 }; 156 157 clock_disp: clock-controller@14550000 { 158 compatible = "samsung,exynos5260-clock-disp"; 159 reg = <0x14550000 0x10000>; 160 #clock-cells = <1>; 161 }; 162 163 gic: interrupt-controller@10481000 { 164 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 165 #interrupt-cells = <3>; 166 #address-cells = <0>; 167 #size-cells = <0>; 168 interrupt-controller; 169 reg = <0x10481000 0x1000>, 170 <0x10482000 0x2000>, 171 <0x10484000 0x2000>, 172 <0x10486000 0x2000>; 173 interrupts = <GIC_PPI 9 174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 175 }; 176 177 chipid: chipid@10000000 { 178 compatible = "samsung,exynos4210-chipid"; 179 reg = <0x10000000 0x100>; 180 }; 181 182 mct: mct@100B0000 { 183 compatible = "samsung,exynos4210-mct"; 184 reg = <0x100B0000 0x1000>; 185 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; 186 clock-names = "fin_pll", "mct"; 187 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 cci: cci@10F00000 { 202 compatible = "arm,cci-400"; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 reg = <0x10F00000 0x1000>; 206 ranges = <0x0 0x10F00000 0x6000>; 207 208 cci_control0: slave-if@4000 { 209 compatible = "arm,cci-400-ctrl-if"; 210 interface-type = "ace"; 211 reg = <0x4000 0x1000>; 212 }; 213 214 cci_control1: slave-if@5000 { 215 compatible = "arm,cci-400-ctrl-if"; 216 interface-type = "ace"; 217 reg = <0x5000 0x1000>; 218 }; 219 }; 220 221 pinctrl_0: pinctrl@11600000 { 222 compatible = "samsung,exynos5260-pinctrl"; 223 reg = <0x11600000 0x1000>; 224 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 225 226 wakeup-interrupt-controller { 227 compatible = "samsung,exynos4210-wakeup-eint"; 228 interrupt-parent = <&gic>; 229 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 230 }; 231 }; 232 233 pinctrl_1: pinctrl@12290000 { 234 compatible = "samsung,exynos5260-pinctrl"; 235 reg = <0x12290000 0x1000>; 236 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 pinctrl_2: pinctrl@128B0000 { 240 compatible = "samsung,exynos5260-pinctrl"; 241 reg = <0x128B0000 0x1000>; 242 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 243 }; 244 245 pmu_system_controller: system-controller@10D50000 { 246 compatible = "samsung,exynos5260-pmu", "syscon"; 247 reg = <0x10D50000 0x10000>; 248 }; 249 250 uart0: serial@12C00000 { 251 compatible = "samsung,exynos4210-uart"; 252 reg = <0x12C00000 0x100>; 253 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; 255 clock-names = "uart", "clk_uart_baud0"; 256 status = "disabled"; 257 }; 258 259 uart1: serial@12C10000 { 260 compatible = "samsung,exynos4210-uart"; 261 reg = <0x12C10000 0x100>; 262 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; 264 clock-names = "uart", "clk_uart_baud0"; 265 status = "disabled"; 266 }; 267 268 uart2: serial@12C20000 { 269 compatible = "samsung,exynos4210-uart"; 270 reg = <0x12C20000 0x100>; 271 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; 273 clock-names = "uart", "clk_uart_baud0"; 274 status = "disabled"; 275 }; 276 277 uart3: serial@12860000 { 278 compatible = "samsung,exynos4210-uart"; 279 reg = <0x12860000 0x100>; 280 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; 282 clock-names = "uart", "clk_uart_baud0"; 283 status = "disabled"; 284 }; 285 286 mmc_0: mmc@12140000 { 287 compatible = "samsung,exynos5250-dw-mshc"; 288 reg = <0x12140000 0x2000>; 289 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; 293 clock-names = "biu", "ciu"; 294 fifo-depth = <64>; 295 status = "disabled"; 296 }; 297 298 mmc_1: mmc@12150000 { 299 compatible = "samsung,exynos5250-dw-mshc"; 300 reg = <0x12150000 0x2000>; 301 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; 305 clock-names = "biu", "ciu"; 306 fifo-depth = <64>; 307 status = "disabled"; 308 }; 309 310 mmc_2: mmc@12160000 { 311 compatible = "samsung,exynos5250-dw-mshc"; 312 reg = <0x12160000 0x2000>; 313 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; 317 clock-names = "biu", "ciu"; 318 fifo-depth = <64>; 319 status = "disabled"; 320 }; 321 }; 322}; 323 324#include "exynos5260-pinctrl.dtsi" 325