1/* 2 * SAMSUNG EXYNOS5422 SoC cpu device tree source 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. 8 * 9 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration 10 * but particular boards choose different booting order. 11 * 12 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 13 * booting cluster (big or LITTLE) is chosen by IROM code by reading 14 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting 15 * from the LITTLE: Cortex-A7. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22/ { 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@100 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a7"; 30 reg = <0x100>; 31 clocks = <&clock CLK_KFC_CLK>; 32 clock-frequency = <1000000000>; 33 cci-control-port = <&cci_control0>; 34 operating-points-v2 = <&cluster_a7_opp_table>; 35 #cooling-cells = <2>; /* min followed by max */ 36 }; 37 38 cpu1: cpu@101 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0x101>; 42 clock-frequency = <1000000000>; 43 cci-control-port = <&cci_control0>; 44 operating-points-v2 = <&cluster_a7_opp_table>; 45 #cooling-cells = <2>; /* min followed by max */ 46 }; 47 48 cpu2: cpu@102 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a7"; 51 reg = <0x102>; 52 clock-frequency = <1000000000>; 53 cci-control-port = <&cci_control0>; 54 operating-points-v2 = <&cluster_a7_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu3: cpu@103 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0x103>; 62 clock-frequency = <1000000000>; 63 cci-control-port = <&cci_control0>; 64 operating-points-v2 = <&cluster_a7_opp_table>; 65 #cooling-cells = <2>; /* min followed by max */ 66 }; 67 68 cpu4: cpu@0 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a15"; 71 clocks = <&clock CLK_ARM_CLK>; 72 reg = <0x0>; 73 clock-frequency = <1800000000>; 74 cci-control-port = <&cci_control1>; 75 operating-points-v2 = <&cluster_a15_opp_table>; 76 #cooling-cells = <2>; /* min followed by max */ 77 }; 78 79 cpu5: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a15"; 82 reg = <0x1>; 83 clock-frequency = <1800000000>; 84 cci-control-port = <&cci_control1>; 85 operating-points-v2 = <&cluster_a15_opp_table>; 86 #cooling-cells = <2>; /* min followed by max */ 87 }; 88 89 cpu6: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a15"; 92 reg = <0x2>; 93 clock-frequency = <1800000000>; 94 cci-control-port = <&cci_control1>; 95 operating-points-v2 = <&cluster_a15_opp_table>; 96 #cooling-cells = <2>; /* min followed by max */ 97 }; 98 99 cpu7: cpu@3 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a15"; 102 reg = <0x3>; 103 clock-frequency = <1800000000>; 104 cci-control-port = <&cci_control1>; 105 operating-points-v2 = <&cluster_a15_opp_table>; 106 #cooling-cells = <2>; /* min followed by max */ 107 }; 108 }; 109}; 110