1/* 2 * Copyright 2013 Gateworks Corporation 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13 14/ { 15 /* these are used by bootloader for disabling nodes */ 16 aliases { 17 led0 = &led0; 18 led1 = &led1; 19 led2 = &led2; 20 nand = &gpmi; 21 ssi0 = &ssi1; 22 usb0 = &usbh1; 23 usb1 = &usbotg; 24 }; 25 26 chosen { 27 bootargs = "console=ttymxc1,115200"; 28 }; 29 30 backlight { 31 compatible = "pwm-backlight"; 32 pwms = <&pwm4 0 5000000>; 33 brightness-levels = <0 4 8 16 32 64 128 255>; 34 default-brightness-level = <7>; 35 }; 36 37 leds { 38 compatible = "gpio-leds"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_gpio_leds>; 41 42 led0: user1 { 43 label = "user1"; 44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 45 default-state = "on"; 46 linux,default-trigger = "heartbeat"; 47 }; 48 49 led1: user2 { 50 label = "user2"; 51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 52 default-state = "off"; 53 }; 54 55 led2: user3 { 56 label = "user3"; 57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 58 default-state = "off"; 59 }; 60 }; 61 62 memory { 63 reg = <0x10000000 0x40000000>; 64 }; 65 66 pps { 67 compatible = "pps-gpio"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_pps>; 70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 71 status = "okay"; 72 }; 73 74 reg_1p0v: regulator-1p0v { 75 compatible = "regulator-fixed"; 76 regulator-name = "1P0V"; 77 regulator-min-microvolt = <1000000>; 78 regulator-max-microvolt = <1000000>; 79 regulator-always-on; 80 }; 81 82 reg_3p3v: regulator-3p3v { 83 compatible = "regulator-fixed"; 84 regulator-name = "3P3V"; 85 regulator-min-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>; 87 regulator-always-on; 88 }; 89 90 reg_usb_h1_vbus: regulator-usb-h1-vbus { 91 compatible = "regulator-fixed"; 92 regulator-name = "usb_h1_vbus"; 93 regulator-min-microvolt = <5000000>; 94 regulator-max-microvolt = <5000000>; 95 regulator-always-on; 96 }; 97 98 reg_usb_otg_vbus: regulator-usb-otg-vbus { 99 compatible = "regulator-fixed"; 100 regulator-name = "usb_otg_vbus"; 101 regulator-min-microvolt = <5000000>; 102 regulator-max-microvolt = <5000000>; 103 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 }; 106 107 sound { 108 compatible = "fsl,imx6q-ventana-sgtl5000", 109 "fsl,imx-audio-sgtl5000"; 110 model = "sgtl5000-audio"; 111 ssi-controller = <&ssi1>; 112 audio-codec = <&codec>; 113 audio-routing = 114 "MIC_IN", "Mic Jack", 115 "Mic Jack", "Mic Bias", 116 "Headphone Jack", "HP_OUT"; 117 mux-int-port = <1>; 118 mux-ext-port = <4>; 119 }; 120}; 121 122&audmux { 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_audmux>; 125 status = "okay"; 126}; 127 128&can1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_flexcan1>; 131 status = "okay"; 132}; 133 134&clks { 135 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 136 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 137 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 138 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 139}; 140 141&fec { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_enet>; 144 phy-mode = "rgmii-id"; 145 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 146 status = "okay"; 147}; 148 149&gpmi { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_gpmi_nand>; 152 status = "okay"; 153}; 154 155&hdmi { 156 ddc-i2c-bus = <&i2c3>; 157 status = "okay"; 158}; 159 160&i2c1 { 161 clock-frequency = <100000>; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_i2c1>; 164 status = "okay"; 165 166 eeprom1: eeprom@50 { 167 compatible = "atmel,24c02"; 168 reg = <0x50>; 169 pagesize = <16>; 170 }; 171 172 eeprom2: eeprom@51 { 173 compatible = "atmel,24c02"; 174 reg = <0x51>; 175 pagesize = <16>; 176 }; 177 178 eeprom3: eeprom@52 { 179 compatible = "atmel,24c02"; 180 reg = <0x52>; 181 pagesize = <16>; 182 }; 183 184 eeprom4: eeprom@53 { 185 compatible = "atmel,24c02"; 186 reg = <0x53>; 187 pagesize = <16>; 188 }; 189 190 gpio: pca9555@23 { 191 compatible = "nxp,pca9555"; 192 reg = <0x23>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 }; 196 197 rtc: ds1672@68 { 198 compatible = "dallas,ds1672"; 199 reg = <0x68>; 200 }; 201}; 202 203&i2c2 { 204 clock-frequency = <100000>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_i2c2>; 207 status = "okay"; 208 209 ltc3676: pmic@3c { 210 compatible = "lltc,ltc3676"; 211 reg = <0x3c>; 212 interrupt-parent = <&gpio1>; 213 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 214 215 regulators { 216 /* VDD_SOC (1+R1/R2 = 1.635) */ 217 reg_vdd_soc: sw1 { 218 regulator-name = "vddsoc"; 219 regulator-min-microvolt = <674400>; 220 regulator-max-microvolt = <1308000>; 221 lltc,fb-voltage-divider = <127000 200000>; 222 regulator-ramp-delay = <7000>; 223 regulator-boot-on; 224 regulator-always-on; 225 }; 226 227 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 228 reg_1p8v: sw2 { 229 regulator-name = "vdd1p8"; 230 regulator-min-microvolt = <1033310>; 231 regulator-max-microvolt = <2004000>; 232 lltc,fb-voltage-divider = <301000 200000>; 233 regulator-ramp-delay = <7000>; 234 regulator-boot-on; 235 regulator-always-on; 236 }; 237 238 /* VDD_ARM (1+R1/R2 = 1.635) */ 239 reg_vdd_arm: sw3 { 240 regulator-name = "vddarm"; 241 regulator-min-microvolt = <674400>; 242 regulator-max-microvolt = <1308000>; 243 lltc,fb-voltage-divider = <127000 200000>; 244 regulator-ramp-delay = <7000>; 245 regulator-boot-on; 246 regulator-always-on; 247 }; 248 249 /* VDD_DDR (1+R1/R2 = 2.105) */ 250 reg_vdd_ddr: sw4 { 251 regulator-name = "vddddr"; 252 regulator-min-microvolt = <868310>; 253 regulator-max-microvolt = <1684000>; 254 lltc,fb-voltage-divider = <221000 200000>; 255 regulator-ramp-delay = <7000>; 256 regulator-boot-on; 257 regulator-always-on; 258 }; 259 260 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 261 reg_2p5v: ldo2 { 262 regulator-name = "vdd2p5"; 263 regulator-min-microvolt = <2490375>; 264 regulator-max-microvolt = <2490375>; 265 lltc,fb-voltage-divider = <487000 200000>; 266 regulator-boot-on; 267 regulator-always-on; 268 }; 269 270 /* VDD_AUD_1P8: Audio codec */ 271 reg_aud_1p8v: ldo3 { 272 regulator-name = "vdd1p8a"; 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <1800000>; 275 regulator-boot-on; 276 }; 277 278 /* VDD_HIGH (1+R1/R2 = 4.17) */ 279 reg_3p0v: ldo4 { 280 regulator-name = "vdd3p0"; 281 regulator-min-microvolt = <3023250>; 282 regulator-max-microvolt = <3023250>; 283 lltc,fb-voltage-divider = <634000 200000>; 284 regulator-boot-on; 285 regulator-always-on; 286 }; 287 }; 288 }; 289}; 290 291&i2c3 { 292 clock-frequency = <100000>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_i2c3>; 295 status = "okay"; 296 297 codec: sgtl5000@0a { 298 compatible = "fsl,sgtl5000"; 299 reg = <0x0a>; 300 clocks = <&clks IMX6QDL_CLK_CKO>; 301 VDDA-supply = <®_1p8v>; 302 VDDIO-supply = <®_3p3v>; 303 }; 304 305 touchscreen: egalax_ts@04 { 306 compatible = "eeti,egalax_ts"; 307 reg = <0x04>; 308 interrupt-parent = <&gpio1>; 309 interrupts = <11 2>; 310 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 311 }; 312}; 313 314&ldb { 315 status = "okay"; 316 317 lvds-channel@0 { 318 fsl,data-mapping = "spwg"; 319 fsl,data-width = <18>; 320 status = "okay"; 321 322 display-timings { 323 native-mode = <&timing0>; 324 timing0: hsd100pxn1 { 325 clock-frequency = <65000000>; 326 hactive = <1024>; 327 vactive = <768>; 328 hback-porch = <220>; 329 hfront-porch = <40>; 330 vback-porch = <21>; 331 vfront-porch = <7>; 332 hsync-len = <60>; 333 vsync-len = <10>; 334 }; 335 }; 336 }; 337}; 338 339&pcie { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_pcie>; 342 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 343 status = "okay"; 344}; 345 346&pwm2 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 349 status = "disabled"; 350}; 351 352&pwm3 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 355 status = "disabled"; 356}; 357 358&pwm4 { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_pwm4>; 361 status = "okay"; 362}; 363 364&ssi1 { 365 status = "okay"; 366}; 367 368&uart1 { 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_uart1>; 371 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 372 status = "okay"; 373}; 374 375&uart2 { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_uart2>; 378 status = "okay"; 379}; 380 381&uart5 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_uart5>; 384 status = "okay"; 385}; 386 387&usbotg { 388 vbus-supply = <®_usb_otg_vbus>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_usbotg>; 391 disable-over-current; 392 status = "okay"; 393}; 394 395&usbh1 { 396 vbus-supply = <®_usb_h1_vbus>; 397 status = "okay"; 398}; 399 400&usdhc3 { 401 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 402 pinctrl-0 = <&pinctrl_usdhc3>; 403 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 404 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 405 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 406 vmmc-supply = <®_3p3v>; 407 no-1-8-v; /* firmware will remove if board revision supports */ 408 status = "okay"; 409}; 410 411&wdog1 { 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_wdog>; 414 fsl,ext-reset-output; 415}; 416 417&iomuxc { 418 imx6qdl-gw53xx { 419 pinctrl_audmux: audmuxgrp { 420 fsl,pins = < 421 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 422 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 423 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 424 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 425 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 426 >; 427 }; 428 429 pinctrl_enet: enetgrp { 430 fsl,pins = < 431 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 432 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 433 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 434 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 435 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 436 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 437 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 438 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 439 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 440 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 441 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 442 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 443 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 444 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 445 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 446 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 447 >; 448 }; 449 450 pinctrl_flexcan1: flexcan1grp { 451 fsl,pins = < 452 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 453 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 454 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 455 >; 456 }; 457 458 pinctrl_gpio_leds: gpioledsgrp { 459 fsl,pins = < 460 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 461 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 462 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 463 >; 464 }; 465 466 pinctrl_gpmi_nand: gpminandgrp { 467 fsl,pins = < 468 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 469 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 470 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 471 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 472 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 473 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 474 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 475 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 476 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 477 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 478 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 479 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 480 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 481 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 482 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 483 >; 484 }; 485 486 pinctrl_i2c1: i2c1grp { 487 fsl,pins = < 488 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 489 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 490 >; 491 }; 492 493 pinctrl_i2c2: i2c2grp { 494 fsl,pins = < 495 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 496 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 497 >; 498 }; 499 500 pinctrl_i2c3: i2c3grp { 501 fsl,pins = < 502 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 503 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 504 >; 505 }; 506 507 pinctrl_pcie: pciegrp { 508 fsl,pins = < 509 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 510 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 511 >; 512 }; 513 514 pinctrl_pmic: pmicgrp { 515 fsl,pins = < 516 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 517 >; 518 }; 519 520 pinctrl_pps: ppsgrp { 521 fsl,pins = < 522 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 523 >; 524 }; 525 526 pinctrl_pwm2: pwm2grp { 527 fsl,pins = < 528 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 529 >; 530 }; 531 532 pinctrl_pwm3: pwm3grp { 533 fsl,pins = < 534 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 535 >; 536 }; 537 538 pinctrl_pwm4: pwm4grp { 539 fsl,pins = < 540 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 541 >; 542 }; 543 544 pinctrl_uart1: uart1grp { 545 fsl,pins = < 546 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 547 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 548 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 549 >; 550 }; 551 552 pinctrl_uart2: uart2grp { 553 fsl,pins = < 554 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 555 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 556 >; 557 }; 558 559 pinctrl_uart5: uart5grp { 560 fsl,pins = < 561 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 562 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 563 >; 564 }; 565 566 pinctrl_usbotg: usbotggrp { 567 fsl,pins = < 568 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 569 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 570 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 571 >; 572 }; 573 574 pinctrl_usdhc3: usdhc3grp { 575 fsl,pins = < 576 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 577 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 578 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 579 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 580 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 581 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 582 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 583 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 584 >; 585 }; 586 587 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 588 fsl,pins = < 589 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 590 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 591 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 592 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 593 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 594 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 595 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 596 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 597 >; 598 }; 599 600 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 601 fsl,pins = < 602 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 603 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 604 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 605 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 606 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 607 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 608 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 609 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 610 >; 611 }; 612 613 pinctrl_wdog: wdoggrp { 614 fsl,pins = < 615 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 616 >; 617 }; 618 }; 619}; 620