1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/input.h> 50 51/ { 52 /* these are used by bootloader for disabling nodes */ 53 aliases { 54 led0 = &led0; 55 led1 = &led1; 56 led2 = &led2; 57 ssi0 = &ssi1; 58 usb0 = &usbh1; 59 usb1 = &usbotg; 60 }; 61 62 chosen { 63 stdout-path = &uart2; 64 }; 65 66 backlight-display { 67 compatible = "pwm-backlight"; 68 pwms = <&pwm4 0 5000000>; 69 brightness-levels = < 70 0 1 2 3 4 5 6 7 8 9 71 10 11 12 13 14 15 16 17 18 19 72 20 21 22 23 24 25 26 27 28 29 73 30 31 32 33 34 35 36 37 38 39 74 40 41 42 43 44 45 46 47 48 49 75 50 51 52 53 54 55 56 57 58 59 76 60 61 62 63 64 65 66 67 68 69 77 70 71 72 73 74 75 76 77 78 79 78 80 81 82 83 84 85 86 87 88 89 79 90 91 92 93 94 95 96 97 98 99 80 100 81 >; 82 default-brightness-level = <100>; 83 }; 84 85 backlight-keypad { 86 compatible = "gpio-backlight"; 87 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 88 default-on; 89 }; 90 91 leds { 92 compatible = "gpio-leds"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_gpio_leds>; 95 96 led0: user1 { 97 label = "user1"; 98 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 99 default-state = "on"; 100 linux,default-trigger = "heartbeat"; 101 }; 102 103 led1: user2 { 104 label = "user2"; 105 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 106 default-state = "off"; 107 }; 108 109 led2: user3 { 110 label = "user3"; 111 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 112 default-state = "off"; 113 }; 114 }; 115 116 memory@10000000 { 117 reg = <0x10000000 0x40000000>; 118 }; 119 120 pps { 121 compatible = "pps-gpio"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_pps>; 124 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 125 }; 126 127 reg_2p5v: regulator-2p5v { 128 compatible = "regulator-fixed"; 129 regulator-name = "2P5V"; 130 regulator-min-microvolt = <2500000>; 131 regulator-max-microvolt = <2500000>; 132 regulator-always-on; 133 }; 134 135 reg_3p3v: regulator-3p3v { 136 compatible = "regulator-fixed"; 137 regulator-name = "3P3V"; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 regulator-always-on; 141 }; 142 143 reg_5p0v: regulator-5p0v { 144 compatible = "regulator-fixed"; 145 regulator-name = "5P0V"; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 regulator-always-on; 149 }; 150 151 reg_12p0v: regulator-12p0v { 152 compatible = "regulator-fixed"; 153 regulator-name = "12P0V"; 154 regulator-min-microvolt = <12000000>; 155 regulator-max-microvolt = <12000000>; 156 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 157 enable-active-high; 158 }; 159 160 reg_1p4v: regulator-vddsoc { 161 compatible = "regulator-fixed"; 162 regulator-name = "vdd_soc"; 163 regulator-min-microvolt = <1400000>; 164 regulator-max-microvolt = <1400000>; 165 regulator-always-on; 166 }; 167 168 reg_usb_h1_vbus: regulator-usb-h1-vbus { 169 compatible = "regulator-fixed"; 170 regulator-name = "usb_h1_vbus"; 171 regulator-min-microvolt = <5000000>; 172 regulator-max-microvolt = <5000000>; 173 regulator-always-on; 174 }; 175 176 reg_usb_otg_vbus: regulator-usb-otg-vbus { 177 compatible = "regulator-fixed"; 178 regulator-name = "usb_otg_vbus"; 179 regulator-min-microvolt = <5000000>; 180 regulator-max-microvolt = <5000000>; 181 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 182 enable-active-high; 183 }; 184 185 sound { 186 compatible = "fsl,imx6q-ventana-sgtl5000", 187 "fsl,imx-audio-sgtl5000"; 188 model = "sgtl5000-audio"; 189 ssi-controller = <&ssi1>; 190 audio-codec = <&sgtl5000>; 191 audio-routing = 192 "MIC_IN", "Mic Jack", 193 "Mic Jack", "Mic Bias", 194 "Headphone Jack", "HP_OUT"; 195 mux-int-port = <1>; 196 mux-ext-port = <4>; 197 }; 198}; 199 200&audmux { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_audmux>; 203 status = "okay"; 204}; 205 206&ecspi3 { 207 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_ecspi3>; 210 status = "okay"; 211}; 212 213&can1 { 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_flexcan>; 216 status = "okay"; 217}; 218 219&clks { 220 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 221 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 222 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 223 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 224}; 225 226&fec { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_enet>; 229 phy-mode = "rgmii-id"; 230 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 231 status = "okay"; 232}; 233 234&hdmi { 235 ddc-i2c-bus = <&i2c3>; 236 status = "okay"; 237}; 238 239&i2c1 { 240 clock-frequency = <100000>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_i2c1>; 243 status = "okay"; 244 245 eeprom1: eeprom@50 { 246 compatible = "atmel,24c02"; 247 reg = <0x50>; 248 pagesize = <16>; 249 }; 250 251 eeprom2: eeprom@51 { 252 compatible = "atmel,24c02"; 253 reg = <0x51>; 254 pagesize = <16>; 255 }; 256 257 eeprom3: eeprom@52 { 258 compatible = "atmel,24c02"; 259 reg = <0x52>; 260 pagesize = <16>; 261 }; 262 263 eeprom4: eeprom@53 { 264 compatible = "atmel,24c02"; 265 reg = <0x53>; 266 pagesize = <16>; 267 }; 268 269 pca9555: gpio@23 { 270 compatible = "nxp,pca9555"; 271 reg = <0x23>; 272 gpio-controller; 273 #gpio-cells = <2>; 274 }; 275 276 ds1672: rtc@68 { 277 compatible = "dallas,ds1672"; 278 reg = <0x68>; 279 }; 280}; 281 282&i2c2 { 283 clock-frequency = <100000>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_i2c2>; 286 status = "okay"; 287 288 sgtl5000: codec@a { 289 compatible = "fsl,sgtl5000"; 290 reg = <0x0a>; 291 clocks = <&clks IMX6QDL_CLK_CKO>; 292 VDDA-supply = <®_1p8v>; 293 VDDIO-supply = <®_3p3v>; 294 }; 295 296 tca8418: keypad@34 { 297 compatible = "ti,tca8418"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_keypad>; 300 reg = <0x34>; 301 interrupt-parent = <&gpio5>; 302 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 303 linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) 304 MATRIX_KEY(0x00, 0x00, BTN_1) 305 MATRIX_KEY(0x01, 0x01, BTN_2) 306 MATRIX_KEY(0x01, 0x00, BTN_3) 307 MATRIX_KEY(0x02, 0x00, BTN_4) 308 MATRIX_KEY(0x00, 0x03, BTN_5) 309 MATRIX_KEY(0x00, 0x02, BTN_6) 310 MATRIX_KEY(0x01, 0x03, BTN_7) 311 MATRIX_KEY(0x01, 0x02, BTN_8) 312 MATRIX_KEY(0x02, 0x02, BTN_9) 313 >; 314 keypad,num-rows = <4>; 315 keypad,num-columns = <4>; 316 }; 317 318 ltc3676: pmic@3c { 319 compatible = "lltc,ltc3676"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_pmic>; 322 reg = <0x3c>; 323 interrupt-parent = <&gpio1>; 324 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 325 326 regulators { 327 /* VDD_DDR (1+R1/R2 = 2.105) */ 328 reg_vdd_ddr: sw2 { 329 regulator-name = "vddddr"; 330 regulator-min-microvolt = <868310>; 331 regulator-max-microvolt = <1684000>; 332 lltc,fb-voltage-divider = <221000 200000>; 333 regulator-ramp-delay = <7000>; 334 regulator-boot-on; 335 regulator-always-on; 336 }; 337 338 /* VDD_ARM (1+R1/R2 = 1.931) */ 339 reg_vdd_arm: sw3 { 340 regulator-name = "vddarm"; 341 regulator-min-microvolt = <796551>; 342 regulator-max-microvolt = <1544827>; 343 lltc,fb-voltage-divider = <243000 261000>; 344 regulator-ramp-delay = <7000>; 345 regulator-boot-on; 346 regulator-always-on; 347 linux,phandle = <®_vdd_arm>; 348 }; 349 350 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 351 reg_1p8v: sw4 { 352 regulator-name = "vdd1p8"; 353 regulator-min-microvolt = <1033310>; 354 regulator-max-microvolt = <2004000>; 355 lltc,fb-voltage-divider = <301000 200000>; 356 regulator-ramp-delay = <7000>; 357 regulator-boot-on; 358 regulator-always-on; 359 }; 360 361 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ 362 reg_1p0v: ldo2 { 363 regulator-name = "vdd1p0"; 364 regulator-min-microvolt = <950000>; 365 regulator-max-microvolt = <1050000>; 366 lltc,fb-voltage-divider = <78700 200000>; 367 regulator-boot-on; 368 regulator-always-on; 369 }; 370 371 /* VDD_AUD_1P8: Audio codec */ 372 reg_aud_1p8v: ldo3 { 373 regulator-name = "vdd1p8a"; 374 regulator-min-microvolt = <1800000>; 375 regulator-max-microvolt = <1800000>; 376 regulator-boot-on; 377 }; 378 379 /* VDD_HIGH (1+R1/R2 = 4.17) */ 380 reg_3p0v: ldo4 { 381 regulator-name = "vdd3p0"; 382 regulator-min-microvolt = <3023250>; 383 regulator-max-microvolt = <3023250>; 384 lltc,fb-voltage-divider = <634000 200000>; 385 regulator-boot-on; 386 regulator-always-on; 387 }; 388 }; 389 }; 390}; 391 392&i2c3 { 393 clock-frequency = <100000>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_i2c3>; 396 status = "okay"; 397 398 egalax_ts: touchscreen@4 { 399 compatible = "eeti,egalax_ts"; 400 reg = <0x04>; 401 interrupt-parent = <&gpio5>; 402 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 403 wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 404 }; 405}; 406 407&ldb { 408 fsl,dual-channel; 409 status = "okay"; 410 411 lvds-channel@0 { 412 fsl,data-mapping = "spwg"; 413 fsl,data-width = <18>; 414 status = "okay"; 415 416 display-timings { 417 native-mode = <&timing0>; 418 timing0: hsd100pxn1 { 419 clock-frequency = <65000000>; 420 hactive = <1024>; 421 vactive = <768>; 422 hback-porch = <220>; 423 hfront-porch = <40>; 424 vback-porch = <21>; 425 vfront-porch = <7>; 426 hsync-len = <60>; 427 vsync-len = <10>; 428 }; 429 }; 430 }; 431}; 432 433&pcie { 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_pcie>; 436 reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; 437 status = "okay"; 438}; 439 440&pwm2 { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 443 status = "disabled"; 444}; 445 446&pwm3 { 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 449 status = "disabled"; 450}; 451 452&pwm4 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_pwm4>; 455 status = "okay"; 456}; 457 458&ssi1 { 459 status = "okay"; 460}; 461 462&uart1 { 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_uart1>; 465 uart-has-rtscts; 466 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 467 status = "okay"; 468}; 469 470&uart2 { 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pinctrl_uart2>; 473 status = "okay"; 474}; 475 476&uart5 { 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_uart5>; 479 status = "okay"; 480}; 481 482&usbotg { 483 vbus-supply = <®_usb_otg_vbus>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pinctrl_usbotg>; 486 disable-over-current; 487 status = "okay"; 488}; 489 490&usbh1 { 491 vbus-supply = <®_usb_h1_vbus>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_usbh1>; 494 status = "okay"; 495}; 496 497&usdhc2 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_usdhc2>; 500 bus-width = <8>; 501 vmmc-supply = <®_3p3v>; 502 non-removable; 503 status = "okay"; 504}; 505 506&usdhc3 { 507 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 508 pinctrl-0 = <&pinctrl_usdhc3>; 509 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 510 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 511 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 512 vmmc-supply = <®_3p3v>; 513 status = "okay"; 514}; 515 516&wdog1 { 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pinctrl_wdog>; 519 fsl,ext-reset-output; 520}; 521 522&iomuxc { 523 pinctrl_audmux: audmuxgrp { 524 fsl,pins = < 525 /* AUD4 */ 526 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 527 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 528 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 529 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 530 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 531 /* AUD6 */ 532 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 533 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 534 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 535 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 536 >; 537 }; 538 539 pinctrl_ecspi3: escpi3grp { 540 fsl,pins = < 541 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 542 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 543 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 544 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 545 >; 546 }; 547 548 pinctrl_enet: enetgrp { 549 fsl,pins = < 550 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 551 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 552 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 553 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 554 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 555 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 556 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 557 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 558 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 559 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 560 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 561 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 562 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 563 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 564 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 565 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 566 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 567 >; 568 }; 569 570 pinctrl_flexcan: flexcangrp { 571 fsl,pins = < 572 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 573 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 574 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 575 >; 576 }; 577 578 pinctrl_gpio_leds: gpioledsgrp { 579 fsl,pins = < 580 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 581 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 582 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 583 >; 584 }; 585 586 pinctrl_i2c1: i2c1grp { 587 fsl,pins = < 588 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 589 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 590 >; 591 }; 592 593 pinctrl_i2c2: i2c2grp { 594 fsl,pins = < 595 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 596 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 597 >; 598 }; 599 600 pinctrl_i2c3: i2c3grp { 601 fsl,pins = < 602 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 603 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 604 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ 605 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ 606 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ 607 >; 608 }; 609 610 pinctrl_keypad: keypadgrp { 611 fsl,pins = < 612 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ 613 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ 614 >; 615 }; 616 617 pinctrl_pcie: pciegrp { 618 fsl,pins = < 619 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ 620 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 621 >; 622 }; 623 624 pinctrl_pmic: pmicgrp { 625 fsl,pins = < 626 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 627 >; 628 }; 629 630 pinctrl_pps: ppsgrp { 631 fsl,pins = < 632 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 633 >; 634 }; 635 636 pinctrl_pwm2: pwm2grp { 637 fsl,pins = < 638 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 639 >; 640 }; 641 642 pinctrl_pwm3: pwm3grp { 643 fsl,pins = < 644 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 645 >; 646 }; 647 648 pinctrl_pwm4: pwm4grp { 649 fsl,pins = < 650 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 651 >; 652 }; 653 654 pinctrl_uart1: uart1grp { 655 fsl,pins = < 656 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 657 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 658 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 659 >; 660 }; 661 662 pinctrl_uart2: uart2grp { 663 fsl,pins = < 664 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 665 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 666 >; 667 }; 668 669 pinctrl_uart5: uart5grp { 670 fsl,pins = < 671 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 672 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 673 >; 674 }; 675 676 pinctrl_usbh1: usbh1grp { 677 fsl,pins = < 678 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ 679 >; 680 }; 681 682 pinctrl_usbotg: usbotggrp { 683 fsl,pins = < 684 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 685 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 686 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 687 >; 688 }; 689 690 pinctrl_usdhc2: usdhc2grp { 691 fsl,pins = < 692 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 693 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 694 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 695 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 696 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 697 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 698 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 699 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 700 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 701 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 702 >; 703 }; 704 705 pinctrl_usdhc3: usdhc3grp { 706 fsl,pins = < 707 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 708 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 709 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 710 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 711 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 712 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 713 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 714 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 715 >; 716 }; 717 718 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 719 fsl,pins = < 720 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 721 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 722 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 723 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 724 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 725 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 726 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 727 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 728 >; 729 }; 730 731 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 732 fsl,pins = < 733 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 734 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 735 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 736 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 737 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 738 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 739 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 740 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 741 >; 742 }; 743 744 pinctrl_wdog: wdoggrp { 745 fsl,pins = < 746 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 747 >; 748 }; 749}; 750