1/* 2 * Embedded Artists LPC3250 board 3 * 4 * Copyright 2012 Roland Stigge <stigge@antcom.de> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14/dts-v1/; 15#include "lpc32xx.dtsi" 16 17/ { 18 model = "Embedded Artists LPC3250 board based on NXP LPC3250"; 19 compatible = "ea,ea3250", "nxp,lpc3250"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0x80000000 0x4000000>; 26 }; 27 28 gpio_keys { 29 compatible = "gpio-keys"; 30 #address-cells = <1>; 31 #size-cells = <0>; 32 autorepeat; 33 button@21 { 34 label = "Interrupt Key"; 35 linux,code = <103>; 36 gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ 37 }; 38 key1 { 39 label = "KEY1"; 40 linux,code = <1>; 41 gpios = <&pca9532 0 0>; 42 }; 43 key2 { 44 label = "KEY2"; 45 linux,code = <2>; 46 gpios = <&pca9532 1 0>; 47 }; 48 key3 { 49 label = "KEY3"; 50 linux,code = <3>; 51 gpios = <&pca9532 2 0>; 52 }; 53 key4 { 54 label = "KEY4"; 55 linux,code = <4>; 56 gpios = <&pca9532 3 0>; 57 }; 58 joy0 { 59 label = "Joystick Key 0"; 60 linux,code = <10>; 61 gpios = <&gpio 2 0 0>; /* P2.0 */ 62 }; 63 joy1 { 64 label = "Joystick Key 1"; 65 linux,code = <11>; 66 gpios = <&gpio 2 1 0>; /* P2.1 */ 67 }; 68 joy2 { 69 label = "Joystick Key 2"; 70 linux,code = <12>; 71 gpios = <&gpio 2 2 0>; /* P2.2 */ 72 }; 73 joy3 { 74 label = "Joystick Key 3"; 75 linux,code = <13>; 76 gpios = <&gpio 2 3 0>; /* P2.3 */ 77 }; 78 joy4 { 79 label = "Joystick Key 4"; 80 linux,code = <14>; 81 gpios = <&gpio 2 4 0>; /* P2.4 */ 82 }; 83 }; 84 85 leds { 86 compatible = "gpio-leds"; 87 88 /* LEDs on OEM Board */ 89 90 led1 { 91 gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ 92 linux,default-trigger = "timer"; 93 default-state = "off"; 94 }; 95 96 led2 { 97 gpios = <&gpio 2 10 1>; /* P2.10, active low */ 98 default-state = "off"; 99 }; 100 101 led3 { 102 gpios = <&gpio 2 11 1>; /* P2.11, active low */ 103 default-state = "off"; 104 }; 105 106 led4 { 107 gpios = <&gpio 2 12 1>; /* P2.12, active low */ 108 default-state = "off"; 109 }; 110 111 /* LEDs on Base Board */ 112 113 lede1 { 114 gpios = <&pca9532 8 0>; 115 default-state = "off"; 116 }; 117 lede2 { 118 gpios = <&pca9532 9 0>; 119 default-state = "off"; 120 }; 121 lede3 { 122 gpios = <&pca9532 10 0>; 123 default-state = "off"; 124 }; 125 lede4 { 126 gpios = <&pca9532 11 0>; 127 default-state = "off"; 128 }; 129 lede5 { 130 gpios = <&pca9532 12 0>; 131 default-state = "off"; 132 }; 133 lede6 { 134 gpios = <&pca9532 13 0>; 135 default-state = "off"; 136 }; 137 lede7 { 138 gpios = <&pca9532 14 0>; 139 default-state = "off"; 140 }; 141 lede8 { 142 gpios = <&pca9532 15 0>; 143 default-state = "off"; 144 }; 145 }; 146}; 147 148/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ 149&adc { 150 status = "okay"; 151}; 152 153&i2c1 { 154 clock-frequency = <100000>; 155 156 uda1380: uda1380@18 { 157 compatible = "nxp,uda1380"; 158 reg = <0x18>; 159 power-gpio = <&gpio 3 10 0>; 160 reset-gpio = <&gpio 3 2 0>; 161 dac-clk = "wspll"; 162 }; 163 164 eeprom@50 { 165 compatible = "atmel,24c256"; 166 reg = <0x50>; 167 }; 168 169 eeprom@57 { 170 compatible = "atmel,24c64"; 171 reg = <0x57>; 172 }; 173 174 pca9532: pca9532@60 { 175 compatible = "nxp,pca9532"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 reg = <0x60>; 179 }; 180}; 181 182&i2c2 { 183 clock-frequency = <100000>; 184}; 185 186&i2cusb { 187 clock-frequency = <100000>; 188 189 isp1301: usb-transceiver@2d { 190 compatible = "nxp,isp1301"; 191 reg = <0x2d>; 192 }; 193}; 194 195&mac { 196 phy-mode = "rmii"; 197 use-iram; 198}; 199 200/* Here, choose exactly one from: ohci, usbd */ 201&ohci /* &usbd */ { 202 transceiver = <&isp1301>; 203 status = "okay"; 204}; 205 206&sd { 207 wp-gpios = <&pca9532 5 0>; 208 cd-gpios = <&pca9532 4 0>; 209 cd-inverted; 210 bus-width = <4>; 211 status = "okay"; 212}; 213 214/* 128MB Flash via SLC NAND controller */ 215&slc { 216 status = "okay"; 217 218 nxp,wdr-clks = <14>; 219 nxp,wwidth = <260000000>; 220 nxp,whold = <104000000>; 221 nxp,wsetup = <200000000>; 222 nxp,rdr-clks = <14>; 223 nxp,rwidth = <34666666>; 224 nxp,rhold = <104000000>; 225 nxp,rsetup = <200000000>; 226 nand-on-flash-bbt; 227 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ 228 229 partitions { 230 compatible = "fixed-partitions"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 234 mtd0@00000000 { 235 label = "ea3250-boot"; 236 reg = <0x00000000 0x00080000>; 237 read-only; 238 }; 239 240 mtd1@00080000 { 241 label = "ea3250-uboot"; 242 reg = <0x00080000 0x000c0000>; 243 read-only; 244 }; 245 246 mtd2@00140000 { 247 label = "ea3250-kernel"; 248 reg = <0x00140000 0x00400000>; 249 }; 250 251 mtd3@00540000 { 252 label = "ea3250-rootfs"; 253 reg = <0x00540000 0x07ac0000>; 254 }; 255 }; 256}; 257 258&uart1 { 259 status = "okay"; 260}; 261 262&uart3 { 263 status = "okay"; 264}; 265 266&uart5 { 267 status = "okay"; 268}; 269 270&uart6 { 271 status = "okay"; 272}; 273