1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Joe.C <yingjoe.chen@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include "skeleton64.dtsi" 18 19/ { 20 compatible = "mediatek,mt8127"; 21 interrupt-parent = <&sysirq>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "mediatek,mt81xx-tz-smp"; 27 28 cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 }; 33 cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0x1>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0x2>; 42 }; 43 cpu@3 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0x3>; 47 }; 48 49 }; 50 51 reserved-memory { 52 #address-cells = <2>; 53 #size-cells = <2>; 54 ranges; 55 56 trustzone-bootinfo@80002000 { 57 compatible = "mediatek,trustzone-bootinfo"; 58 reg = <0 0x80002000 0 0x1000>; 59 }; 60 }; 61 62 clocks { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 compatible = "simple-bus"; 66 ranges; 67 68 system_clk: dummy13m { 69 compatible = "fixed-clock"; 70 clock-frequency = <13000000>; 71 #clock-cells = <0>; 72 }; 73 74 rtc_clk: dummy32k { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 80 uart_clk: dummy26m { 81 compatible = "fixed-clock"; 82 clock-frequency = <26000000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 timer { 88 compatible = "arm,armv7-timer"; 89 interrupt-parent = <&gic>; 90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 91 IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 93 IRQ_TYPE_LEVEL_LOW)>, 94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 95 IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 97 IRQ_TYPE_LEVEL_LOW)>; 98 clock-frequency = <13000000>; 99 arm,cpu-registers-not-fw-configured; 100 }; 101 102 soc { 103 #address-cells = <2>; 104 #size-cells = <2>; 105 compatible = "simple-bus"; 106 ranges; 107 108 timer: timer@10008000 { 109 compatible = "mediatek,mt8127-timer", 110 "mediatek,mt6577-timer"; 111 reg = <0 0x10008000 0 0x80>; 112 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 113 clocks = <&system_clk>, <&rtc_clk>; 114 clock-names = "system-clk", "rtc-clk"; 115 }; 116 117 sysirq: interrupt-controller@10200100 { 118 compatible = "mediatek,mt8127-sysirq", 119 "mediatek,mt6577-sysirq"; 120 interrupt-controller; 121 #interrupt-cells = <3>; 122 interrupt-parent = <&gic>; 123 reg = <0 0x10200100 0 0x1c>; 124 }; 125 126 gic: interrupt-controller@10211000 { 127 compatible = "arm,cortex-a7-gic"; 128 interrupt-controller; 129 #interrupt-cells = <3>; 130 interrupt-parent = <&gic>; 131 reg = <0 0x10211000 0 0x1000>, 132 <0 0x10212000 0 0x2000>, 133 <0 0x10214000 0 0x2000>, 134 <0 0x10216000 0 0x2000>; 135 }; 136 137 uart0: serial@11002000 { 138 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 139 reg = <0 0x11002000 0 0x400>; 140 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 141 clocks = <&uart_clk>; 142 status = "disabled"; 143 }; 144 145 uart1: serial@11003000 { 146 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 147 reg = <0 0x11003000 0 0x400>; 148 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 149 clocks = <&uart_clk>; 150 status = "disabled"; 151 }; 152 153 uart2: serial@11004000 { 154 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 155 reg = <0 0x11004000 0 0x400>; 156 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 157 clocks = <&uart_clk>; 158 status = "disabled"; 159 }; 160 161 uart3: serial@11005000 { 162 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 163 reg = <0 0x11005000 0 0x400>; 164 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 165 clocks = <&uart_clk>; 166 status = "disabled"; 167 }; 168 }; 169}; 170