1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8974.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/reset/qcom,gcc-msm8974.h> 8#include <dt-bindings/gpio/gpio.h> 9#include "skeleton.dtsi" 10 11/ { 12 model = "Qualcomm MSM8974"; 13 compatible = "qcom,msm8974"; 14 interrupt-parent = <&intc>; 15 16 reserved-memory { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 ranges; 20 21 mpss@08000000 { 22 reg = <0x08000000 0x5100000>; 23 no-map; 24 }; 25 26 mba@00d100000 { 27 reg = <0x0d100000 0x100000>; 28 no-map; 29 }; 30 31 reserved@0d200000 { 32 reg = <0x0d200000 0xa00000>; 33 no-map; 34 }; 35 36 adsp_region: adsp@0dc00000 { 37 reg = <0x0dc00000 0x1900000>; 38 no-map; 39 }; 40 41 venus@0f500000 { 42 reg = <0x0f500000 0x500000>; 43 no-map; 44 }; 45 46 smem_region: smem@fa00000 { 47 reg = <0xfa00000 0x200000>; 48 no-map; 49 }; 50 51 tz@0fc00000 { 52 reg = <0x0fc00000 0x160000>; 53 no-map; 54 }; 55 56 rfsa@0fd60000 { 57 reg = <0x0fd60000 0x20000>; 58 no-map; 59 }; 60 61 rmtfs@0fd80000 { 62 reg = <0x0fd80000 0x180000>; 63 no-map; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 interrupts = <1 9 0xf04>; 71 72 CPU0: cpu@0 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v2"; 75 device_type = "cpu"; 76 reg = <0>; 77 next-level-cache = <&L2>; 78 qcom,acc = <&acc0>; 79 qcom,saw = <&saw0>; 80 cpu-idle-states = <&CPU_SPC>; 81 }; 82 83 CPU1: cpu@1 { 84 compatible = "qcom,krait"; 85 enable-method = "qcom,kpss-acc-v2"; 86 device_type = "cpu"; 87 reg = <1>; 88 next-level-cache = <&L2>; 89 qcom,acc = <&acc1>; 90 qcom,saw = <&saw1>; 91 cpu-idle-states = <&CPU_SPC>; 92 }; 93 94 CPU2: cpu@2 { 95 compatible = "qcom,krait"; 96 enable-method = "qcom,kpss-acc-v2"; 97 device_type = "cpu"; 98 reg = <2>; 99 next-level-cache = <&L2>; 100 qcom,acc = <&acc2>; 101 qcom,saw = <&saw2>; 102 cpu-idle-states = <&CPU_SPC>; 103 }; 104 105 CPU3: cpu@3 { 106 compatible = "qcom,krait"; 107 enable-method = "qcom,kpss-acc-v2"; 108 device_type = "cpu"; 109 reg = <3>; 110 next-level-cache = <&L2>; 111 qcom,acc = <&acc3>; 112 qcom,saw = <&saw3>; 113 cpu-idle-states = <&CPU_SPC>; 114 }; 115 116 L2: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 qcom,saw = <&saw_l2>; 120 }; 121 122 idle-states { 123 CPU_SPC: spc { 124 compatible = "qcom,idle-state-spc", 125 "arm,idle-state"; 126 entry-latency-us = <150>; 127 exit-latency-us = <200>; 128 min-residency-us = <2000>; 129 }; 130 }; 131 }; 132 133 thermal-zones { 134 cpu-thermal0 { 135 polling-delay-passive = <250>; 136 polling-delay = <1000>; 137 138 thermal-sensors = <&tsens 5>; 139 140 trips { 141 cpu_alert0: trip0 { 142 temperature = <75000>; 143 hysteresis = <2000>; 144 type = "passive"; 145 }; 146 cpu_crit0: trip1 { 147 temperature = <110000>; 148 hysteresis = <2000>; 149 type = "critical"; 150 }; 151 }; 152 }; 153 154 cpu-thermal1 { 155 polling-delay-passive = <250>; 156 polling-delay = <1000>; 157 158 thermal-sensors = <&tsens 6>; 159 160 trips { 161 cpu_alert1: trip0 { 162 temperature = <75000>; 163 hysteresis = <2000>; 164 type = "passive"; 165 }; 166 cpu_crit1: trip1 { 167 temperature = <110000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 }; 173 174 cpu-thermal2 { 175 polling-delay-passive = <250>; 176 polling-delay = <1000>; 177 178 thermal-sensors = <&tsens 7>; 179 180 trips { 181 cpu_alert2: trip0 { 182 temperature = <75000>; 183 hysteresis = <2000>; 184 type = "passive"; 185 }; 186 cpu_crit2: trip1 { 187 temperature = <110000>; 188 hysteresis = <2000>; 189 type = "critical"; 190 }; 191 }; 192 }; 193 194 cpu-thermal3 { 195 polling-delay-passive = <250>; 196 polling-delay = <1000>; 197 198 thermal-sensors = <&tsens 8>; 199 200 trips { 201 cpu_alert3: trip0 { 202 temperature = <75000>; 203 hysteresis = <2000>; 204 type = "passive"; 205 }; 206 cpu_crit3: trip1 { 207 temperature = <110000>; 208 hysteresis = <2000>; 209 type = "critical"; 210 }; 211 }; 212 }; 213 }; 214 215 cpu-pmu { 216 compatible = "qcom,krait-pmu"; 217 interrupts = <1 7 0xf04>; 218 }; 219 220 clocks { 221 xo_board: xo_board { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <19200000>; 225 }; 226 227 sleep_clk: sleep_clk { 228 compatible = "fixed-clock"; 229 #clock-cells = <0>; 230 clock-frequency = <32768>; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv7-timer"; 236 interrupts = <1 2 0xf08>, 237 <1 3 0xf08>, 238 <1 4 0xf08>, 239 <1 1 0xf08>; 240 clock-frequency = <19200000>; 241 }; 242 243 adsp-pil { 244 compatible = "qcom,msm8974-adsp-pil"; 245 246 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 247 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 248 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 249 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 250 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 251 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 252 253 cx-supply = <&pm8841_s2>; 254 255 clocks = <&xo_board>; 256 clock-names = "xo"; 257 258 memory-region = <&adsp_region>; 259 260 qcom,smem-states = <&adsp_smp2p_out 0>; 261 qcom,smem-state-names = "stop"; 262 }; 263 264 smem { 265 compatible = "qcom,smem"; 266 267 memory-region = <&smem_region>; 268 qcom,rpm-msg-ram = <&rpm_msg_ram>; 269 270 hwlocks = <&tcsr_mutex 3>; 271 }; 272 273 smp2p-adsp { 274 compatible = "qcom,smp2p"; 275 qcom,smem = <443>, <429>; 276 277 interrupt-parent = <&intc>; 278 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 279 280 qcom,ipc = <&apcs 8 10>; 281 282 qcom,local-pid = <0>; 283 qcom,remote-pid = <2>; 284 285 adsp_smp2p_out: master-kernel { 286 qcom,entry-name = "master-kernel"; 287 #qcom,smem-state-cells = <1>; 288 }; 289 290 adsp_smp2p_in: slave-kernel { 291 qcom,entry-name = "slave-kernel"; 292 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 }; 296 }; 297 298 smp2p-modem { 299 compatible = "qcom,smp2p"; 300 qcom,smem = <435>, <428>; 301 302 interrupt-parent = <&intc>; 303 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 304 305 qcom,ipc = <&apcs 8 14>; 306 307 qcom,local-pid = <0>; 308 qcom,remote-pid = <1>; 309 310 modem_smp2p_out: master-kernel { 311 qcom,entry-name = "master-kernel"; 312 #qcom,smem-state-cells = <1>; 313 }; 314 315 modem_smp2p_in: slave-kernel { 316 qcom,entry-name = "slave-kernel"; 317 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 }; 321 }; 322 323 smp2p-wcnss { 324 compatible = "qcom,smp2p"; 325 qcom,smem = <451>, <431>; 326 327 interrupt-parent = <&intc>; 328 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 329 330 qcom,ipc = <&apcs 8 18>; 331 332 qcom,local-pid = <0>; 333 qcom,remote-pid = <4>; 334 335 wcnss_smp2p_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 338 #qcom,smem-state-cells = <1>; 339 }; 340 341 wcnss_smp2p_in: slave-kernel { 342 qcom,entry-name = "slave-kernel"; 343 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 }; 348 349 smsm { 350 compatible = "qcom,smsm"; 351 352 #address-cells = <1>; 353 #size-cells = <0>; 354 355 qcom,ipc-1 = <&apcs 8 13>; 356 qcom,ipc-2 = <&apcs 8 9>; 357 qcom,ipc-3 = <&apcs 8 19>; 358 359 apps_smsm: apps@0 { 360 reg = <0>; 361 362 #qcom,smem-state-cells = <1>; 363 }; 364 365 modem_smsm: modem@1 { 366 reg = <1>; 367 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 368 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 }; 372 373 adsp_smsm: adsp@2 { 374 reg = <2>; 375 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>; 376 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 }; 380 381 wcnss_smsm: wcnss@7 { 382 reg = <7>; 383 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 384 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 }; 388 }; 389 390 firmware { 391 scm { 392 compatible = "qcom,scm"; 393 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 394 clock-names = "core", "bus", "iface"; 395 }; 396 }; 397 398 soc: soc { 399 #address-cells = <1>; 400 #size-cells = <1>; 401 ranges; 402 compatible = "simple-bus"; 403 404 intc: interrupt-controller@f9000000 { 405 compatible = "qcom,msm-qgic2"; 406 interrupt-controller; 407 #interrupt-cells = <3>; 408 reg = <0xf9000000 0x1000>, 409 <0xf9002000 0x1000>; 410 }; 411 412 apcs: syscon@f9011000 { 413 compatible = "syscon"; 414 reg = <0xf9011000 0x1000>; 415 }; 416 417 qfprom: qfprom@fc4bc000 { 418 #address-cells = <1>; 419 #size-cells = <1>; 420 compatible = "qcom,qfprom"; 421 reg = <0xfc4bc000 0x1000>; 422 tsens_calib: calib@d0 { 423 reg = <0xd0 0x18>; 424 }; 425 tsens_backup: backup@440 { 426 reg = <0x440 0x10>; 427 }; 428 }; 429 430 tsens: thermal-sensor@fc4a8000 { 431 compatible = "qcom,msm8974-tsens"; 432 reg = <0xfc4a8000 0x2000>; 433 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 434 nvmem-cell-names = "calib", "calib_backup"; 435 #thermal-sensor-cells = <1>; 436 }; 437 438 timer@f9020000 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges; 442 compatible = "arm,armv7-timer-mem"; 443 reg = <0xf9020000 0x1000>; 444 clock-frequency = <19200000>; 445 446 frame@f9021000 { 447 frame-number = <0>; 448 interrupts = <0 8 0x4>, 449 <0 7 0x4>; 450 reg = <0xf9021000 0x1000>, 451 <0xf9022000 0x1000>; 452 }; 453 454 frame@f9023000 { 455 frame-number = <1>; 456 interrupts = <0 9 0x4>; 457 reg = <0xf9023000 0x1000>; 458 status = "disabled"; 459 }; 460 461 frame@f9024000 { 462 frame-number = <2>; 463 interrupts = <0 10 0x4>; 464 reg = <0xf9024000 0x1000>; 465 status = "disabled"; 466 }; 467 468 frame@f9025000 { 469 frame-number = <3>; 470 interrupts = <0 11 0x4>; 471 reg = <0xf9025000 0x1000>; 472 status = "disabled"; 473 }; 474 475 frame@f9026000 { 476 frame-number = <4>; 477 interrupts = <0 12 0x4>; 478 reg = <0xf9026000 0x1000>; 479 status = "disabled"; 480 }; 481 482 frame@f9027000 { 483 frame-number = <5>; 484 interrupts = <0 13 0x4>; 485 reg = <0xf9027000 0x1000>; 486 status = "disabled"; 487 }; 488 489 frame@f9028000 { 490 frame-number = <6>; 491 interrupts = <0 14 0x4>; 492 reg = <0xf9028000 0x1000>; 493 status = "disabled"; 494 }; 495 }; 496 497 saw0: power-controller@f9089000 { 498 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 499 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 500 }; 501 502 saw1: power-controller@f9099000 { 503 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 504 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 505 }; 506 507 saw2: power-controller@f90a9000 { 508 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 509 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 510 }; 511 512 saw3: power-controller@f90b9000 { 513 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 514 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 515 }; 516 517 saw_l2: power-controller@f9012000 { 518 compatible = "qcom,saw2"; 519 reg = <0xf9012000 0x1000>; 520 regulator; 521 }; 522 523 acc0: clock-controller@f9088000 { 524 compatible = "qcom,kpss-acc-v2"; 525 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 526 }; 527 528 acc1: clock-controller@f9098000 { 529 compatible = "qcom,kpss-acc-v2"; 530 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 531 }; 532 533 acc2: clock-controller@f90a8000 { 534 compatible = "qcom,kpss-acc-v2"; 535 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 536 }; 537 538 acc3: clock-controller@f90b8000 { 539 compatible = "qcom,kpss-acc-v2"; 540 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 541 }; 542 543 restart@fc4ab000 { 544 compatible = "qcom,pshold"; 545 reg = <0xfc4ab000 0x4>; 546 }; 547 548 gcc: clock-controller@fc400000 { 549 compatible = "qcom,gcc-msm8974"; 550 #clock-cells = <1>; 551 #reset-cells = <1>; 552 #power-domain-cells = <1>; 553 reg = <0xfc400000 0x4000>; 554 }; 555 556 tcsr: syscon@fd4a0000 { 557 compatible = "syscon"; 558 reg = <0xfd4a0000 0x10000>; 559 }; 560 561 tcsr_mutex_block: syscon@fd484000 { 562 compatible = "syscon"; 563 reg = <0xfd484000 0x2000>; 564 }; 565 566 mmcc: clock-controller@fd8c0000 { 567 compatible = "qcom,mmcc-msm8974"; 568 #clock-cells = <1>; 569 #reset-cells = <1>; 570 #power-domain-cells = <1>; 571 reg = <0xfd8c0000 0x6000>; 572 }; 573 574 tcsr_mutex: tcsr-mutex { 575 compatible = "qcom,tcsr-mutex"; 576 syscon = <&tcsr_mutex_block 0 0x80>; 577 578 #hwlock-cells = <1>; 579 }; 580 581 rpm_msg_ram: memory@fc428000 { 582 compatible = "qcom,rpm-msg-ram"; 583 reg = <0xfc428000 0x4000>; 584 }; 585 586 blsp1_uart1: serial@f991d000 { 587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 588 reg = <0xf991d000 0x1000>; 589 interrupts = <0 107 0x0>; 590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 591 clock-names = "core", "iface"; 592 status = "disabled"; 593 }; 594 595 blsp1_uart2: serial@f991e000 { 596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 597 reg = <0xf991e000 0x1000>; 598 interrupts = <0 108 0x0>; 599 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 600 clock-names = "core", "iface"; 601 status = "disabled"; 602 }; 603 604 sdhci@f9824900 { 605 compatible = "qcom,sdhci-msm-v4"; 606 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 607 reg-names = "hc_mem", "core_mem"; 608 interrupts = <0 123 0>, <0 138 0>; 609 interrupt-names = "hc_irq", "pwr_irq"; 610 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 611 <&gcc GCC_SDCC1_AHB_CLK>, 612 <&xo_board>; 613 clock-names = "core", "iface", "xo"; 614 status = "disabled"; 615 }; 616 617 sdhci@f98a4900 { 618 compatible = "qcom,sdhci-msm-v4"; 619 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 620 reg-names = "hc_mem", "core_mem"; 621 interrupts = <0 125 0>, <0 221 0>; 622 interrupt-names = "hc_irq", "pwr_irq"; 623 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 624 <&gcc GCC_SDCC2_AHB_CLK>, 625 <&xo_board>; 626 clock-names = "core", "iface", "xo"; 627 status = "disabled"; 628 }; 629 630 otg: usb@f9a55000 { 631 compatible = "qcom,ci-hdrc"; 632 reg = <0xf9a55000 0x200>, 633 <0xf9a55200 0x200>; 634 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 636 <&gcc GCC_USB_HS_SYSTEM_CLK>; 637 clock-names = "iface", "core"; 638 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 639 assigned-clock-rates = <75000000>; 640 resets = <&gcc GCC_USB_HS_BCR>; 641 reset-names = "core"; 642 phy_type = "ulpi"; 643 dr_mode = "otg"; 644 ahb-burst-config = <0>; 645 phy-names = "usb-phy"; 646 status = "disabled"; 647 #reset-cells = <1>; 648 649 ulpi { 650 usb_hs1_phy: phy@a { 651 compatible = "qcom,usb-hs-phy-msm8974", 652 "qcom,usb-hs-phy"; 653 #phy-cells = <0>; 654 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 655 clock-names = "ref", "sleep"; 656 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 657 reset-names = "phy", "por"; 658 status = "disabled"; 659 }; 660 661 usb_hs2_phy: phy@b { 662 compatible = "qcom,usb-hs-phy-msm8974", 663 "qcom,usb-hs-phy"; 664 #phy-cells = <0>; 665 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 666 clock-names = "ref", "sleep"; 667 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; 668 reset-names = "phy", "por"; 669 status = "disabled"; 670 }; 671 }; 672 }; 673 674 rng@f9bff000 { 675 compatible = "qcom,prng"; 676 reg = <0xf9bff000 0x200>; 677 clocks = <&gcc GCC_PRNG_AHB_CLK>; 678 clock-names = "core"; 679 }; 680 681 msmgpio: pinctrl@fd510000 { 682 compatible = "qcom,msm8974-pinctrl"; 683 reg = <0xfd510000 0x4000>; 684 gpio-controller; 685 #gpio-cells = <2>; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 interrupts = <0 208 0>; 689 }; 690 691 i2c@f9924000 { 692 status = "disabled"; 693 compatible = "qcom,i2c-qup-v2.1.1"; 694 reg = <0xf9924000 0x1000>; 695 interrupts = <0 96 IRQ_TYPE_NONE>; 696 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 697 clock-names = "core", "iface"; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 702 blsp_i2c8: i2c@f9964000 { 703 status = "disabled"; 704 compatible = "qcom,i2c-qup-v2.1.1"; 705 reg = <0xf9964000 0x1000>; 706 interrupts = <0 102 IRQ_TYPE_NONE>; 707 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 708 clock-names = "core", "iface"; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 }; 712 713 blsp_i2c11: i2c@f9967000 { 714 status = "disabled"; 715 compatible = "qcom,i2c-qup-v2.1.1"; 716 reg = <0xf9967000 0x1000>; 717 interrupts = <0 105 IRQ_TYPE_NONE>; 718 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 719 clock-names = "core", "iface"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 723 dma-names = "tx", "rx"; 724 }; 725 726 spmi_bus: spmi@fc4cf000 { 727 compatible = "qcom,spmi-pmic-arb"; 728 reg-names = "core", "intr", "cnfg"; 729 reg = <0xfc4cf000 0x1000>, 730 <0xfc4cb000 0x1000>, 731 <0xfc4ca000 0x1000>; 732 interrupt-names = "periph_irq"; 733 interrupts = <0 190 0>; 734 qcom,ee = <0>; 735 qcom,channel = <0>; 736 #address-cells = <2>; 737 #size-cells = <0>; 738 interrupt-controller; 739 #interrupt-cells = <4>; 740 }; 741 742 blsp2_dma: dma-controller@f9944000 { 743 compatible = "qcom,bam-v1.4.0"; 744 reg = <0xf9944000 0x19000>; 745 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 747 clock-names = "bam_clk"; 748 #dma-cells = <1>; 749 qcom,ee = <0>; 750 }; 751 752 etr@fc322000 { 753 compatible = "arm,coresight-tmc", "arm,primecell"; 754 reg = <0xfc322000 0x1000>; 755 756 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 757 clock-names = "apb_pclk", "atclk"; 758 759 port { 760 etr_in: endpoint { 761 slave-mode; 762 remote-endpoint = <&replicator_out0>; 763 }; 764 }; 765 }; 766 767 tpiu@fc318000 { 768 compatible = "arm,coresight-tpiu", "arm,primecell"; 769 reg = <0xfc318000 0x1000>; 770 771 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 772 clock-names = "apb_pclk", "atclk"; 773 774 port { 775 tpiu_in: endpoint { 776 slave-mode; 777 remote-endpoint = <&replicator_out1>; 778 }; 779 }; 780 }; 781 782 replicator@fc31c000 { 783 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 784 reg = <0xfc31c000 0x1000>; 785 786 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 787 clock-names = "apb_pclk", "atclk"; 788 789 ports { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 port@0 { 794 reg = <0>; 795 replicator_out0: endpoint { 796 remote-endpoint = <&etr_in>; 797 }; 798 }; 799 port@1 { 800 reg = <1>; 801 replicator_out1: endpoint { 802 remote-endpoint = <&tpiu_in>; 803 }; 804 }; 805 port@2 { 806 reg = <0>; 807 replicator_in: endpoint { 808 slave-mode; 809 remote-endpoint = <&etf_out>; 810 }; 811 }; 812 }; 813 }; 814 815 etf@fc307000 { 816 compatible = "arm,coresight-tmc", "arm,primecell"; 817 reg = <0xfc307000 0x1000>; 818 819 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 820 clock-names = "apb_pclk", "atclk"; 821 822 ports { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 826 port@0 { 827 reg = <0>; 828 etf_out: endpoint { 829 remote-endpoint = <&replicator_in>; 830 }; 831 }; 832 port@1 { 833 reg = <0>; 834 etf_in: endpoint { 835 slave-mode; 836 remote-endpoint = <&merger_out>; 837 }; 838 }; 839 }; 840 }; 841 842 funnel@fc31b000 { 843 compatible = "arm,coresight-funnel", "arm,primecell"; 844 reg = <0xfc31b000 0x1000>; 845 846 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 847 clock-names = "apb_pclk", "atclk"; 848 849 ports { 850 #address-cells = <1>; 851 #size-cells = <0>; 852 853 /* 854 * Not described input ports: 855 * 0 - connected trought funnel to Audio, Modem and 856 * Resource and Power Manager CPU's 857 * 2...7 - not-connected 858 */ 859 port@1 { 860 reg = <1>; 861 merger_in1: endpoint { 862 slave-mode; 863 remote-endpoint = <&funnel1_out>; 864 }; 865 }; 866 port@8 { 867 reg = <0>; 868 merger_out: endpoint { 869 remote-endpoint = <&etf_in>; 870 }; 871 }; 872 }; 873 }; 874 875 funnel@fc31a000 { 876 compatible = "arm,coresight-funnel", "arm,primecell"; 877 reg = <0xfc31a000 0x1000>; 878 879 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 880 clock-names = "apb_pclk", "atclk"; 881 882 ports { 883 #address-cells = <1>; 884 #size-cells = <0>; 885 886 /* 887 * Not described input ports: 888 * 0 - not-connected 889 * 1 - connected trought funnel to Multimedia CPU 890 * 2 - connected to Wireless CPU 891 * 3 - not-connected 892 * 4 - not-connected 893 * 6 - not-connected 894 * 7 - connected to STM 895 */ 896 port@5 { 897 reg = <5>; 898 funnel1_in5: endpoint { 899 slave-mode; 900 remote-endpoint = <&kpss_out>; 901 }; 902 }; 903 port@8 { 904 reg = <0>; 905 funnel1_out: endpoint { 906 remote-endpoint = <&merger_in1>; 907 }; 908 }; 909 }; 910 }; 911 912 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ 913 compatible = "arm,coresight-funnel", "arm,primecell"; 914 reg = <0xfc345000 0x1000>; 915 916 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 917 clock-names = "apb_pclk", "atclk"; 918 919 ports { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 port@0 { 924 reg = <0>; 925 kpss_in0: endpoint { 926 slave-mode; 927 remote-endpoint = <&etm0_out>; 928 }; 929 }; 930 port@1 { 931 reg = <1>; 932 kpss_in1: endpoint { 933 slave-mode; 934 remote-endpoint = <&etm1_out>; 935 }; 936 }; 937 port@2 { 938 reg = <2>; 939 kpss_in2: endpoint { 940 slave-mode; 941 remote-endpoint = <&etm2_out>; 942 }; 943 }; 944 port@3 { 945 reg = <3>; 946 kpss_in3: endpoint { 947 slave-mode; 948 remote-endpoint = <&etm3_out>; 949 }; 950 }; 951 port@8 { 952 reg = <0>; 953 kpss_out: endpoint { 954 remote-endpoint = <&funnel1_in5>; 955 }; 956 }; 957 }; 958 }; 959 960 etm@fc33c000 { 961 compatible = "arm,coresight-etm4x", "arm,primecell"; 962 reg = <0xfc33c000 0x1000>; 963 964 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 965 clock-names = "apb_pclk", "atclk"; 966 967 cpu = <&CPU0>; 968 969 port { 970 etm0_out: endpoint { 971 remote-endpoint = <&kpss_in0>; 972 }; 973 }; 974 }; 975 976 etm@fc33d000 { 977 compatible = "arm,coresight-etm4x", "arm,primecell"; 978 reg = <0xfc33d000 0x1000>; 979 980 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 981 clock-names = "apb_pclk", "atclk"; 982 983 cpu = <&CPU1>; 984 985 port { 986 etm1_out: endpoint { 987 remote-endpoint = <&kpss_in1>; 988 }; 989 }; 990 }; 991 992 etm@fc33e000 { 993 compatible = "arm,coresight-etm4x", "arm,primecell"; 994 reg = <0xfc33e000 0x1000>; 995 996 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 997 clock-names = "apb_pclk", "atclk"; 998 999 cpu = <&CPU2>; 1000 1001 port { 1002 etm2_out: endpoint { 1003 remote-endpoint = <&kpss_in2>; 1004 }; 1005 }; 1006 }; 1007 1008 etm@fc33f000 { 1009 compatible = "arm,coresight-etm4x", "arm,primecell"; 1010 reg = <0xfc33f000 0x1000>; 1011 1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1013 clock-names = "apb_pclk", "atclk"; 1014 1015 cpu = <&CPU3>; 1016 1017 port { 1018 etm3_out: endpoint { 1019 remote-endpoint = <&kpss_in3>; 1020 }; 1021 }; 1022 }; 1023 }; 1024 1025 smd { 1026 compatible = "qcom,smd"; 1027 1028 adsp { 1029 interrupts = <0 156 IRQ_TYPE_EDGE_RISING>; 1030 1031 qcom,ipc = <&apcs 8 8>; 1032 qcom,smd-edge = <1>; 1033 }; 1034 1035 modem { 1036 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1037 1038 qcom,ipc = <&apcs 8 12>; 1039 qcom,smd-edge = <0>; 1040 }; 1041 1042 rpm { 1043 interrupts = <0 168 1>; 1044 qcom,ipc = <&apcs 8 0>; 1045 qcom,smd-edge = <15>; 1046 1047 rpm_requests { 1048 compatible = "qcom,rpm-msm8974"; 1049 qcom,smd-channels = "rpm_requests"; 1050 1051 rpmcc: clock-controller { 1052 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 1053 #clock-cells = <1>; 1054 }; 1055 1056 pm8841-regulators { 1057 compatible = "qcom,rpm-pm8841-regulators"; 1058 1059 pm8841_s1: s1 {}; 1060 pm8841_s2: s2 {}; 1061 pm8841_s3: s3 {}; 1062 pm8841_s4: s4 {}; 1063 pm8841_s5: s5 {}; 1064 pm8841_s6: s6 {}; 1065 pm8841_s7: s7 {}; 1066 pm8841_s8: s8 {}; 1067 }; 1068 1069 pm8941-regulators { 1070 compatible = "qcom,rpm-pm8941-regulators"; 1071 1072 pm8941_s1: s1 {}; 1073 pm8941_s2: s2 {}; 1074 pm8941_s3: s3 {}; 1075 1076 pm8941_l1: l1 {}; 1077 pm8941_l2: l2 {}; 1078 pm8941_l3: l3 {}; 1079 pm8941_l4: l4 {}; 1080 pm8941_l5: l5 {}; 1081 pm8941_l6: l6 {}; 1082 pm8941_l7: l7 {}; 1083 pm8941_l8: l8 {}; 1084 pm8941_l9: l9 {}; 1085 pm8941_l10: l10 {}; 1086 pm8941_l11: l11 {}; 1087 pm8941_l12: l12 {}; 1088 pm8941_l13: l13 {}; 1089 pm8941_l14: l14 {}; 1090 pm8941_l15: l15 {}; 1091 pm8941_l16: l16 {}; 1092 pm8941_l17: l17 {}; 1093 pm8941_l18: l18 {}; 1094 pm8941_l19: l19 {}; 1095 pm8941_l20: l20 {}; 1096 pm8941_l21: l21 {}; 1097 pm8941_l22: l22 {}; 1098 pm8941_l23: l23 {}; 1099 pm8941_l24: l24 {}; 1100 1101 pm8941_lvs1: lvs1 {}; 1102 pm8941_lvs2: lvs2 {}; 1103 pm8941_lvs3: lvs3 {}; 1104 }; 1105 }; 1106 }; 1107 }; 1108 1109 vreg_boost: vreg-boost { 1110 compatible = "regulator-fixed"; 1111 1112 regulator-name = "vreg-boost"; 1113 regulator-min-microvolt = <3150000>; 1114 regulator-max-microvolt = <3150000>; 1115 1116 regulator-always-on; 1117 regulator-boot-on; 1118 1119 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 1120 enable-active-high; 1121 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&boost_bypass_n_pin>; 1124 }; 1125 vreg_vph_pwr: vreg-vph-pwr { 1126 compatible = "regulator-fixed"; 1127 regulator-name = "vph-pwr"; 1128 1129 regulator-min-microvolt = <3600000>; 1130 regulator-max-microvolt = <3600000>; 1131 1132 regulator-always-on; 1133 }; 1134}; 1135