1/* 2 * Device Tree Source for the r8a7793 SoC 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/clock/r8a7793-clock.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/power/r8a7793-sysc.h> 15 16/ { 17 compatible = "renesas,r8a7793"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 spi0 = &qspi; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 enable-method = "renesas,apmu"; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a15"; 43 reg = <0>; 44 clock-frequency = <1500000000>; 45 voltage-tolerance = <1>; /* 1% */ 46 clocks = <&cpg_clocks R8A7793_CLK_Z>; 47 clock-latency = <300000>; /* 300 us */ 48 power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 49 50 /* kHz - uV - OPPs unknown yet */ 51 operating-points = <1500000 1000000>, 52 <1312500 1000000>, 53 <1125000 1000000>, 54 < 937500 1000000>, 55 < 750000 1000000>, 56 < 375000 1000000>; 57 next-level-cache = <&L2_CA15>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <1>; 64 clock-frequency = <1500000000>; 65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 66 }; 67 68 L2_CA15: cache-controller-0 { 69 compatible = "cache"; 70 power-domains = <&sysc R8A7793_PD_CA15_SCU>; 71 cache-unified; 72 cache-level = <2>; 73 }; 74 }; 75 76 apmu@e6152000 { 77 compatible = "renesas,r8a7793-apmu", "renesas,apmu"; 78 reg = <0 0xe6152000 0 0x188>; 79 cpus = <&cpu0 &cpu1>; 80 }; 81 82 thermal-zones { 83 cpu_thermal: cpu-thermal { 84 polling-delay-passive = <0>; 85 polling-delay = <0>; 86 87 thermal-sensors = <&thermal>; 88 89 trips { 90 cpu-crit { 91 temperature = <95000>; 92 hysteresis = <0>; 93 type = "critical"; 94 }; 95 }; 96 cooling-maps { 97 }; 98 }; 99 }; 100 101 gic: interrupt-controller@f1001000 { 102 compatible = "arm,gic-400"; 103 #interrupt-cells = <3>; 104 #address-cells = <0>; 105 interrupt-controller; 106 reg = <0 0xf1001000 0 0x1000>, 107 <0 0xf1002000 0 0x2000>, 108 <0 0xf1004000 0 0x2000>, 109 <0 0xf1006000 0 0x2000>; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 111 clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>; 112 clock-names = "clk"; 113 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 114 }; 115 116 gpio0: gpio@e6050000 { 117 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 118 reg = <0 0xe6050000 0 0x50>; 119 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 120 #gpio-cells = <2>; 121 gpio-controller; 122 gpio-ranges = <&pfc 0 0 32>; 123 #interrupt-cells = <2>; 124 interrupt-controller; 125 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; 126 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 127 }; 128 129 gpio1: gpio@e6051000 { 130 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 131 reg = <0 0xe6051000 0 0x50>; 132 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 133 #gpio-cells = <2>; 134 gpio-controller; 135 gpio-ranges = <&pfc 0 32 26>; 136 #interrupt-cells = <2>; 137 interrupt-controller; 138 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; 139 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 140 }; 141 142 gpio2: gpio@e6052000 { 143 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 144 reg = <0 0xe6052000 0 0x50>; 145 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 146 #gpio-cells = <2>; 147 gpio-controller; 148 gpio-ranges = <&pfc 0 64 32>; 149 #interrupt-cells = <2>; 150 interrupt-controller; 151 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; 152 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 153 }; 154 155 gpio3: gpio@e6053000 { 156 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 157 reg = <0 0xe6053000 0 0x50>; 158 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 159 #gpio-cells = <2>; 160 gpio-controller; 161 gpio-ranges = <&pfc 0 96 32>; 162 #interrupt-cells = <2>; 163 interrupt-controller; 164 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; 165 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 166 }; 167 168 gpio4: gpio@e6054000 { 169 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 170 reg = <0 0xe6054000 0 0x50>; 171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 172 #gpio-cells = <2>; 173 gpio-controller; 174 gpio-ranges = <&pfc 0 128 32>; 175 #interrupt-cells = <2>; 176 interrupt-controller; 177 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; 178 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 179 }; 180 181 gpio5: gpio@e6055000 { 182 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 183 reg = <0 0xe6055000 0 0x50>; 184 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 185 #gpio-cells = <2>; 186 gpio-controller; 187 gpio-ranges = <&pfc 0 160 32>; 188 #interrupt-cells = <2>; 189 interrupt-controller; 190 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; 191 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 192 }; 193 194 gpio6: gpio@e6055400 { 195 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 196 reg = <0 0xe6055400 0 0x50>; 197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 192 32>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; 204 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 205 }; 206 207 gpio7: gpio@e6055800 { 208 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 209 reg = <0 0xe6055800 0 0x50>; 210 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 211 #gpio-cells = <2>; 212 gpio-controller; 213 gpio-ranges = <&pfc 0 224 26>; 214 #interrupt-cells = <2>; 215 interrupt-controller; 216 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; 217 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 218 }; 219 220 thermal: thermal@e61f0000 { 221 compatible = "renesas,thermal-r8a7793", 222 "renesas,rcar-gen2-thermal", 223 "renesas,rcar-thermal"; 224 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 225 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; 227 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 228 #thermal-sensor-cells = <0>; 229 }; 230 231 timer { 232 compatible = "arm,armv7-timer"; 233 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 234 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 237 }; 238 239 cmt0: timer@ffca0000 { 240 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; 241 reg = <0 0xffca0000 0 0x1004>; 242 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&mstp1_clks R8A7793_CLK_CMT0>; 245 clock-names = "fck"; 246 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 247 248 renesas,channels-mask = <0x60>; 249 250 status = "disabled"; 251 }; 252 253 cmt1: timer@e6130000 { 254 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; 255 reg = <0 0xe6130000 0 0x1004>; 256 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&mstp3_clks R8A7793_CLK_CMT1>; 265 clock-names = "fck"; 266 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 267 268 renesas,channels-mask = <0xff>; 269 270 status = "disabled"; 271 }; 272 273 irqc0: interrupt-controller@e61c0000 { 274 compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 275 #interrupt-cells = <2>; 276 interrupt-controller; 277 reg = <0 0xe61c0000 0 0x200>; 278 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&mstp4_clks R8A7793_CLK_IRQC>; 289 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 290 }; 291 292 dmac0: dma-controller@e6700000 { 293 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; 294 reg = <0 0xe6700000 0 0x20000>; 295 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 311 interrupt-names = "error", 312 "ch0", "ch1", "ch2", "ch3", 313 "ch4", "ch5", "ch6", "ch7", 314 "ch8", "ch9", "ch10", "ch11", 315 "ch12", "ch13", "ch14"; 316 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; 317 clock-names = "fck"; 318 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 319 #dma-cells = <1>; 320 dma-channels = <15>; 321 }; 322 323 dmac1: dma-controller@e6720000 { 324 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; 325 reg = <0 0xe6720000 0 0x20000>; 326 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "error", 343 "ch0", "ch1", "ch2", "ch3", 344 "ch4", "ch5", "ch6", "ch7", 345 "ch8", "ch9", "ch10", "ch11", 346 "ch12", "ch13", "ch14"; 347 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; 348 clock-names = "fck"; 349 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 350 #dma-cells = <1>; 351 dma-channels = <15>; 352 }; 353 354 audma0: dma-controller@ec700000 { 355 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; 356 reg = <0 0xec700000 0 0x10000>; 357 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 358 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 359 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 360 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 361 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "error", 372 "ch0", "ch1", "ch2", "ch3", 373 "ch4", "ch5", "ch6", "ch7", 374 "ch8", "ch9", "ch10", "ch11", 375 "ch12"; 376 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; 377 clock-names = "fck"; 378 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 379 #dma-cells = <1>; 380 dma-channels = <13>; 381 }; 382 383 audma1: dma-controller@ec720000 { 384 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; 385 reg = <0 0xec720000 0 0x10000>; 386 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 387 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 388 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 389 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 390 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 391 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 392 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 394 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 395 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 400 interrupt-names = "error", 401 "ch0", "ch1", "ch2", "ch3", 402 "ch4", "ch5", "ch6", "ch7", 403 "ch8", "ch9", "ch10", "ch11", 404 "ch12"; 405 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; 406 clock-names = "fck"; 407 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 408 #dma-cells = <1>; 409 dma-channels = <13>; 410 }; 411 412 /* The memory map in the User's Manual maps the cores to bus numbers */ 413 i2c0: i2c@e6508000 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 417 reg = <0 0xe6508000 0 0x40>; 418 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&mstp9_clks R8A7793_CLK_I2C0>; 420 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 421 i2c-scl-internal-delay-ns = <6>; 422 status = "disabled"; 423 }; 424 425 i2c1: i2c@e6518000 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 429 reg = <0 0xe6518000 0 0x40>; 430 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&mstp9_clks R8A7793_CLK_I2C1>; 432 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 433 i2c-scl-internal-delay-ns = <6>; 434 status = "disabled"; 435 }; 436 437 i2c2: i2c@e6530000 { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 441 reg = <0 0xe6530000 0 0x40>; 442 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&mstp9_clks R8A7793_CLK_I2C2>; 444 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 445 i2c-scl-internal-delay-ns = <6>; 446 status = "disabled"; 447 }; 448 449 i2c3: i2c@e6540000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 453 reg = <0 0xe6540000 0 0x40>; 454 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&mstp9_clks R8A7793_CLK_I2C3>; 456 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 457 i2c-scl-internal-delay-ns = <6>; 458 status = "disabled"; 459 }; 460 461 i2c4: i2c@e6520000 { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 465 reg = <0 0xe6520000 0 0x40>; 466 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&mstp9_clks R8A7793_CLK_I2C4>; 468 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 469 i2c-scl-internal-delay-ns = <6>; 470 status = "disabled"; 471 }; 472 473 i2c5: i2c@e6528000 { 474 /* doesn't need pinmux */ 475 #address-cells = <1>; 476 #size-cells = <0>; 477 compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; 478 reg = <0 0xe6528000 0 0x40>; 479 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&mstp9_clks R8A7793_CLK_I2C5>; 481 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 482 i2c-scl-internal-delay-ns = <110>; 483 status = "disabled"; 484 }; 485 486 i2c6: i2c@e60b0000 { 487 /* doesn't need pinmux */ 488 #address-cells = <1>; 489 #size-cells = <0>; 490 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", 491 "renesas,rmobile-iic"; 492 reg = <0 0xe60b0000 0 0x425>; 493 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; 495 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 496 <&dmac1 0x77>, <&dmac1 0x78>; 497 dma-names = "tx", "rx", "tx", "rx"; 498 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 499 status = "disabled"; 500 }; 501 502 i2c7: i2c@e6500000 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", 506 "renesas,rmobile-iic"; 507 reg = <0 0xe6500000 0 0x425>; 508 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&mstp3_clks R8A7793_CLK_IIC0>; 510 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 511 <&dmac1 0x61>, <&dmac1 0x62>; 512 dma-names = "tx", "rx", "tx", "rx"; 513 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 514 status = "disabled"; 515 }; 516 517 i2c8: i2c@e6510000 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic", 521 "renesas,rmobile-iic"; 522 reg = <0 0xe6510000 0 0x425>; 523 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&mstp3_clks R8A7793_CLK_IIC1>; 525 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 526 <&dmac1 0x65>, <&dmac1 0x66>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 529 status = "disabled"; 530 }; 531 532 pfc: pin-controller@e6060000 { 533 compatible = "renesas,pfc-r8a7793"; 534 reg = <0 0xe6060000 0 0x250>; 535 }; 536 537 sdhi0: sd@ee100000 { 538 compatible = "renesas,sdhi-r8a7793"; 539 reg = <0 0xee100000 0 0x328>; 540 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; 542 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 543 <&dmac1 0xcd>, <&dmac1 0xce>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 max-frequency = <195000000>; 546 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 547 status = "disabled"; 548 }; 549 550 sdhi1: sd@ee140000 { 551 compatible = "renesas,sdhi-r8a7793"; 552 reg = <0 0xee140000 0 0x100>; 553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; 555 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 556 <&dmac1 0xc1>, <&dmac1 0xc2>; 557 dma-names = "tx", "rx", "tx", "rx"; 558 max-frequency = <97500000>; 559 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 560 status = "disabled"; 561 }; 562 563 sdhi2: sd@ee160000 { 564 compatible = "renesas,sdhi-r8a7793"; 565 reg = <0 0xee160000 0 0x100>; 566 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; 568 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 569 <&dmac1 0xd3>, <&dmac1 0xd4>; 570 dma-names = "tx", "rx", "tx", "rx"; 571 max-frequency = <97500000>; 572 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 573 status = "disabled"; 574 }; 575 576 mmcif0: mmc@ee200000 { 577 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; 578 reg = <0 0xee200000 0 0x80>; 579 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; 581 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 582 <&dmac1 0xd1>, <&dmac1 0xd2>; 583 dma-names = "tx", "rx", "tx", "rx"; 584 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 585 reg-io-width = <4>; 586 status = "disabled"; 587 max-frequency = <97500000>; 588 }; 589 590 scifa0: serial@e6c40000 { 591 compatible = "renesas,scifa-r8a7793", 592 "renesas,rcar-gen2-scifa", "renesas,scifa"; 593 reg = <0 0xe6c40000 0 64>; 594 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; 596 clock-names = "fck"; 597 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 598 <&dmac1 0x21>, <&dmac1 0x22>; 599 dma-names = "tx", "rx", "tx", "rx"; 600 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 601 status = "disabled"; 602 }; 603 604 scifa1: serial@e6c50000 { 605 compatible = "renesas,scifa-r8a7793", 606 "renesas,rcar-gen2-scifa", "renesas,scifa"; 607 reg = <0 0xe6c50000 0 64>; 608 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; 610 clock-names = "fck"; 611 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 612 <&dmac1 0x25>, <&dmac1 0x26>; 613 dma-names = "tx", "rx", "tx", "rx"; 614 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 615 status = "disabled"; 616 }; 617 618 scifa2: serial@e6c60000 { 619 compatible = "renesas,scifa-r8a7793", 620 "renesas,rcar-gen2-scifa", "renesas,scifa"; 621 reg = <0 0xe6c60000 0 64>; 622 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; 624 clock-names = "fck"; 625 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 626 <&dmac1 0x27>, <&dmac1 0x28>; 627 dma-names = "tx", "rx", "tx", "rx"; 628 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 629 status = "disabled"; 630 }; 631 632 scifa3: serial@e6c70000 { 633 compatible = "renesas,scifa-r8a7793", 634 "renesas,rcar-gen2-scifa", "renesas,scifa"; 635 reg = <0 0xe6c70000 0 64>; 636 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; 638 clock-names = "fck"; 639 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 640 <&dmac1 0x1b>, <&dmac1 0x1c>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 643 status = "disabled"; 644 }; 645 646 scifa4: serial@e6c78000 { 647 compatible = "renesas,scifa-r8a7793", 648 "renesas,rcar-gen2-scifa", "renesas,scifa"; 649 reg = <0 0xe6c78000 0 64>; 650 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; 652 clock-names = "fck"; 653 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 654 <&dmac1 0x1f>, <&dmac1 0x20>; 655 dma-names = "tx", "rx", "tx", "rx"; 656 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 657 status = "disabled"; 658 }; 659 660 scifa5: serial@e6c80000 { 661 compatible = "renesas,scifa-r8a7793", 662 "renesas,rcar-gen2-scifa", "renesas,scifa"; 663 reg = <0 0xe6c80000 0 64>; 664 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; 666 clock-names = "fck"; 667 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 668 <&dmac1 0x23>, <&dmac1 0x24>; 669 dma-names = "tx", "rx", "tx", "rx"; 670 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 671 status = "disabled"; 672 }; 673 674 scifb0: serial@e6c20000 { 675 compatible = "renesas,scifb-r8a7793", 676 "renesas,rcar-gen2-scifb", "renesas,scifb"; 677 reg = <0 0xe6c20000 0 0x100>; 678 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; 680 clock-names = "fck"; 681 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 682 <&dmac1 0x3d>, <&dmac1 0x3e>; 683 dma-names = "tx", "rx", "tx", "rx"; 684 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 685 status = "disabled"; 686 }; 687 688 scifb1: serial@e6c30000 { 689 compatible = "renesas,scifb-r8a7793", 690 "renesas,rcar-gen2-scifb", "renesas,scifb"; 691 reg = <0 0xe6c30000 0 0x100>; 692 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; 694 clock-names = "fck"; 695 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 696 <&dmac1 0x19>, <&dmac1 0x1a>; 697 dma-names = "tx", "rx", "tx", "rx"; 698 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 699 status = "disabled"; 700 }; 701 702 scifb2: serial@e6ce0000 { 703 compatible = "renesas,scifb-r8a7793", 704 "renesas,rcar-gen2-scifb", "renesas,scifb"; 705 reg = <0 0xe6ce0000 0 0x100>; 706 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; 708 clock-names = "fck"; 709 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 710 <&dmac1 0x1d>, <&dmac1 0x1e>; 711 dma-names = "tx", "rx", "tx", "rx"; 712 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 713 status = "disabled"; 714 }; 715 716 scif0: serial@e6e60000 { 717 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 718 "renesas,scif"; 719 reg = <0 0xe6e60000 0 64>; 720 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, 722 <&scif_clk>; 723 clock-names = "fck", "brg_int", "scif_clk"; 724 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 725 <&dmac1 0x29>, <&dmac1 0x2a>; 726 dma-names = "tx", "rx", "tx", "rx"; 727 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 728 status = "disabled"; 729 }; 730 731 scif1: serial@e6e68000 { 732 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 733 "renesas,scif"; 734 reg = <0 0xe6e68000 0 64>; 735 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, 737 <&scif_clk>; 738 clock-names = "fck", "brg_int", "scif_clk"; 739 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 740 <&dmac1 0x2d>, <&dmac1 0x2e>; 741 dma-names = "tx", "rx", "tx", "rx"; 742 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 743 status = "disabled"; 744 }; 745 746 scif2: serial@e6e58000 { 747 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 748 "renesas,scif"; 749 reg = <0 0xe6e58000 0 64>; 750 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, 752 <&scif_clk>; 753 clock-names = "fck", "brg_int", "scif_clk"; 754 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 755 <&dmac1 0x2b>, <&dmac1 0x2c>; 756 dma-names = "tx", "rx", "tx", "rx"; 757 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 758 status = "disabled"; 759 }; 760 761 scif3: serial@e6ea8000 { 762 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 763 "renesas,scif"; 764 reg = <0 0xe6ea8000 0 64>; 765 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, 767 <&scif_clk>; 768 clock-names = "fck", "brg_int", "scif_clk"; 769 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 770 <&dmac1 0x2f>, <&dmac1 0x30>; 771 dma-names = "tx", "rx", "tx", "rx"; 772 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 773 status = "disabled"; 774 }; 775 776 scif4: serial@e6ee0000 { 777 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 778 "renesas,scif"; 779 reg = <0 0xe6ee0000 0 64>; 780 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, 782 <&scif_clk>; 783 clock-names = "fck", "brg_int", "scif_clk"; 784 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 785 <&dmac1 0xfb>, <&dmac1 0xfc>; 786 dma-names = "tx", "rx", "tx", "rx"; 787 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 788 status = "disabled"; 789 }; 790 791 scif5: serial@e6ee8000 { 792 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", 793 "renesas,scif"; 794 reg = <0 0xe6ee8000 0 64>; 795 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, 797 <&scif_clk>; 798 clock-names = "fck", "brg_int", "scif_clk"; 799 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 800 <&dmac1 0xfd>, <&dmac1 0xfe>; 801 dma-names = "tx", "rx", "tx", "rx"; 802 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 803 status = "disabled"; 804 }; 805 806 hscif0: serial@e62c0000 { 807 compatible = "renesas,hscif-r8a7793", 808 "renesas,rcar-gen2-hscif", "renesas,hscif"; 809 reg = <0 0xe62c0000 0 96>; 810 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, 812 <&scif_clk>; 813 clock-names = "fck", "brg_int", "scif_clk"; 814 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 815 <&dmac1 0x39>, <&dmac1 0x3a>; 816 dma-names = "tx", "rx", "tx", "rx"; 817 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 818 status = "disabled"; 819 }; 820 821 hscif1: serial@e62c8000 { 822 compatible = "renesas,hscif-r8a7793", 823 "renesas,rcar-gen2-hscif", "renesas,hscif"; 824 reg = <0 0xe62c8000 0 96>; 825 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, 827 <&scif_clk>; 828 clock-names = "fck", "brg_int", "scif_clk"; 829 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 830 <&dmac1 0x4d>, <&dmac1 0x4e>; 831 dma-names = "tx", "rx", "tx", "rx"; 832 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 833 status = "disabled"; 834 }; 835 836 hscif2: serial@e62d0000 { 837 compatible = "renesas,hscif-r8a7793", 838 "renesas,rcar-gen2-hscif", "renesas,hscif"; 839 reg = <0 0xe62d0000 0 96>; 840 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, 842 <&scif_clk>; 843 clock-names = "fck", "brg_int", "scif_clk"; 844 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 845 <&dmac1 0x3b>, <&dmac1 0x3c>; 846 dma-names = "tx", "rx", "tx", "rx"; 847 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 848 status = "disabled"; 849 }; 850 851 icram0: sram@e63a0000 { 852 compatible = "mmio-sram"; 853 reg = <0 0xe63a0000 0 0x12000>; 854 }; 855 856 icram1: sram@e63c0000 { 857 compatible = "mmio-sram"; 858 reg = <0 0xe63c0000 0 0x1000>; 859 #address-cells = <1>; 860 #size-cells = <1>; 861 ranges = <0 0 0xe63c0000 0x1000>; 862 863 smp-sram@0 { 864 compatible = "renesas,smp-sram"; 865 reg = <0 0x10>; 866 }; 867 }; 868 869 ether: ethernet@ee700000 { 870 compatible = "renesas,ether-r8a7793"; 871 reg = <0 0xee700000 0 0x400>; 872 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&mstp8_clks R8A7793_CLK_ETHER>; 874 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 875 phy-mode = "rmii"; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 vin0: video@e6ef0000 { 882 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; 883 reg = <0 0xe6ef0000 0 0x1000>; 884 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&mstp8_clks R8A7793_CLK_VIN0>; 886 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 887 status = "disabled"; 888 }; 889 890 vin1: video@e6ef1000 { 891 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; 892 reg = <0 0xe6ef1000 0 0x1000>; 893 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&mstp8_clks R8A7793_CLK_VIN1>; 895 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 896 status = "disabled"; 897 }; 898 899 vin2: video@e6ef2000 { 900 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; 901 reg = <0 0xe6ef2000 0 0x1000>; 902 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&mstp8_clks R8A7793_CLK_VIN2>; 904 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 905 status = "disabled"; 906 }; 907 908 qspi: spi@e6b10000 { 909 compatible = "renesas,qspi-r8a7793", "renesas,qspi"; 910 reg = <0 0xe6b10000 0 0x2c>; 911 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; 913 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 914 <&dmac1 0x17>, <&dmac1 0x18>; 915 dma-names = "tx", "rx", "tx", "rx"; 916 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 917 num-cs = <1>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 status = "disabled"; 921 }; 922 923 du: display@feb00000 { 924 compatible = "renesas,du-r8a7793"; 925 reg = <0 0xfeb00000 0 0x40000>, 926 <0 0xfeb90000 0 0x1c>; 927 reg-names = "du", "lvds.0"; 928 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&mstp7_clks R8A7793_CLK_DU0>, 931 <&mstp7_clks R8A7793_CLK_DU1>, 932 <&mstp7_clks R8A7793_CLK_LVDS0>; 933 clock-names = "du.0", "du.1", "lvds.0"; 934 status = "disabled"; 935 936 ports { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 940 port@0 { 941 reg = <0>; 942 du_out_rgb: endpoint { 943 }; 944 }; 945 port@1 { 946 reg = <1>; 947 du_out_lvds0: endpoint { 948 }; 949 }; 950 }; 951 }; 952 953 can0: can@e6e80000 { 954 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; 955 reg = <0 0xe6e80000 0 0x1000>; 956 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, 958 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; 959 clock-names = "clkp1", "clkp2", "can_clk"; 960 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 961 status = "disabled"; 962 }; 963 964 can1: can@e6e88000 { 965 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; 966 reg = <0 0xe6e88000 0 0x1000>; 967 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, 969 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; 970 clock-names = "clkp1", "clkp2", "can_clk"; 971 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 972 status = "disabled"; 973 }; 974 975 clocks { 976 #address-cells = <2>; 977 #size-cells = <2>; 978 ranges; 979 980 /* External root clock */ 981 extal_clk: extal { 982 compatible = "fixed-clock"; 983 #clock-cells = <0>; 984 /* This value must be overridden by the board. */ 985 clock-frequency = <0>; 986 }; 987 988 /* 989 * The external audio clocks are configured as 0 Hz fixed frequency clocks by 990 * default. Boards that provide audio clocks should override them. 991 */ 992 audio_clk_a: audio_clk_a { 993 compatible = "fixed-clock"; 994 #clock-cells = <0>; 995 clock-frequency = <0>; 996 }; 997 audio_clk_b: audio_clk_b { 998 compatible = "fixed-clock"; 999 #clock-cells = <0>; 1000 clock-frequency = <0>; 1001 }; 1002 audio_clk_c: audio_clk_c { 1003 compatible = "fixed-clock"; 1004 #clock-cells = <0>; 1005 clock-frequency = <0>; 1006 }; 1007 1008 /* External USB clock - can be overridden by the board */ 1009 usb_extal_clk: usb_extal { 1010 compatible = "fixed-clock"; 1011 #clock-cells = <0>; 1012 clock-frequency = <48000000>; 1013 }; 1014 1015 /* External CAN clock */ 1016 can_clk: can { 1017 compatible = "fixed-clock"; 1018 #clock-cells = <0>; 1019 /* This value must be overridden by the board. */ 1020 clock-frequency = <0>; 1021 }; 1022 1023 /* External SCIF clock */ 1024 scif_clk: scif { 1025 compatible = "fixed-clock"; 1026 #clock-cells = <0>; 1027 /* This value must be overridden by the board. */ 1028 clock-frequency = <0>; 1029 }; 1030 1031 /* Special CPG clocks */ 1032 cpg_clocks: cpg_clocks@e6150000 { 1033 compatible = "renesas,r8a7793-cpg-clocks", 1034 "renesas,rcar-gen2-cpg-clocks"; 1035 reg = <0 0xe6150000 0 0x1000>; 1036 clocks = <&extal_clk &usb_extal_clk>; 1037 #clock-cells = <1>; 1038 clock-output-names = "main", "pll0", "pll1", "pll3", 1039 "lb", "qspi", "sdh", "sd0", "z", 1040 "rcan", "adsp"; 1041 #power-domain-cells = <0>; 1042 }; 1043 1044 /* Variable factor clocks */ 1045 sd2_clk: sd2@e6150078 { 1046 compatible = "renesas,r8a7793-div6-clock", 1047 "renesas,cpg-div6-clock"; 1048 reg = <0 0xe6150078 0 4>; 1049 clocks = <&pll1_div2_clk>; 1050 #clock-cells = <0>; 1051 }; 1052 sd3_clk: sd3@e615026c { 1053 compatible = "renesas,r8a7793-div6-clock", 1054 "renesas,cpg-div6-clock"; 1055 reg = <0 0xe615026c 0 4>; 1056 clocks = <&pll1_div2_clk>; 1057 #clock-cells = <0>; 1058 }; 1059 mmc0_clk: mmc0@e6150240 { 1060 compatible = "renesas,r8a7793-div6-clock", 1061 "renesas,cpg-div6-clock"; 1062 reg = <0 0xe6150240 0 4>; 1063 clocks = <&pll1_div2_clk>; 1064 #clock-cells = <0>; 1065 }; 1066 1067 /* Fixed factor clocks */ 1068 pll1_div2_clk: pll1_div2 { 1069 compatible = "fixed-factor-clock"; 1070 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1071 #clock-cells = <0>; 1072 clock-div = <2>; 1073 clock-mult = <1>; 1074 }; 1075 zg_clk: zg { 1076 compatible = "fixed-factor-clock"; 1077 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1078 #clock-cells = <0>; 1079 clock-div = <5>; 1080 clock-mult = <1>; 1081 }; 1082 zx_clk: zx { 1083 compatible = "fixed-factor-clock"; 1084 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1085 #clock-cells = <0>; 1086 clock-div = <3>; 1087 clock-mult = <1>; 1088 }; 1089 zs_clk: zs { 1090 compatible = "fixed-factor-clock"; 1091 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1092 #clock-cells = <0>; 1093 clock-div = <6>; 1094 clock-mult = <1>; 1095 }; 1096 hp_clk: hp { 1097 compatible = "fixed-factor-clock"; 1098 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1099 #clock-cells = <0>; 1100 clock-div = <12>; 1101 clock-mult = <1>; 1102 }; 1103 p_clk: p { 1104 compatible = "fixed-factor-clock"; 1105 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1106 #clock-cells = <0>; 1107 clock-div = <24>; 1108 clock-mult = <1>; 1109 }; 1110 m2_clk: m2 { 1111 compatible = "fixed-factor-clock"; 1112 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1113 #clock-cells = <0>; 1114 clock-div = <8>; 1115 clock-mult = <1>; 1116 }; 1117 rclk_clk: rclk { 1118 compatible = "fixed-factor-clock"; 1119 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 1120 #clock-cells = <0>; 1121 clock-div = <(48 * 1024)>; 1122 clock-mult = <1>; 1123 }; 1124 mp_clk: mp { 1125 compatible = "fixed-factor-clock"; 1126 clocks = <&pll1_div2_clk>; 1127 #clock-cells = <0>; 1128 clock-div = <15>; 1129 clock-mult = <1>; 1130 }; 1131 cp_clk: cp { 1132 compatible = "fixed-factor-clock"; 1133 clocks = <&extal_clk>; 1134 #clock-cells = <0>; 1135 clock-div = <2>; 1136 clock-mult = <1>; 1137 }; 1138 1139 /* Gate clocks */ 1140 mstp1_clks: mstp1_clks@e6150134 { 1141 compatible = "renesas,r8a7793-mstp-clocks", 1142 "renesas,cpg-mstp-clocks"; 1143 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1144 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 1145 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 1146 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 1147 <&zs_clk>, <&zs_clk>, <&zs_clk>; 1148 #clock-cells = <1>; 1149 clock-indices = < 1150 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 1151 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 1152 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC 1153 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 1154 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 1155 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 1156 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 1157 R8A7793_CLK_VSP1_S 1158 >; 1159 clock-output-names = 1160 "vcp0", "vpc0", "ssp_dev", "tmu1", 1161 "pvrsrvkm", "tddmac", "fdp1", "fdp0", 1162 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 1163 "vsp1-du0", "vsps"; 1164 }; 1165 mstp2_clks: mstp2_clks@e6150138 { 1166 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1167 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 1168 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 1169 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; 1170 #clock-cells = <1>; 1171 clock-indices = < 1172 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 1173 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 1174 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 1175 >; 1176 clock-output-names = 1177 "scifa2", "scifa1", "scifa0", "scifb0", 1178 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; 1179 }; 1180 mstp3_clks: mstp3_clks@e615013c { 1181 compatible = "renesas,r8a7793-mstp-clocks", 1182 "renesas,cpg-mstp-clocks"; 1183 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1184 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, 1185 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, 1186 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, 1187 <&rclk_clk>, <&hp_clk>, <&hp_clk>; 1188 #clock-cells = <1>; 1189 clock-indices = < 1190 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 1191 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 1192 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 1193 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 1194 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 1195 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 1196 >; 1197 clock-output-names = 1198 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", 1199 "i2c7", "pciec", "i2c8", "ssusb", "cmt1", 1200 "usbdmac0", "usbdmac1"; 1201 }; 1202 mstp4_clks: mstp4_clks@e6150140 { 1203 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1204 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 1205 clocks = <&cp_clk>, <&zs_clk>; 1206 #clock-cells = <1>; 1207 clock-indices = < 1208 R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS 1209 >; 1210 clock-output-names = "irqc", "intc-sys"; 1211 }; 1212 mstp5_clks: mstp5_clks@e6150144 { 1213 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1214 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1215 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; 1216 #clock-cells = <1>; 1217 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1 1218 R8A7793_CLK_THERMAL>; 1219 clock-output-names = "audmac0", "audmac1", "thermal"; 1220 }; 1221 mstp7_clks: mstp7_clks@e615014c { 1222 compatible = "renesas,r8a7793-mstp-clocks", 1223 "renesas,cpg-mstp-clocks"; 1224 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 1225 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, 1226 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 1227 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, 1228 <&zx_clk>, <&zx_clk>; 1229 #clock-cells = <1>; 1230 clock-indices = < 1231 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB 1232 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 1233 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 1234 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 1235 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 1236 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 1237 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 1238 >; 1239 clock-output-names = 1240 "ehci", "hsusb", "hscif2", "scif5", "scif4", 1241 "hscif1", "hscif0", "scif3", "scif2", 1242 "scif1", "scif0", "du1", "du0", "lvds0"; 1243 }; 1244 mstp8_clks: mstp8_clks@e6150990 { 1245 compatible = "renesas,r8a7793-mstp-clocks", 1246 "renesas,cpg-mstp-clocks"; 1247 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1248 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, 1249 <&p_clk>, <&zs_clk>, <&zs_clk>; 1250 #clock-cells = <1>; 1251 clock-indices = < 1252 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 1253 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 1254 R8A7793_CLK_ETHER R8A7793_CLK_SATA1 1255 R8A7793_CLK_SATA0 1256 >; 1257 clock-output-names = 1258 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", 1259 "sata1", "sata0"; 1260 }; 1261 mstp9_clks: mstp9_clks@e6150994 { 1262 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1263 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1264 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1265 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1266 <&p_clk>, <&p_clk>, 1267 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, 1268 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1269 <&hp_clk>, <&hp_clk>; 1270 #clock-cells = <1>; 1271 clock-indices = < 1272 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 1273 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 1274 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 1275 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 1276 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 1277 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 1278 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 1279 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 1280 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 1281 >; 1282 clock-output-names = 1283 "gpio7", "gpio6", "gpio5", "gpio4", 1284 "gpio3", "gpio2", "gpio1", "gpio0", 1285 "rcan1", "rcan0", "qspi_mod", "i2c5", 1286 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", 1287 "i2c0"; 1288 }; 1289 mstp10_clks: mstp10_clks@e6150998 { 1290 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1291 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; 1292 clocks = <&p_clk>, 1293 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1294 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1295 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1296 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1297 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1298 <&p_clk>, 1299 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1300 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1301 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1302 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1303 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1304 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, 1305 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; 1306 1307 #clock-cells = <1>; 1308 clock-indices = < 1309 R8A7793_CLK_SSI_ALL 1310 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 1311 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 1312 R8A7793_CLK_SCU_ALL 1313 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 1314 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 1315 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 1316 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 1317 >; 1318 clock-output-names = 1319 "ssi-all", 1320 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", 1321 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", 1322 "scu-all", 1323 "scu-dvc1", "scu-dvc0", 1324 "scu-ctu1-mix1", "scu-ctu0-mix0", 1325 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", 1326 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; 1327 }; 1328 mstp11_clks: mstp11_clks@e615099c { 1329 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 1330 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1331 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1332 #clock-cells = <1>; 1333 clock-indices = < 1334 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 1335 >; 1336 clock-output-names = "scifa3", "scifa4", "scifa5"; 1337 }; 1338 }; 1339 1340 rst: reset-controller@e6160000 { 1341 compatible = "renesas,r8a7793-rst"; 1342 reg = <0 0xe6160000 0 0x0100>; 1343 }; 1344 1345 prr: chipid@ff000044 { 1346 compatible = "renesas,prr"; 1347 reg = <0 0xff000044 0 4>; 1348 }; 1349 1350 sysc: system-controller@e6180000 { 1351 compatible = "renesas,r8a7793-sysc"; 1352 reg = <0 0xe6180000 0 0x0200>; 1353 #power-domain-cells = <1>; 1354 }; 1355 1356 ipmmu_sy0: mmu@e6280000 { 1357 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1358 reg = <0 0xe6280000 0 0x1000>; 1359 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1361 #iommu-cells = <1>; 1362 status = "disabled"; 1363 }; 1364 1365 ipmmu_sy1: mmu@e6290000 { 1366 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1367 reg = <0 0xe6290000 0 0x1000>; 1368 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1369 #iommu-cells = <1>; 1370 status = "disabled"; 1371 }; 1372 1373 ipmmu_ds: mmu@e6740000 { 1374 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1375 reg = <0 0xe6740000 0 0x1000>; 1376 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1378 #iommu-cells = <1>; 1379 status = "disabled"; 1380 }; 1381 1382 ipmmu_mp: mmu@ec680000 { 1383 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1384 reg = <0 0xec680000 0 0x1000>; 1385 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1386 #iommu-cells = <1>; 1387 status = "disabled"; 1388 }; 1389 1390 ipmmu_mx: mmu@fe951000 { 1391 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1392 reg = <0 0xfe951000 0 0x1000>; 1393 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1395 #iommu-cells = <1>; 1396 status = "disabled"; 1397 }; 1398 1399 ipmmu_rt: mmu@ffc80000 { 1400 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1401 reg = <0 0xffc80000 0 0x1000>; 1402 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1403 #iommu-cells = <1>; 1404 status = "disabled"; 1405 }; 1406 1407 ipmmu_gp: mmu@e62a0000 { 1408 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1409 reg = <0 0xe62a0000 0 0x1000>; 1410 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1412 #iommu-cells = <1>; 1413 status = "disabled"; 1414 }; 1415 1416 rcar_sound: sound@ec500000 { 1417 /* 1418 * #sound-dai-cells is required 1419 * 1420 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1421 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1422 */ 1423 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2"; 1424 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1425 <0 0xec5a0000 0 0x100>, /* ADG */ 1426 <0 0xec540000 0 0x1000>, /* SSIU */ 1427 <0 0xec541000 0 0x280>, /* SSI */ 1428 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1429 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1430 1431 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, 1432 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, 1433 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, 1434 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, 1435 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, 1436 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, 1437 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, 1438 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, 1439 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, 1440 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, 1441 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, 1442 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, 1443 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; 1444 clock-names = "ssi-all", 1445 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1446 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1447 "src.9", "src.8", "src.7", "src.6", "src.5", 1448 "src.4", "src.3", "src.2", "src.1", "src.0", 1449 "dvc.0", "dvc.1", 1450 "clk_a", "clk_b", "clk_c", "clk_i"; 1451 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1452 1453 status = "disabled"; 1454 1455 rcar_sound,dvc { 1456 dvc0: dvc-0 { 1457 dmas = <&audma1 0xbc>; 1458 dma-names = "tx"; 1459 }; 1460 dvc1: dvc-1 { 1461 dmas = <&audma1 0xbe>; 1462 dma-names = "tx"; 1463 }; 1464 }; 1465 1466 rcar_sound,src { 1467 src0: src-0 { 1468 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1469 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1470 dma-names = "rx", "tx"; 1471 }; 1472 src1: src-1 { 1473 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1474 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1475 dma-names = "rx", "tx"; 1476 }; 1477 src2: src-2 { 1478 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1480 dma-names = "rx", "tx"; 1481 }; 1482 src3: src-3 { 1483 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1484 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1485 dma-names = "rx", "tx"; 1486 }; 1487 src4: src-4 { 1488 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1489 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1490 dma-names = "rx", "tx"; 1491 }; 1492 src5: src-5 { 1493 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1494 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1495 dma-names = "rx", "tx"; 1496 }; 1497 src6: src-6 { 1498 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1499 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1500 dma-names = "rx", "tx"; 1501 }; 1502 src7: src-7 { 1503 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1504 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1505 dma-names = "rx", "tx"; 1506 }; 1507 src8: src-8 { 1508 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1509 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1510 dma-names = "rx", "tx"; 1511 }; 1512 src9: src-9 { 1513 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1514 dmas = <&audma0 0x97>, <&audma1 0xba>; 1515 dma-names = "rx", "tx"; 1516 }; 1517 }; 1518 1519 rcar_sound,ssi { 1520 ssi0: ssi-0 { 1521 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1522 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1523 dma-names = "rx", "tx", "rxu", "txu"; 1524 }; 1525 ssi1: ssi-1 { 1526 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1528 dma-names = "rx", "tx", "rxu", "txu"; 1529 }; 1530 ssi2: ssi-2 { 1531 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1532 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1533 dma-names = "rx", "tx", "rxu", "txu"; 1534 }; 1535 ssi3: ssi-3 { 1536 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1537 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1538 dma-names = "rx", "tx", "rxu", "txu"; 1539 }; 1540 ssi4: ssi-4 { 1541 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1542 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1543 dma-names = "rx", "tx", "rxu", "txu"; 1544 }; 1545 ssi5: ssi-5 { 1546 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1547 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1548 dma-names = "rx", "tx", "rxu", "txu"; 1549 }; 1550 ssi6: ssi-6 { 1551 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1552 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1553 dma-names = "rx", "tx", "rxu", "txu"; 1554 }; 1555 ssi7: ssi-7 { 1556 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1557 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1558 dma-names = "rx", "tx", "rxu", "txu"; 1559 }; 1560 ssi8: ssi-8 { 1561 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1562 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1563 dma-names = "rx", "tx", "rxu", "txu"; 1564 }; 1565 ssi9: ssi-9 { 1566 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1567 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1568 dma-names = "rx", "tx", "rxu", "txu"; 1569 }; 1570 }; 1571 }; 1572}; 1573