1/* 2 * DTS file for all SPEAr13xx SoCs 3 * 4 * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14/include/ "skeleton.dtsi" 15 16/ { 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 compatible = "arm,cortex-a9"; 25 device_type = "cpu"; 26 reg = <0>; 27 next-level-cache = <&L2>; 28 }; 29 30 cpu@1 { 31 compatible = "arm,cortex-a9"; 32 device_type = "cpu"; 33 reg = <1>; 34 next-level-cache = <&L2>; 35 }; 36 }; 37 38 gic: interrupt-controller@ec801000 { 39 compatible = "arm,cortex-a9-gic"; 40 interrupt-controller; 41 #interrupt-cells = <3>; 42 reg = < 0xec801000 0x1000 >, 43 < 0xec800100 0x0100 >; 44 }; 45 46 pmu { 47 compatible = "arm,cortex-a9-pmu"; 48 interrupts = <0 6 0x04 49 0 7 0x04>; 50 }; 51 52 L2: l2-cache { 53 compatible = "arm,pl310-cache"; 54 reg = <0xed000000 0x1000>; 55 cache-unified; 56 cache-level = <2>; 57 }; 58 59 memory { 60 name = "memory"; 61 device_type = "memory"; 62 reg = <0 0x40000000>; 63 }; 64 65 chosen { 66 bootargs = "console=ttyAMA0,115200"; 67 }; 68 69 cpufreq { 70 compatible = "st,cpufreq-spear"; 71 cpufreq_tbl = < 166000 72 200000 73 250000 74 300000 75 400000 76 500000 77 600000 >; 78 status = "disabled"; 79 }; 80 81 ahb { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 compatible = "simple-bus"; 85 ranges = <0x50000000 0x50000000 0x10000000 86 0x80000000 0x80000000 0x20000000 87 0xb0000000 0xb0000000 0x22000000 88 0xd8000000 0xd8000000 0x01000000 89 0xe0000000 0xe0000000 0x10000000>; 90 91 sdhci@b3000000 { 92 compatible = "st,sdhci-spear"; 93 reg = <0xb3000000 0x100>; 94 interrupts = <0 28 0x4>; 95 status = "disabled"; 96 }; 97 98 cf@b2800000 { 99 compatible = "arasan,cf-spear1340"; 100 reg = <0xb2800000 0x1000>; 101 interrupts = <0 29 0x4>; 102 status = "disabled"; 103 dmas = <&dwdma0 0 0 0>; 104 dma-names = "data"; 105 }; 106 107 dwdma0: dma@ea800000 { 108 compatible = "snps,dma-spear1340"; 109 reg = <0xea800000 0x1000>; 110 interrupts = <0 19 0x4>; 111 status = "disabled"; 112 113 dma-channels = <8>; 114 #dma-cells = <3>; 115 dma-requests = <32>; 116 chan_allocation_order = <1>; 117 chan_priority = <1>; 118 block_size = <0xfff>; 119 dma-masters = <2>; 120 data-width = <8 8>; 121 multi-block = <1 1 1 1 1 1 1 1>; 122 }; 123 124 dma@eb000000 { 125 compatible = "snps,dma-spear1340"; 126 reg = <0xeb000000 0x1000>; 127 interrupts = <0 59 0x4>; 128 status = "disabled"; 129 130 dma-requests = <32>; 131 dma-channels = <8>; 132 dma-masters = <2>; 133 #dma-cells = <3>; 134 chan_allocation_order = <1>; 135 chan_priority = <1>; 136 block_size = <0xfff>; 137 data-width = <8 8>; 138 multi-block = <1 1 1 1 1 1 1 1>; 139 }; 140 141 fsmc: flash@b0000000 { 142 compatible = "st,spear600-fsmc-nand"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 reg = <0xb0000000 0x1000 /* FSMC Register*/ 146 0xb0800000 0x0010 /* NAND Base DATA */ 147 0xb0820000 0x0010 /* NAND Base ADDR */ 148 0xb0810000 0x0010>; /* NAND Base CMD */ 149 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 150 interrupts = <0 20 0x4 151 0 21 0x4 152 0 22 0x4 153 0 23 0x4>; 154 st,mode = <2>; 155 status = "disabled"; 156 }; 157 158 gmac0: eth@e2000000 { 159 compatible = "st,spear600-gmac"; 160 reg = <0xe2000000 0x8000>; 161 interrupts = <0 33 0x4 162 0 34 0x4>; 163 interrupt-names = "macirq", "eth_wake_irq"; 164 status = "disabled"; 165 }; 166 167 pcm { 168 compatible = "st,pcm-audio"; 169 #address-cells = <0>; 170 #size-cells = <0>; 171 status = "disabled"; 172 }; 173 174 smi: flash@ea000000 { 175 compatible = "st,spear600-smi"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 reg = <0xea000000 0x1000>; 179 interrupts = <0 30 0x4>; 180 status = "disabled"; 181 }; 182 183 ehci@e4800000 { 184 compatible = "st,spear600-ehci", "usb-ehci"; 185 reg = <0xe4800000 0x1000>; 186 interrupts = <0 64 0x4>; 187 usbh0_id = <0>; 188 status = "disabled"; 189 }; 190 191 ehci@e5800000 { 192 compatible = "st,spear600-ehci", "usb-ehci"; 193 reg = <0xe5800000 0x1000>; 194 interrupts = <0 66 0x4>; 195 usbh1_id = <1>; 196 status = "disabled"; 197 }; 198 199 ohci@e4000000 { 200 compatible = "st,spear600-ohci", "usb-ohci"; 201 reg = <0xe4000000 0x1000>; 202 interrupts = <0 65 0x4>; 203 usbh0_id = <0>; 204 status = "disabled"; 205 }; 206 207 ohci@e5000000 { 208 compatible = "st,spear600-ohci", "usb-ohci"; 209 reg = <0xe5000000 0x1000>; 210 interrupts = <0 67 0x4>; 211 usbh1_id = <1>; 212 status = "disabled"; 213 }; 214 215 apb { 216 #address-cells = <1>; 217 #size-cells = <1>; 218 compatible = "simple-bus"; 219 ranges = <0x50000000 0x50000000 0x10000000 220 0xb0000000 0xb0000000 0x10000000 221 0xd0000000 0xd0000000 0x02000000 222 0xd8000000 0xd8000000 0x01000000 223 0xe0000000 0xe0000000 0x10000000>; 224 225 misc: syscon@e0700000 { 226 compatible = "st,spear1340-misc", "syscon"; 227 reg = <0xe0700000 0x1000>; 228 }; 229 230 gpio0: gpio@e0600000 { 231 compatible = "arm,pl061", "arm,primecell"; 232 reg = <0xe0600000 0x1000>; 233 interrupts = <0 24 0x4>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 status = "disabled"; 239 }; 240 241 gpio1: gpio@e0680000 { 242 compatible = "arm,pl061", "arm,primecell"; 243 reg = <0xe0680000 0x1000>; 244 interrupts = <0 25 0x4>; 245 gpio-controller; 246 #gpio-cells = <2>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 status = "disabled"; 250 }; 251 252 kbd@e0300000 { 253 compatible = "st,spear300-kbd"; 254 reg = <0xe0300000 0x1000>; 255 interrupts = <0 52 0x4>; 256 status = "disabled"; 257 }; 258 259 i2c0: i2c@e0280000 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "snps,designware-i2c"; 263 reg = <0xe0280000 0x1000>; 264 interrupts = <0 41 0x4>; 265 status = "disabled"; 266 }; 267 268 i2s@e0180000 { 269 compatible = "st,designware-i2s"; 270 reg = <0xe0180000 0x1000>; 271 interrupt-names = "play_irq", "record_irq"; 272 interrupts = <0 10 0x4 273 0 11 0x4 >; 274 status = "disabled"; 275 }; 276 277 i2s@e0200000 { 278 compatible = "st,designware-i2s"; 279 reg = <0xe0200000 0x1000>; 280 interrupt-names = "play_irq", "record_irq"; 281 interrupts = <0 26 0x4 282 0 53 0x4>; 283 status = "disabled"; 284 }; 285 286 spi0: spi@e0100000 { 287 compatible = "arm,pl022", "arm,primecell"; 288 reg = <0xe0100000 0x1000>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 interrupts = <0 31 0x4>; 292 status = "disabled"; 293 dmas = <&dwdma0 4 0 0>, 294 <&dwdma0 5 0 0>; 295 dma-names = "tx", "rx"; 296 }; 297 298 rtc@e0580000 { 299 compatible = "st,spear600-rtc"; 300 reg = <0xe0580000 0x1000>; 301 interrupts = <0 36 0x4>; 302 status = "disabled"; 303 }; 304 305 serial@e0000000 { 306 compatible = "arm,pl011", "arm,primecell"; 307 reg = <0xe0000000 0x1000>; 308 interrupts = <0 35 0x4>; 309 status = "disabled"; 310 }; 311 312 adc@e0080000 { 313 compatible = "st,spear600-adc"; 314 reg = <0xe0080000 0x1000>; 315 interrupts = <0 12 0x4>; 316 status = "disabled"; 317 }; 318 319 timer@e0380000 { 320 compatible = "st,spear-timer"; 321 reg = <0xe0380000 0x400>; 322 interrupts = <0 37 0x4>; 323 }; 324 325 timer@ec800600 { 326 compatible = "arm,cortex-a9-twd-timer"; 327 reg = <0xec800600 0x20>; 328 interrupts = <1 13 0x4>; 329 status = "disabled"; 330 }; 331 332 wdt@ec800620 { 333 compatible = "arm,cortex-a9-twd-wdt"; 334 reg = <0xec800620 0x20>; 335 status = "disabled"; 336 }; 337 338 thermal@e07008c4 { 339 compatible = "st,thermal-spear1340"; 340 reg = <0xe07008c4 0x4>; 341 thermal_flags = <0x7000>; 342 }; 343 }; 344 }; 345}; 346