1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "skeleton.dtsi" 44#include "armv7-m.dtsi" 45#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> 46#include <dt-bindings/clock/stm32fx-clock.h> 47#include <dt-bindings/mfd/stm32f7-rcc.h> 48 49/ { 50 clocks { 51 clk_hse: clk-hse { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <0>; 55 }; 56 57 clk-lse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 clk-lsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32000>; 67 }; 68 69 clk_i2s_ckin: clk-i2s-ckin { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <48000000>; 73 }; 74 }; 75 76 soc { 77 timer2: timer@40000000 { 78 compatible = "st,stm32-timer"; 79 reg = <0x40000000 0x400>; 80 interrupts = <28>; 81 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 82 status = "disabled"; 83 }; 84 85 timer3: timer@40000400 { 86 compatible = "st,stm32-timer"; 87 reg = <0x40000400 0x400>; 88 interrupts = <29>; 89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 90 status = "disabled"; 91 }; 92 93 timer4: timer@40000800 { 94 compatible = "st,stm32-timer"; 95 reg = <0x40000800 0x400>; 96 interrupts = <30>; 97 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 98 status = "disabled"; 99 }; 100 101 timer5: timer@40000c00 { 102 compatible = "st,stm32-timer"; 103 reg = <0x40000c00 0x400>; 104 interrupts = <50>; 105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 106 }; 107 108 timer6: timer@40001000 { 109 compatible = "st,stm32-timer"; 110 reg = <0x40001000 0x400>; 111 interrupts = <54>; 112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 113 status = "disabled"; 114 }; 115 116 timer7: timer@40001400 { 117 compatible = "st,stm32-timer"; 118 reg = <0x40001400 0x400>; 119 interrupts = <55>; 120 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 121 status = "disabled"; 122 }; 123 124 rtc: rtc@40002800 { 125 compatible = "st,stm32-rtc"; 126 reg = <0x40002800 0x400>; 127 clocks = <&rcc 1 CLK_RTC>; 128 clock-names = "ck_rtc"; 129 assigned-clocks = <&rcc 1 CLK_RTC>; 130 assigned-clock-parents = <&rcc 1 CLK_LSE>; 131 interrupt-parent = <&exti>; 132 interrupts = <17 1>; 133 interrupt-names = "alarm"; 134 st,syscfg = <&pwrcfg>; 135 status = "disabled"; 136 }; 137 138 usart2: serial@40004400 { 139 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 140 reg = <0x40004400 0x400>; 141 interrupts = <38>; 142 clocks = <&rcc 1 CLK_USART2>; 143 status = "disabled"; 144 }; 145 146 usart3: serial@40004800 { 147 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 148 reg = <0x40004800 0x400>; 149 interrupts = <39>; 150 clocks = <&rcc 1 CLK_USART3>; 151 status = "disabled"; 152 }; 153 154 usart4: serial@40004c00 { 155 compatible = "st,stm32f7-uart"; 156 reg = <0x40004c00 0x400>; 157 interrupts = <52>; 158 clocks = <&rcc 1 CLK_UART4>; 159 status = "disabled"; 160 }; 161 162 usart5: serial@40005000 { 163 compatible = "st,stm32f7-uart"; 164 reg = <0x40005000 0x400>; 165 interrupts = <53>; 166 clocks = <&rcc 1 CLK_UART5>; 167 status = "disabled"; 168 }; 169 170 cec: cec@40006c00 { 171 compatible = "st,stm32-cec"; 172 reg = <0x40006C00 0x400>; 173 interrupts = <94>; 174 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 175 clock-names = "cec", "hdmi-cec"; 176 status = "disabled"; 177 }; 178 179 usart7: serial@40007800 { 180 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 181 reg = <0x40007800 0x400>; 182 interrupts = <82>; 183 clocks = <&rcc 1 CLK_UART7>; 184 status = "disabled"; 185 }; 186 187 usart8: serial@40007c00 { 188 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 189 reg = <0x40007c00 0x400>; 190 interrupts = <83>; 191 clocks = <&rcc 1 CLK_UART8>; 192 status = "disabled"; 193 }; 194 195 usart1: serial@40011000 { 196 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 197 reg = <0x40011000 0x400>; 198 interrupts = <37>; 199 clocks = <&rcc 1 CLK_USART1>; 200 status = "disabled"; 201 }; 202 203 usart6: serial@40011400 { 204 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 205 reg = <0x40011400 0x400>; 206 interrupts = <71>; 207 clocks = <&rcc 1 CLK_USART6>; 208 status = "disabled"; 209 }; 210 211 syscfg: system-config@40013800 { 212 compatible = "syscon"; 213 reg = <0x40013800 0x400>; 214 }; 215 216 exti: interrupt-controller@40013c00 { 217 compatible = "st,stm32-exti"; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 reg = <0x40013C00 0x400>; 221 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 222 }; 223 224 pwrcfg: power-config@40007000 { 225 compatible = "syscon"; 226 reg = <0x40007000 0x400>; 227 }; 228 229 pin-controller { 230 #address-cells = <1>; 231 #size-cells = <1>; 232 compatible = "st,stm32f746-pinctrl"; 233 ranges = <0 0x40020000 0x3000>; 234 interrupt-parent = <&exti>; 235 st,syscfg = <&syscfg 0x8>; 236 pins-are-numbered; 237 238 gpioa: gpio@40020000 { 239 gpio-controller; 240 #gpio-cells = <2>; 241 interrupt-controller; 242 #interrupt-cells = <2>; 243 reg = <0x0 0x400>; 244 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; 245 st,bank-name = "GPIOA"; 246 }; 247 248 gpiob: gpio@40020400 { 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 reg = <0x400 0x400>; 254 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; 255 st,bank-name = "GPIOB"; 256 }; 257 258 gpioc: gpio@40020800 { 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 reg = <0x800 0x400>; 264 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; 265 st,bank-name = "GPIOC"; 266 }; 267 268 gpiod: gpio@40020c00 { 269 gpio-controller; 270 #gpio-cells = <2>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 reg = <0xc00 0x400>; 274 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; 275 st,bank-name = "GPIOD"; 276 }; 277 278 gpioe: gpio@40021000 { 279 gpio-controller; 280 #gpio-cells = <2>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 reg = <0x1000 0x400>; 284 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; 285 st,bank-name = "GPIOE"; 286 }; 287 288 gpiof: gpio@40021400 { 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 reg = <0x1400 0x400>; 294 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; 295 st,bank-name = "GPIOF"; 296 }; 297 298 gpiog: gpio@40021800 { 299 gpio-controller; 300 #gpio-cells = <2>; 301 interrupt-controller; 302 #interrupt-cells = <2>; 303 reg = <0x1800 0x400>; 304 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; 305 st,bank-name = "GPIOG"; 306 }; 307 308 gpioh: gpio@40021c00 { 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 reg = <0x1c00 0x400>; 314 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; 315 st,bank-name = "GPIOH"; 316 }; 317 318 gpioi: gpio@40022000 { 319 gpio-controller; 320 #gpio-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 reg = <0x2000 0x400>; 324 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; 325 st,bank-name = "GPIOI"; 326 }; 327 328 gpioj: gpio@40022400 { 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 reg = <0x2400 0x400>; 334 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; 335 st,bank-name = "GPIOJ"; 336 }; 337 338 gpiok: gpio@40022800 { 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 reg = <0x2800 0x400>; 344 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; 345 st,bank-name = "GPIOK"; 346 }; 347 348 cec_pins_a: cec@0 { 349 pins { 350 pinmux = <STM32F746_PA15_FUNC_HDMI_CEC>; 351 slew-rate = <0>; 352 drive-open-drain; 353 bias-disable; 354 }; 355 }; 356 357 usart1_pins_a: usart1@0 { 358 pins1 { 359 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 360 bias-disable; 361 drive-push-pull; 362 slew-rate = <0>; 363 }; 364 pins2 { 365 pinmux = <STM32F746_PA10_FUNC_USART1_RX>; 366 bias-disable; 367 }; 368 }; 369 370 usart1_pins_b: usart1@1 { 371 pins1 { 372 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 373 bias-disable; 374 drive-push-pull; 375 slew-rate = <0>; 376 }; 377 pins2 { 378 pinmux = <STM32F746_PB7_FUNC_USART1_RX>; 379 bias-disable; 380 }; 381 }; 382 }; 383 384 crc: crc@40023000 { 385 compatible = "st,stm32f7-crc"; 386 reg = <0x40023000 0x400>; 387 clocks = <&rcc 0 12>; 388 status = "disabled"; 389 }; 390 391 rcc: rcc@40023800 { 392 #reset-cells = <1>; 393 #clock-cells = <2>; 394 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 395 reg = <0x40023800 0x400>; 396 clocks = <&clk_hse>, <&clk_i2s_ckin>; 397 st,syscfg = <&pwrcfg>; 398 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 399 assigned-clock-rates = <1000000>; 400 }; 401 402 dma1: dma@40026000 { 403 compatible = "st,stm32-dma"; 404 reg = <0x40026000 0x400>; 405 interrupts = <11>, 406 <12>, 407 <13>, 408 <14>, 409 <15>, 410 <16>, 411 <17>, 412 <47>; 413 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 414 #dma-cells = <4>; 415 status = "disabled"; 416 }; 417 418 dma2: dma@40026400 { 419 compatible = "st,stm32-dma"; 420 reg = <0x40026400 0x400>; 421 interrupts = <56>, 422 <57>, 423 <58>, 424 <59>, 425 <60>, 426 <68>, 427 <69>, 428 <70>; 429 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 430 #dma-cells = <4>; 431 st,mem2mem; 432 status = "disabled"; 433 }; 434 }; 435}; 436 437&systick { 438 clocks = <&rcc 1 0>; 439 status = "okay"; 440}; 441