1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton64.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/clock/sun9i-a80-ccu.h> 50#include <dt-bindings/clock/sun9i-a80-de.h> 51#include <dt-bindings/clock/sun9i-a80-usb.h> 52#include <dt-bindings/reset/sun9i-a80-ccu.h> 53#include <dt-bindings/reset/sun9i-a80-de.h> 54#include <dt-bindings/reset/sun9i-a80-usb.h> 55 56/ { 57 interrupt-parent = <&gic>; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a7"; 65 device_type = "cpu"; 66 reg = <0x0>; 67 }; 68 69 cpu1: cpu@1 { 70 compatible = "arm,cortex-a7"; 71 device_type = "cpu"; 72 reg = <0x1>; 73 }; 74 75 cpu2: cpu@2 { 76 compatible = "arm,cortex-a7"; 77 device_type = "cpu"; 78 reg = <0x2>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a7"; 83 device_type = "cpu"; 84 reg = <0x3>; 85 }; 86 87 cpu4: cpu@100 { 88 compatible = "arm,cortex-a15"; 89 device_type = "cpu"; 90 reg = <0x100>; 91 }; 92 93 cpu5: cpu@101 { 94 compatible = "arm,cortex-a15"; 95 device_type = "cpu"; 96 reg = <0x101>; 97 }; 98 99 cpu6: cpu@102 { 100 compatible = "arm,cortex-a15"; 101 device_type = "cpu"; 102 reg = <0x102>; 103 }; 104 105 cpu7: cpu@103 { 106 compatible = "arm,cortex-a15"; 107 device_type = "cpu"; 108 reg = <0x103>; 109 }; 110 }; 111 112 memory { 113 /* 8GB max. with LPAE */ 114 reg = <0 0x20000000 0x02 0>; 115 }; 116 117 timer { 118 compatible = "arm,armv7-timer"; 119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 123 clock-frequency = <24000000>; 124 arm,cpu-registers-not-fw-configured; 125 }; 126 127 clocks { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 /* 131 * map 64 bit address range down to 32 bits, 132 * as the peripherals are all under 512MB. 133 */ 134 ranges = <0 0 0 0x20000000>; 135 136 /* 137 * This clock is actually configurable from the PRCM address 138 * space. The external 24M oscillator can be turned off, and 139 * the clock switched to an internal 16M RC oscillator. Under 140 * normal operation there's no reason to do this, and the 141 * default is to use the external good one, so just model this 142 * as a fixed clock. Also it is not entirely clear if the 143 * osc24M mux in the PRCM affects the entire clock tree, which 144 * would also throw all the PLL clock rates off, or just the 145 * downstream clocks in the PRCM. 146 */ 147 osc24M: osc24M_clk { 148 #clock-cells = <0>; 149 compatible = "fixed-clock"; 150 clock-frequency = <24000000>; 151 clock-output-names = "osc24M"; 152 }; 153 154 /* 155 * The 32k clock is from an external source, normally the 156 * AC100 codec/RTC chip. This serves as a placeholder for 157 * board dts files to specify the source. 158 */ 159 osc32k: osc32k_clk { 160 #clock-cells = <0>; 161 compatible = "fixed-factor-clock"; 162 clock-div = <1>; 163 clock-mult = <1>; 164 clock-output-names = "osc32k"; 165 }; 166 167 cpus_clk: clk@08001410 { 168 compatible = "allwinner,sun9i-a80-cpus-clk"; 169 reg = <0x08001410 0x4>; 170 #clock-cells = <0>; 171 clocks = <&osc32k>, <&osc24M>, 172 <&ccu CLK_PLL_PERIPH0>, 173 <&ccu CLK_PLL_AUDIO>; 174 clock-output-names = "cpus"; 175 }; 176 177 ahbs: ahbs_clk { 178 compatible = "fixed-factor-clock"; 179 #clock-cells = <0>; 180 clock-div = <1>; 181 clock-mult = <1>; 182 clocks = <&cpus_clk>; 183 clock-output-names = "ahbs"; 184 }; 185 186 apbs: clk@0800141c { 187 compatible = "allwinner,sun8i-a23-apb0-clk"; 188 reg = <0x0800141c 0x4>; 189 #clock-cells = <0>; 190 clocks = <&ahbs>; 191 clock-output-names = "apbs"; 192 }; 193 194 apbs_gates: clk@08001428 { 195 compatible = "allwinner,sun9i-a80-apbs-gates-clk"; 196 reg = <0x08001428 0x4>; 197 #clock-cells = <1>; 198 clocks = <&apbs>; 199 clock-indices = <0>, <1>, 200 <2>, <3>, 201 <4>, <5>, 202 <6>, <7>, 203 <12>, <13>, 204 <16>, <17>, 205 <18>, <20>; 206 clock-output-names = "apbs_pio", "apbs_ir", 207 "apbs_timer", "apbs_rsb", 208 "apbs_uart", "apbs_1wire", 209 "apbs_i2c0", "apbs_i2c1", 210 "apbs_ps2_0", "apbs_ps2_1", 211 "apbs_dma", "apbs_i2s0", 212 "apbs_i2s1", "apbs_twd"; 213 }; 214 215 r_1wire_clk: clk@08001450 { 216 reg = <0x08001450 0x4>; 217 #clock-cells = <0>; 218 compatible = "allwinner,sun4i-a10-mod0-clk"; 219 clocks = <&osc32k>, <&osc24M>; 220 clock-output-names = "r_1wire"; 221 }; 222 223 r_ir_clk: clk@08001454 { 224 reg = <0x08001454 0x4>; 225 #clock-cells = <0>; 226 compatible = "allwinner,sun4i-a10-mod0-clk"; 227 clocks = <&osc32k>, <&osc24M>; 228 clock-output-names = "r_ir"; 229 }; 230 }; 231 232 soc { 233 compatible = "simple-bus"; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 /* 237 * map 64 bit address range down to 32 bits, 238 * as the peripherals are all under 512MB. 239 */ 240 ranges = <0 0 0 0x20000000>; 241 242 ehci0: usb@00a00000 { 243 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 244 reg = <0x00a00000 0x100>; 245 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&usb_clocks CLK_BUS_HCI0>; 247 resets = <&usb_clocks RST_USB0_HCI>; 248 phys = <&usbphy1>; 249 phy-names = "usb"; 250 status = "disabled"; 251 }; 252 253 ohci0: usb@00a00400 { 254 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 255 reg = <0x00a00400 0x100>; 256 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&usb_clocks CLK_BUS_HCI0>, 258 <&usb_clocks CLK_USB_OHCI0>; 259 resets = <&usb_clocks RST_USB0_HCI>; 260 phys = <&usbphy1>; 261 phy-names = "usb"; 262 status = "disabled"; 263 }; 264 265 usbphy1: phy@00a00800 { 266 compatible = "allwinner,sun9i-a80-usb-phy"; 267 reg = <0x00a00800 0x4>; 268 clocks = <&usb_clocks CLK_USB0_PHY>; 269 clock-names = "phy"; 270 resets = <&usb_clocks RST_USB0_PHY>; 271 reset-names = "phy"; 272 status = "disabled"; 273 #phy-cells = <0>; 274 }; 275 276 ehci1: usb@00a01000 { 277 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 278 reg = <0x00a01000 0x100>; 279 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&usb_clocks CLK_BUS_HCI1>; 281 resets = <&usb_clocks RST_USB1_HCI>; 282 phys = <&usbphy2>; 283 phy-names = "usb"; 284 status = "disabled"; 285 }; 286 287 usbphy2: phy@00a01800 { 288 compatible = "allwinner,sun9i-a80-usb-phy"; 289 reg = <0x00a01800 0x4>; 290 clocks = <&usb_clocks CLK_USB1_HSIC>, 291 <&usb_clocks CLK_USB_HSIC>, 292 <&usb_clocks CLK_USB1_PHY>; 293 clock-names = "hsic_480M", 294 "hsic_12M", 295 "phy"; 296 resets = <&usb_clocks RST_USB1_HSIC>, 297 <&usb_clocks RST_USB1_PHY>; 298 reset-names = "hsic", 299 "phy"; 300 status = "disabled"; 301 #phy-cells = <0>; 302 /* usb1 is always used with HSIC */ 303 phy_type = "hsic"; 304 }; 305 306 ehci2: usb@00a02000 { 307 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 308 reg = <0x00a02000 0x100>; 309 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&usb_clocks CLK_BUS_HCI2>; 311 resets = <&usb_clocks RST_USB2_HCI>; 312 phys = <&usbphy3>; 313 phy-names = "usb"; 314 status = "disabled"; 315 }; 316 317 ohci2: usb@00a02400 { 318 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 319 reg = <0x00a02400 0x100>; 320 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&usb_clocks CLK_BUS_HCI2>, 322 <&usb_clocks CLK_USB_OHCI2>; 323 resets = <&usb_clocks RST_USB2_HCI>; 324 phys = <&usbphy3>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 usbphy3: phy@00a02800 { 330 compatible = "allwinner,sun9i-a80-usb-phy"; 331 reg = <0x00a02800 0x4>; 332 clocks = <&usb_clocks CLK_USB2_HSIC>, 333 <&usb_clocks CLK_USB_HSIC>, 334 <&usb_clocks CLK_USB2_PHY>; 335 clock-names = "hsic_480M", 336 "hsic_12M", 337 "phy"; 338 resets = <&usb_clocks RST_USB2_HSIC>, 339 <&usb_clocks RST_USB2_PHY>; 340 reset-names = "hsic", 341 "phy"; 342 status = "disabled"; 343 #phy-cells = <0>; 344 }; 345 346 usb_clocks: clock@00a08000 { 347 compatible = "allwinner,sun9i-a80-usb-clks"; 348 reg = <0x00a08000 0x8>; 349 clocks = <&ccu CLK_BUS_USB>, <&osc24M>; 350 clock-names = "bus", "hosc"; 351 #clock-cells = <1>; 352 #reset-cells = <1>; 353 }; 354 355 mmc0: mmc@01c0f000 { 356 compatible = "allwinner,sun9i-a80-mmc"; 357 reg = <0x01c0f000 0x1000>; 358 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, 359 <&ccu CLK_MMC0_OUTPUT>, 360 <&ccu CLK_MMC0_SAMPLE>; 361 clock-names = "ahb", "mmc", "output", "sample"; 362 resets = <&mmc_config_clk 0>; 363 reset-names = "ahb"; 364 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 365 status = "disabled"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 }; 369 370 mmc1: mmc@01c10000 { 371 compatible = "allwinner,sun9i-a80-mmc"; 372 reg = <0x01c10000 0x1000>; 373 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, 374 <&ccu CLK_MMC1_OUTPUT>, 375 <&ccu CLK_MMC1_SAMPLE>; 376 clock-names = "ahb", "mmc", "output", "sample"; 377 resets = <&mmc_config_clk 1>; 378 reset-names = "ahb"; 379 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 380 status = "disabled"; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 }; 384 385 mmc2: mmc@01c11000 { 386 compatible = "allwinner,sun9i-a80-mmc"; 387 reg = <0x01c11000 0x1000>; 388 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, 389 <&ccu CLK_MMC2_OUTPUT>, 390 <&ccu CLK_MMC2_SAMPLE>; 391 clock-names = "ahb", "mmc", "output", "sample"; 392 resets = <&mmc_config_clk 2>; 393 reset-names = "ahb"; 394 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 }; 399 400 mmc3: mmc@01c12000 { 401 compatible = "allwinner,sun9i-a80-mmc"; 402 reg = <0x01c12000 0x1000>; 403 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, 404 <&ccu CLK_MMC3_OUTPUT>, 405 <&ccu CLK_MMC3_SAMPLE>; 406 clock-names = "ahb", "mmc", "output", "sample"; 407 resets = <&mmc_config_clk 3>; 408 reset-names = "ahb"; 409 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 410 status = "disabled"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 }; 414 415 mmc_config_clk: clk@01c13000 { 416 compatible = "allwinner,sun9i-a80-mmc-config-clk"; 417 reg = <0x01c13000 0x10>; 418 clocks = <&ccu CLK_BUS_MMC>; 419 clock-names = "ahb"; 420 resets = <&ccu RST_BUS_MMC>; 421 reset-names = "ahb"; 422 #clock-cells = <1>; 423 #reset-cells = <1>; 424 clock-output-names = "mmc0_config", "mmc1_config", 425 "mmc2_config", "mmc3_config"; 426 }; 427 428 gic: interrupt-controller@01c41000 { 429 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 430 reg = <0x01c41000 0x1000>, 431 <0x01c42000 0x2000>, 432 <0x01c44000 0x2000>, 433 <0x01c46000 0x2000>; 434 interrupt-controller; 435 #interrupt-cells = <3>; 436 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 437 }; 438 439 de_clocks: clock@03000000 { 440 compatible = "allwinner,sun9i-a80-de-clks"; 441 reg = <0x03000000 0x30>; 442 clocks = <&ccu CLK_DE>, 443 <&ccu CLK_SDRAM>, 444 <&ccu CLK_BUS_DE>; 445 clock-names = "mod", 446 "dram", 447 "bus"; 448 resets = <&ccu RST_BUS_DE>; 449 #clock-cells = <1>; 450 #reset-cells = <1>; 451 }; 452 453 ccu: clock@06000000 { 454 compatible = "allwinner,sun9i-a80-ccu"; 455 reg = <0x06000000 0x800>; 456 clocks = <&osc24M>, <&osc32k>; 457 clock-names = "hosc", "losc"; 458 #clock-cells = <1>; 459 #reset-cells = <1>; 460 }; 461 462 timer@06000c00 { 463 compatible = "allwinner,sun4i-a10-timer"; 464 reg = <0x06000c00 0xa0>; 465 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 471 472 clocks = <&osc24M>; 473 }; 474 475 wdt: watchdog@06000ca0 { 476 compatible = "allwinner,sun6i-a31-wdt"; 477 reg = <0x06000ca0 0x20>; 478 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 479 }; 480 481 pio: pinctrl@06000800 { 482 compatible = "allwinner,sun9i-a80-pinctrl"; 483 reg = <0x06000800 0x400>; 484 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 490 clock-names = "apb", "hosc", "losc"; 491 gpio-controller; 492 interrupt-controller; 493 #interrupt-cells = <3>; 494 #size-cells = <0>; 495 #gpio-cells = <3>; 496 497 i2c3_pins_a: i2c3@0 { 498 pins = "PG10", "PG11"; 499 function = "i2c3"; 500 }; 501 502 mmc0_pins: mmc0 { 503 pins = "PF0", "PF1" ,"PF2", "PF3", 504 "PF4", "PF5"; 505 function = "mmc0"; 506 drive-strength = <30>; 507 bias-pull-up; 508 }; 509 510 mmc1_pins: mmc1 { 511 pins = "PG0", "PG1" ,"PG2", "PG3", 512 "PG4", "PG5"; 513 function = "mmc1"; 514 drive-strength = <30>; 515 bias-pull-up; 516 }; 517 518 mmc2_8bit_pins: mmc2_8bit { 519 pins = "PC6", "PC7", "PC8", "PC9", 520 "PC10", "PC11", "PC12", 521 "PC13", "PC14", "PC15", 522 "PC16"; 523 function = "mmc2"; 524 drive-strength = <30>; 525 bias-pull-up; 526 }; 527 528 uart0_pins_a: uart0@0 { 529 pins = "PH12", "PH13"; 530 function = "uart0"; 531 }; 532 533 uart4_pins_a: uart4@0 { 534 pins = "PG12", "PG13", "PG14", "PG15"; 535 function = "uart4"; 536 }; 537 }; 538 539 uart0: serial@07000000 { 540 compatible = "snps,dw-apb-uart"; 541 reg = <0x07000000 0x400>; 542 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 543 reg-shift = <2>; 544 reg-io-width = <4>; 545 clocks = <&ccu CLK_BUS_UART0>; 546 resets = <&ccu RST_BUS_UART0>; 547 status = "disabled"; 548 }; 549 550 uart1: serial@07000400 { 551 compatible = "snps,dw-apb-uart"; 552 reg = <0x07000400 0x400>; 553 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 554 reg-shift = <2>; 555 reg-io-width = <4>; 556 clocks = <&ccu CLK_BUS_UART1>; 557 resets = <&ccu RST_BUS_UART1>; 558 status = "disabled"; 559 }; 560 561 uart2: serial@07000800 { 562 compatible = "snps,dw-apb-uart"; 563 reg = <0x07000800 0x400>; 564 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 565 reg-shift = <2>; 566 reg-io-width = <4>; 567 clocks = <&ccu CLK_BUS_UART2>; 568 resets = <&ccu RST_BUS_UART2>; 569 status = "disabled"; 570 }; 571 572 uart3: serial@07000c00 { 573 compatible = "snps,dw-apb-uart"; 574 reg = <0x07000c00 0x400>; 575 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 576 reg-shift = <2>; 577 reg-io-width = <4>; 578 clocks = <&ccu CLK_BUS_UART3>; 579 resets = <&ccu RST_BUS_UART3>; 580 status = "disabled"; 581 }; 582 583 uart4: serial@07001000 { 584 compatible = "snps,dw-apb-uart"; 585 reg = <0x07001000 0x400>; 586 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 587 reg-shift = <2>; 588 reg-io-width = <4>; 589 clocks = <&ccu CLK_BUS_UART4>; 590 resets = <&ccu RST_BUS_UART4>; 591 status = "disabled"; 592 }; 593 594 uart5: serial@07001400 { 595 compatible = "snps,dw-apb-uart"; 596 reg = <0x07001400 0x400>; 597 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 598 reg-shift = <2>; 599 reg-io-width = <4>; 600 clocks = <&ccu CLK_BUS_UART5>; 601 resets = <&ccu RST_BUS_UART5>; 602 status = "disabled"; 603 }; 604 605 i2c0: i2c@07002800 { 606 compatible = "allwinner,sun6i-a31-i2c"; 607 reg = <0x07002800 0x400>; 608 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&ccu CLK_BUS_I2C0>; 610 resets = <&ccu RST_BUS_I2C0>; 611 status = "disabled"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 }; 615 616 i2c1: i2c@07002c00 { 617 compatible = "allwinner,sun6i-a31-i2c"; 618 reg = <0x07002c00 0x400>; 619 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_I2C1>; 621 resets = <&ccu RST_BUS_I2C1>; 622 status = "disabled"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 }; 626 627 i2c2: i2c@07003000 { 628 compatible = "allwinner,sun6i-a31-i2c"; 629 reg = <0x07003000 0x400>; 630 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&ccu CLK_BUS_I2C2>; 632 resets = <&ccu RST_BUS_I2C2>; 633 status = "disabled"; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 }; 637 638 i2c3: i2c@07003400 { 639 compatible = "allwinner,sun6i-a31-i2c"; 640 reg = <0x07003400 0x400>; 641 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&ccu CLK_BUS_I2C3>; 643 resets = <&ccu RST_BUS_I2C3>; 644 status = "disabled"; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 }; 648 649 i2c4: i2c@07003800 { 650 compatible = "allwinner,sun6i-a31-i2c"; 651 reg = <0x07003800 0x400>; 652 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&ccu CLK_BUS_I2C4>; 654 resets = <&ccu RST_BUS_I2C4>; 655 status = "disabled"; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 }; 659 660 r_wdt: watchdog@08001000 { 661 compatible = "allwinner,sun6i-a31-wdt"; 662 reg = <0x08001000 0x20>; 663 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 664 }; 665 666 apbs_rst: reset@080014b0 { 667 reg = <0x080014b0 0x4>; 668 compatible = "allwinner,sun6i-a31-clock-reset"; 669 #reset-cells = <1>; 670 }; 671 672 nmi_intc: interrupt-controller@080015a0 { 673 compatible = "allwinner,sun9i-a80-nmi"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 reg = <0x080015a0 0xc>; 677 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 678 }; 679 680 r_ir: ir@08002000 { 681 compatible = "allwinner,sun5i-a13-ir"; 682 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&r_ir_pins>; 685 clocks = <&apbs_gates 1>, <&r_ir_clk>; 686 clock-names = "apb", "ir"; 687 resets = <&apbs_rst 1>; 688 reg = <0x08002000 0x40>; 689 status = "disabled"; 690 }; 691 692 r_uart: serial@08002800 { 693 compatible = "snps,dw-apb-uart"; 694 reg = <0x08002800 0x400>; 695 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 696 reg-shift = <2>; 697 reg-io-width = <4>; 698 clocks = <&apbs_gates 4>; 699 resets = <&apbs_rst 4>; 700 status = "disabled"; 701 }; 702 703 r_pio: pinctrl@08002c00 { 704 compatible = "allwinner,sun9i-a80-r-pinctrl"; 705 reg = <0x08002c00 0x400>; 706 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; 709 clock-names = "apb", "hosc", "losc"; 710 resets = <&apbs_rst 0>; 711 gpio-controller; 712 interrupt-controller; 713 #interrupt-cells = <3>; 714 #gpio-cells = <3>; 715 716 r_ir_pins: r_ir { 717 pins = "PL6"; 718 function = "s_cir_rx"; 719 }; 720 721 r_rsb_pins: r_rsb { 722 pins = "PN0", "PN1"; 723 function = "s_rsb"; 724 drive-strength = <20>; 725 bias-pull-up; 726 }; 727 }; 728 729 r_rsb: i2c@08003400 { 730 compatible = "allwinner,sun8i-a23-rsb"; 731 reg = <0x08003400 0x400>; 732 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&apbs_gates 3>; 734 clock-frequency = <3000000>; 735 resets = <&apbs_rst 3>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&r_rsb_pins>; 738 status = "disabled"; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 }; 742 }; 743}; 744