1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * CoreTile Express A15x2 A7x3 6 * Cortex-A15_A7 MPCore (V2P-CA15_A7) 7 * 8 * HBI-0249A 9 */ 10 11/dts-v1/; 12 13/ { 14 model = "V2P-CA15_CA7"; 15 arm,hbi = <0x249>; 16 arm,vexpress,site = <0xf>; 17 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 aliases { 25 serial0 = &v2m_serial0; 26 serial1 = &v2m_serial1; 27 serial2 = &v2m_serial2; 28 serial3 = &v2m_serial3; 29 i2c0 = &v2m_i2c_dvi; 30 i2c1 = &v2m_i2c_pcie; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a15"; 40 reg = <0>; 41 cci-control-port = <&cci_control1>; 42 cpu-idle-states = <&CLUSTER_SLEEP_BIG>; 43 capacity-dmips-mhz = <1024>; 44 sched-energy-costs = <&CPU_COST_A15 &CLUSTER_COST_A15>; 45 }; 46 47 cpu1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a15"; 50 reg = <1>; 51 cci-control-port = <&cci_control1>; 52 cpu-idle-states = <&CLUSTER_SLEEP_BIG>; 53 capacity-dmips-mhz = <1024>; 54 sched-energy-costs = <&CPU_COST_A15 &CLUSTER_COST_A15>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x100>; 61 cci-control-port = <&cci_control2>; 62 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; 63 capacity-dmips-mhz = <516>; 64 sched-energy-costs = <&CPU_COST_A7 &CLUSTER_COST_A7>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a7"; 70 reg = <0x101>; 71 cci-control-port = <&cci_control2>; 72 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; 73 capacity-dmips-mhz = <516>; 74 sched-energy-costs = <&CPU_COST_A7 &CLUSTER_COST_A7>; 75 }; 76 77 cpu4: cpu@4 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a7"; 80 reg = <0x102>; 81 cci-control-port = <&cci_control2>; 82 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; 83 capacity-dmips-mhz = <516>; 84 sched-energy-costs = <&CPU_COST_A7 &CLUSTER_COST_A7>; 85 }; 86 87 idle-states { 88 CLUSTER_SLEEP_BIG: cluster-sleep-big { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 entry-latency-us = <1000>; 92 exit-latency-us = <700>; 93 min-residency-us = <2000>; 94 }; 95 96 CLUSTER_SLEEP_LITTLE: cluster-sleep-little { 97 compatible = "arm,idle-state"; 98 local-timer-stop; 99 entry-latency-us = <1000>; 100 exit-latency-us = <500>; 101 min-residency-us = <2500>; 102 }; 103 }; 104 105 energy-costs { 106 CPU_COST_A15: core-cost0 { 107 busy-cost-data = < 108 426 2021 109 512 2312 110 597 2756 111 682 3125 112 768 3524 113 853 3846 114 938 5177 115 1024 6997 116 >; 117 idle-cost-data = < 118 0 119 0 120 0 121 >; 122 }; 123 CPU_COST_A7: core-cost1 { 124 busy-cost-data = < 125 150 187 126 172 275 127 215 334 128 258 407 129 301 447 130 344 549 131 387 761 132 430 1024 133 >; 134 idle-cost-data = < 135 0 136 0 137 0 138 >; 139 }; 140 CLUSTER_COST_A15: cluster-cost0 { 141 busy-cost-data = < 142 426 7920 143 512 8165 144 597 8172 145 682 8195 146 768 8265 147 853 8446 148 938 11426 149 1024 15200 150 >; 151 idle-cost-data = < 152 70 153 70 154 25 155 >; 156 }; 157 CLUSTER_COST_A7: cluster-cost1 { 158 busy-cost-data = < 159 150 2967 160 172 2792 161 215 2810 162 258 2815 163 301 2919 164 344 2847 165 387 3917 166 430 4905 167 >; 168 idle-cost-data = < 169 25 170 25 171 10 172 >; 173 }; 174 }; 175 }; 176 177 memory@80000000 { 178 device_type = "memory"; 179 reg = <0 0x80000000 0 0x40000000>; 180 }; 181 182 wdt@2a490000 { 183 compatible = "arm,sp805", "arm,primecell"; 184 reg = <0 0x2a490000 0 0x1000>; 185 interrupts = <0 98 4>; 186 clocks = <&oscclk6a>, <&oscclk6a>; 187 clock-names = "wdogclk", "apb_pclk"; 188 }; 189 190 hdlcd@2b000000 { 191 compatible = "arm,hdlcd"; 192 reg = <0 0x2b000000 0 0x1000>; 193 interrupts = <0 85 4>; 194 clocks = <&hdlcd_clk>; 195 clock-names = "pxlclk"; 196 }; 197 198 memory-controller@2b0a0000 { 199 compatible = "arm,pl341", "arm,primecell"; 200 reg = <0 0x2b0a0000 0 0x1000>; 201 clocks = <&oscclk6a>; 202 clock-names = "apb_pclk"; 203 }; 204 205 gic: interrupt-controller@2c001000 { 206 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 207 #interrupt-cells = <3>; 208 #address-cells = <0>; 209 interrupt-controller; 210 reg = <0 0x2c001000 0 0x1000>, 211 <0 0x2c002000 0 0x2000>, 212 <0 0x2c004000 0 0x2000>, 213 <0 0x2c006000 0 0x2000>; 214 interrupts = <1 9 0xf04>; 215 }; 216 217 cci@2c090000 { 218 compatible = "arm,cci-400"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 reg = <0 0x2c090000 0 0x1000>; 222 ranges = <0x0 0x0 0x2c090000 0x10000>; 223 224 cci_control1: slave-if@4000 { 225 compatible = "arm,cci-400-ctrl-if"; 226 interface-type = "ace"; 227 reg = <0x4000 0x1000>; 228 }; 229 230 cci_control2: slave-if@5000 { 231 compatible = "arm,cci-400-ctrl-if"; 232 interface-type = "ace"; 233 reg = <0x5000 0x1000>; 234 }; 235 236 pmu@9000 { 237 compatible = "arm,cci-400-pmu,r0"; 238 reg = <0x9000 0x5000>; 239 interrupts = <0 105 4>, 240 <0 101 4>, 241 <0 102 4>, 242 <0 103 4>, 243 <0 104 4>; 244 }; 245 }; 246 247 memory-controller@7ffd0000 { 248 compatible = "arm,pl354", "arm,primecell"; 249 reg = <0 0x7ffd0000 0 0x1000>; 250 interrupts = <0 86 4>, 251 <0 87 4>; 252 clocks = <&oscclk6a>; 253 clock-names = "apb_pclk"; 254 }; 255 256 dma@7ff00000 { 257 compatible = "arm,pl330", "arm,primecell"; 258 reg = <0 0x7ff00000 0 0x1000>; 259 interrupts = <0 92 4>, 260 <0 88 4>, 261 <0 89 4>, 262 <0 90 4>, 263 <0 91 4>; 264 clocks = <&oscclk6a>; 265 clock-names = "apb_pclk"; 266 }; 267 268 scc@7fff0000 { 269 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; 270 reg = <0 0x7fff0000 0 0x1000>; 271 interrupts = <0 95 4>; 272 }; 273 274 timer { 275 compatible = "arm,armv7-timer"; 276 interrupts = <1 13 0xf08>, 277 <1 14 0xf08>, 278 <1 11 0xf08>, 279 <1 10 0xf08>; 280 }; 281 282 pmu_a15 { 283 compatible = "arm,cortex-a15-pmu"; 284 interrupts = <0 68 4>, 285 <0 69 4>; 286 interrupt-affinity = <&cpu0>, 287 <&cpu1>; 288 }; 289 290 pmu_a7 { 291 compatible = "arm,cortex-a7-pmu"; 292 interrupts = <0 128 4>, 293 <0 129 4>, 294 <0 130 4>; 295 interrupt-affinity = <&cpu2>, 296 <&cpu3>, 297 <&cpu4>; 298 }; 299 300 oscclk6a: oscclk6a { 301 /* Reference 24MHz clock */ 302 compatible = "fixed-clock"; 303 #clock-cells = <0>; 304 clock-frequency = <24000000>; 305 clock-output-names = "oscclk6a"; 306 }; 307 308 dcc { 309 compatible = "arm,vexpress,config-bus"; 310 arm,vexpress,config-bridge = <&v2m_sysreg>; 311 312 oscclk0 { 313 /* A15 PLL 0 reference clock */ 314 compatible = "arm,vexpress-osc"; 315 arm,vexpress-sysreg,func = <1 0>; 316 freq-range = <17000000 50000000>; 317 #clock-cells = <0>; 318 clock-output-names = "oscclk0"; 319 }; 320 321 oscclk1 { 322 /* A15 PLL 1 reference clock */ 323 compatible = "arm,vexpress-osc"; 324 arm,vexpress-sysreg,func = <1 1>; 325 freq-range = <17000000 50000000>; 326 #clock-cells = <0>; 327 clock-output-names = "oscclk1"; 328 }; 329 330 oscclk2 { 331 /* A7 PLL 0 reference clock */ 332 compatible = "arm,vexpress-osc"; 333 arm,vexpress-sysreg,func = <1 2>; 334 freq-range = <17000000 50000000>; 335 #clock-cells = <0>; 336 clock-output-names = "oscclk2"; 337 }; 338 339 oscclk3 { 340 /* A7 PLL 1 reference clock */ 341 compatible = "arm,vexpress-osc"; 342 arm,vexpress-sysreg,func = <1 3>; 343 freq-range = <17000000 50000000>; 344 #clock-cells = <0>; 345 clock-output-names = "oscclk3"; 346 }; 347 348 oscclk4 { 349 /* External AXI master clock */ 350 compatible = "arm,vexpress-osc"; 351 arm,vexpress-sysreg,func = <1 4>; 352 freq-range = <20000000 40000000>; 353 #clock-cells = <0>; 354 clock-output-names = "oscclk4"; 355 }; 356 357 hdlcd_clk: oscclk5 { 358 /* HDLCD PLL reference clock */ 359 compatible = "arm,vexpress-osc"; 360 arm,vexpress-sysreg,func = <1 5>; 361 freq-range = <23750000 165000000>; 362 #clock-cells = <0>; 363 clock-output-names = "oscclk5"; 364 }; 365 366 smbclk: oscclk6 { 367 /* Static memory controller clock */ 368 compatible = "arm,vexpress-osc"; 369 arm,vexpress-sysreg,func = <1 6>; 370 freq-range = <20000000 40000000>; 371 #clock-cells = <0>; 372 clock-output-names = "oscclk6"; 373 }; 374 375 oscclk7 { 376 /* SYS PLL reference clock */ 377 compatible = "arm,vexpress-osc"; 378 arm,vexpress-sysreg,func = <1 7>; 379 freq-range = <17000000 50000000>; 380 #clock-cells = <0>; 381 clock-output-names = "oscclk7"; 382 }; 383 384 oscclk8 { 385 /* DDR2 PLL reference clock */ 386 compatible = "arm,vexpress-osc"; 387 arm,vexpress-sysreg,func = <1 8>; 388 freq-range = <20000000 50000000>; 389 #clock-cells = <0>; 390 clock-output-names = "oscclk8"; 391 }; 392 393 volt-a15 { 394 /* A15 CPU core voltage */ 395 compatible = "arm,vexpress-volt"; 396 arm,vexpress-sysreg,func = <2 0>; 397 regulator-name = "A15 Vcore"; 398 regulator-min-microvolt = <800000>; 399 regulator-max-microvolt = <1050000>; 400 regulator-always-on; 401 label = "A15 Vcore"; 402 }; 403 404 volt-a7 { 405 /* A7 CPU core voltage */ 406 compatible = "arm,vexpress-volt"; 407 arm,vexpress-sysreg,func = <2 1>; 408 regulator-name = "A7 Vcore"; 409 regulator-min-microvolt = <800000>; 410 regulator-max-microvolt = <1050000>; 411 regulator-always-on; 412 label = "A7 Vcore"; 413 }; 414 415 amp-a15 { 416 /* Total current for the two A15 cores */ 417 compatible = "arm,vexpress-amp"; 418 arm,vexpress-sysreg,func = <3 0>; 419 label = "A15 Icore"; 420 }; 421 422 amp-a7 { 423 /* Total current for the three A7 cores */ 424 compatible = "arm,vexpress-amp"; 425 arm,vexpress-sysreg,func = <3 1>; 426 label = "A7 Icore"; 427 }; 428 429 temp-dcc { 430 /* DCC internal temperature */ 431 compatible = "arm,vexpress-temp"; 432 arm,vexpress-sysreg,func = <4 0>; 433 label = "DCC"; 434 }; 435 436 power-a15 { 437 /* Total power for the two A15 cores */ 438 compatible = "arm,vexpress-power"; 439 arm,vexpress-sysreg,func = <12 0>; 440 label = "A15 Pcore"; 441 }; 442 443 power-a7 { 444 /* Total power for the three A7 cores */ 445 compatible = "arm,vexpress-power"; 446 arm,vexpress-sysreg,func = <12 1>; 447 label = "A7 Pcore"; 448 }; 449 450 energy-a15 { 451 /* Total energy for the two A15 cores */ 452 compatible = "arm,vexpress-energy"; 453 arm,vexpress-sysreg,func = <13 0>, <13 1>; 454 label = "A15 Jcore"; 455 }; 456 457 energy-a7 { 458 /* Total energy for the three A7 cores */ 459 compatible = "arm,vexpress-energy"; 460 arm,vexpress-sysreg,func = <13 2>, <13 3>; 461 label = "A7 Jcore"; 462 }; 463 }; 464 465 etb@20010000 { 466 compatible = "arm,coresight-etb10", "arm,primecell"; 467 reg = <0 0x20010000 0 0x1000>; 468 469 clocks = <&oscclk6a>; 470 clock-names = "apb_pclk"; 471 port { 472 etb_in_port: endpoint { 473 slave-mode; 474 remote-endpoint = <&replicator_out_port0>; 475 }; 476 }; 477 }; 478 479 tpiu@20030000 { 480 compatible = "arm,coresight-tpiu", "arm,primecell"; 481 reg = <0 0x20030000 0 0x1000>; 482 483 clocks = <&oscclk6a>; 484 clock-names = "apb_pclk"; 485 port { 486 tpiu_in_port: endpoint { 487 slave-mode; 488 remote-endpoint = <&replicator_out_port1>; 489 }; 490 }; 491 }; 492 493 replicator { 494 /* non-configurable replicators don't show up on the 495 * AMBA bus. As such no need to add "arm,primecell". 496 */ 497 compatible = "arm,coresight-replicator"; 498 499 ports { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 503 /* replicator output ports */ 504 port@0 { 505 reg = <0>; 506 replicator_out_port0: endpoint { 507 remote-endpoint = <&etb_in_port>; 508 }; 509 }; 510 511 port@1 { 512 reg = <1>; 513 replicator_out_port1: endpoint { 514 remote-endpoint = <&tpiu_in_port>; 515 }; 516 }; 517 518 /* replicator input port */ 519 port@2 { 520 reg = <0>; 521 replicator_in_port0: endpoint { 522 slave-mode; 523 remote-endpoint = <&funnel_out_port0>; 524 }; 525 }; 526 }; 527 }; 528 529 funnel@20040000 { 530 compatible = "arm,coresight-funnel", "arm,primecell"; 531 reg = <0 0x20040000 0 0x1000>; 532 533 clocks = <&oscclk6a>; 534 clock-names = "apb_pclk"; 535 ports { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 539 /* funnel output port */ 540 port@0 { 541 reg = <0>; 542 funnel_out_port0: endpoint { 543 remote-endpoint = 544 <&replicator_in_port0>; 545 }; 546 }; 547 548 /* funnel input ports */ 549 port@1 { 550 reg = <0>; 551 funnel_in_port0: endpoint { 552 slave-mode; 553 remote-endpoint = <&ptm0_out_port>; 554 }; 555 }; 556 557 port@2 { 558 reg = <1>; 559 funnel_in_port1: endpoint { 560 slave-mode; 561 remote-endpoint = <&ptm1_out_port>; 562 }; 563 }; 564 565 port@3 { 566 reg = <2>; 567 funnel_in_port2: endpoint { 568 slave-mode; 569 remote-endpoint = <&etm0_out_port>; 570 }; 571 }; 572 573 /* Input port #3 is for ITM, not supported here */ 574 575 port@4 { 576 reg = <4>; 577 funnel_in_port4: endpoint { 578 slave-mode; 579 remote-endpoint = <&etm1_out_port>; 580 }; 581 }; 582 583 port@5 { 584 reg = <5>; 585 funnel_in_port5: endpoint { 586 slave-mode; 587 remote-endpoint = <&etm2_out_port>; 588 }; 589 }; 590 }; 591 }; 592 593 ptm@2201c000 { 594 compatible = "arm,coresight-etm3x", "arm,primecell"; 595 reg = <0 0x2201c000 0 0x1000>; 596 597 cpu = <&cpu0>; 598 clocks = <&oscclk6a>; 599 clock-names = "apb_pclk"; 600 port { 601 ptm0_out_port: endpoint { 602 remote-endpoint = <&funnel_in_port0>; 603 }; 604 }; 605 }; 606 607 ptm@2201d000 { 608 compatible = "arm,coresight-etm3x", "arm,primecell"; 609 reg = <0 0x2201d000 0 0x1000>; 610 611 cpu = <&cpu1>; 612 clocks = <&oscclk6a>; 613 clock-names = "apb_pclk"; 614 port { 615 ptm1_out_port: endpoint { 616 remote-endpoint = <&funnel_in_port1>; 617 }; 618 }; 619 }; 620 621 etm@2203c000 { 622 compatible = "arm,coresight-etm3x", "arm,primecell"; 623 reg = <0 0x2203c000 0 0x1000>; 624 625 cpu = <&cpu2>; 626 clocks = <&oscclk6a>; 627 clock-names = "apb_pclk"; 628 port { 629 etm0_out_port: endpoint { 630 remote-endpoint = <&funnel_in_port2>; 631 }; 632 }; 633 }; 634 635 etm@2203d000 { 636 compatible = "arm,coresight-etm3x", "arm,primecell"; 637 reg = <0 0x2203d000 0 0x1000>; 638 639 cpu = <&cpu3>; 640 clocks = <&oscclk6a>; 641 clock-names = "apb_pclk"; 642 port { 643 etm1_out_port: endpoint { 644 remote-endpoint = <&funnel_in_port4>; 645 }; 646 }; 647 }; 648 649 etm@2203e000 { 650 compatible = "arm,coresight-etm3x", "arm,primecell"; 651 reg = <0 0x2203e000 0 0x1000>; 652 653 cpu = <&cpu4>; 654 clocks = <&oscclk6a>; 655 clock-names = "apb_pclk"; 656 port { 657 etm2_out_port: endpoint { 658 remote-endpoint = <&funnel_in_port5>; 659 }; 660 }; 661 }; 662 663 smb@8000000 { 664 compatible = "simple-bus"; 665 666 #address-cells = <2>; 667 #size-cells = <1>; 668 ranges = <0 0 0 0x08000000 0x04000000>, 669 <1 0 0 0x14000000 0x04000000>, 670 <2 0 0 0x18000000 0x04000000>, 671 <3 0 0 0x1c000000 0x04000000>, 672 <4 0 0 0x0c000000 0x04000000>, 673 <5 0 0 0x10000000 0x04000000>; 674 675 #interrupt-cells = <1>; 676 interrupt-map-mask = <0 0 63>; 677 interrupt-map = <0 0 0 &gic 0 0 4>, 678 <0 0 1 &gic 0 1 4>, 679 <0 0 2 &gic 0 2 4>, 680 <0 0 3 &gic 0 3 4>, 681 <0 0 4 &gic 0 4 4>, 682 <0 0 5 &gic 0 5 4>, 683 <0 0 6 &gic 0 6 4>, 684 <0 0 7 &gic 0 7 4>, 685 <0 0 8 &gic 0 8 4>, 686 <0 0 9 &gic 0 9 4>, 687 <0 0 10 &gic 0 10 4>, 688 <0 0 11 &gic 0 11 4>, 689 <0 0 12 &gic 0 12 4>, 690 <0 0 13 &gic 0 13 4>, 691 <0 0 14 &gic 0 14 4>, 692 <0 0 15 &gic 0 15 4>, 693 <0 0 16 &gic 0 16 4>, 694 <0 0 17 &gic 0 17 4>, 695 <0 0 18 &gic 0 18 4>, 696 <0 0 19 &gic 0 19 4>, 697 <0 0 20 &gic 0 20 4>, 698 <0 0 21 &gic 0 21 4>, 699 <0 0 22 &gic 0 22 4>, 700 <0 0 23 &gic 0 23 4>, 701 <0 0 24 &gic 0 24 4>, 702 <0 0 25 &gic 0 25 4>, 703 <0 0 26 &gic 0 26 4>, 704 <0 0 27 &gic 0 27 4>, 705 <0 0 28 &gic 0 28 4>, 706 <0 0 29 &gic 0 29 4>, 707 <0 0 30 &gic 0 30 4>, 708 <0 0 31 &gic 0 31 4>, 709 <0 0 32 &gic 0 32 4>, 710 <0 0 33 &gic 0 33 4>, 711 <0 0 34 &gic 0 34 4>, 712 <0 0 35 &gic 0 35 4>, 713 <0 0 36 &gic 0 36 4>, 714 <0 0 37 &gic 0 37 4>, 715 <0 0 38 &gic 0 38 4>, 716 <0 0 39 &gic 0 39 4>, 717 <0 0 40 &gic 0 40 4>, 718 <0 0 41 &gic 0 41 4>, 719 <0 0 42 &gic 0 42 4>; 720 721 /include/ "vexpress-v2m-rs1.dtsi" 722 }; 723 724 site2: hsb@40000000 { 725 compatible = "simple-bus"; 726 #address-cells = <1>; 727 #size-cells = <1>; 728 ranges = <0 0 0x40000000 0x3fef0000>; 729 #interrupt-cells = <1>; 730 interrupt-map-mask = <0 3>; 731 interrupt-map = <0 0 &gic 0 36 4>, 732 <0 1 &gic 0 37 4>, 733 <0 2 &gic 0 38 4>, 734 <0 3 &gic 0 39 4>; 735 }; 736}; 737