1 /*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/spi/spi.h>
18 #include <linux/platform_data/edma.h>
19 #include <linux/platform_data/gpio-davinci.h>
20 #include <linux/platform_data/spi-davinci.h>
21
22 #include <asm/mach/map.h>
23
24 #include <mach/cputype.h>
25 #include "psc.h"
26 #include <mach/mux.h>
27 #include <mach/irqs.h>
28 #include <mach/time.h>
29 #include <mach/serial.h>
30 #include <mach/common.h>
31
32 #include "davinci.h"
33 #include "clock.h"
34 #include "mux.h"
35 #include "asp.h"
36
37 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
38 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
39 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
40
41 /*
42 * Device specific clocks
43 */
44 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
45
46 static struct pll_data pll1_data = {
47 .num = 1,
48 .phys_base = DAVINCI_PLL1_BASE,
49 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
50 };
51
52 static struct pll_data pll2_data = {
53 .num = 2,
54 .phys_base = DAVINCI_PLL2_BASE,
55 .flags = PLL_HAS_PREDIV,
56 };
57
58 static struct clk ref_clk = {
59 .name = "ref_clk",
60 /* FIXME -- crystal rate is board-specific */
61 .rate = DM355_REF_FREQ,
62 };
63
64 static struct clk pll1_clk = {
65 .name = "pll1",
66 .parent = &ref_clk,
67 .flags = CLK_PLL,
68 .pll_data = &pll1_data,
69 };
70
71 static struct clk pll1_aux_clk = {
72 .name = "pll1_aux_clk",
73 .parent = &pll1_clk,
74 .flags = CLK_PLL | PRE_PLL,
75 };
76
77 static struct clk pll1_sysclk1 = {
78 .name = "pll1_sysclk1",
79 .parent = &pll1_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82 };
83
84 static struct clk pll1_sysclk2 = {
85 .name = "pll1_sysclk2",
86 .parent = &pll1_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV2,
89 };
90
91 static struct clk pll1_sysclk3 = {
92 .name = "pll1_sysclk3",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
96 };
97
98 static struct clk pll1_sysclk4 = {
99 .name = "pll1_sysclk4",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV4,
103 };
104
105 static struct clk pll1_sysclkbp = {
106 .name = "pll1_sysclkbp",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL | PRE_PLL,
109 .div_reg = BPDIV
110 };
111
112 static struct clk vpss_dac_clk = {
113 .name = "vpss_dac",
114 .parent = &pll1_sysclk3,
115 .lpsc = DM355_LPSC_VPSS_DAC,
116 };
117
118 static struct clk vpss_master_clk = {
119 .name = "vpss_master",
120 .parent = &pll1_sysclk4,
121 .lpsc = DAVINCI_LPSC_VPSSMSTR,
122 .flags = CLK_PSC,
123 };
124
125 static struct clk vpss_slave_clk = {
126 .name = "vpss_slave",
127 .parent = &pll1_sysclk4,
128 .lpsc = DAVINCI_LPSC_VPSSSLV,
129 };
130
131 static struct clk clkout1_clk = {
132 .name = "clkout1",
133 .parent = &pll1_aux_clk,
134 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135 };
136
137 static struct clk clkout2_clk = {
138 .name = "clkout2",
139 .parent = &pll1_sysclkbp,
140 };
141
142 static struct clk pll2_clk = {
143 .name = "pll2",
144 .parent = &ref_clk,
145 .flags = CLK_PLL,
146 .pll_data = &pll2_data,
147 };
148
149 static struct clk pll2_sysclk1 = {
150 .name = "pll2_sysclk1",
151 .parent = &pll2_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV1,
154 };
155
156 static struct clk pll2_sysclkbp = {
157 .name = "pll2_sysclkbp",
158 .parent = &pll2_clk,
159 .flags = CLK_PLL | PRE_PLL,
160 .div_reg = BPDIV
161 };
162
163 static struct clk clkout3_clk = {
164 .name = "clkout3",
165 .parent = &pll2_sysclkbp,
166 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167 };
168
169 static struct clk arm_clk = {
170 .name = "arm_clk",
171 .parent = &pll1_sysclk1,
172 .lpsc = DAVINCI_LPSC_ARM,
173 .flags = ALWAYS_ENABLED,
174 };
175
176 /*
177 * NOT LISTED below, and not touched by Linux
178 * - in SyncReset state by default
179 * .lpsc = DAVINCI_LPSC_TPCC,
180 * .lpsc = DAVINCI_LPSC_TPTC0,
181 * .lpsc = DAVINCI_LPSC_TPTC1,
182 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183 * .lpsc = DAVINCI_LPSC_MEMSTICK,
184 * - in Enabled state by default
185 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
192 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
193 */
194
195 static struct clk mjcp_clk = {
196 .name = "mjcp",
197 .parent = &pll1_sysclk1,
198 .lpsc = DAVINCI_LPSC_IMCOP,
199 };
200
201 static struct clk uart0_clk = {
202 .name = "uart0",
203 .parent = &pll1_aux_clk,
204 .lpsc = DAVINCI_LPSC_UART0,
205 };
206
207 static struct clk uart1_clk = {
208 .name = "uart1",
209 .parent = &pll1_aux_clk,
210 .lpsc = DAVINCI_LPSC_UART1,
211 };
212
213 static struct clk uart2_clk = {
214 .name = "uart2",
215 .parent = &pll1_sysclk2,
216 .lpsc = DAVINCI_LPSC_UART2,
217 };
218
219 static struct clk i2c_clk = {
220 .name = "i2c",
221 .parent = &pll1_aux_clk,
222 .lpsc = DAVINCI_LPSC_I2C,
223 };
224
225 static struct clk asp0_clk = {
226 .name = "asp0",
227 .parent = &pll1_sysclk2,
228 .lpsc = DAVINCI_LPSC_McBSP,
229 };
230
231 static struct clk asp1_clk = {
232 .name = "asp1",
233 .parent = &pll1_sysclk2,
234 .lpsc = DM355_LPSC_McBSP1,
235 };
236
237 static struct clk mmcsd0_clk = {
238 .name = "mmcsd0",
239 .parent = &pll1_sysclk2,
240 .lpsc = DAVINCI_LPSC_MMC_SD,
241 };
242
243 static struct clk mmcsd1_clk = {
244 .name = "mmcsd1",
245 .parent = &pll1_sysclk2,
246 .lpsc = DM355_LPSC_MMC_SD1,
247 };
248
249 static struct clk spi0_clk = {
250 .name = "spi0",
251 .parent = &pll1_sysclk2,
252 .lpsc = DAVINCI_LPSC_SPI,
253 };
254
255 static struct clk spi1_clk = {
256 .name = "spi1",
257 .parent = &pll1_sysclk2,
258 .lpsc = DM355_LPSC_SPI1,
259 };
260
261 static struct clk spi2_clk = {
262 .name = "spi2",
263 .parent = &pll1_sysclk2,
264 .lpsc = DM355_LPSC_SPI2,
265 };
266
267 static struct clk gpio_clk = {
268 .name = "gpio",
269 .parent = &pll1_sysclk2,
270 .lpsc = DAVINCI_LPSC_GPIO,
271 };
272
273 static struct clk aemif_clk = {
274 .name = "aemif",
275 .parent = &pll1_sysclk2,
276 .lpsc = DAVINCI_LPSC_AEMIF,
277 };
278
279 static struct clk pwm0_clk = {
280 .name = "pwm0",
281 .parent = &pll1_aux_clk,
282 .lpsc = DAVINCI_LPSC_PWM0,
283 };
284
285 static struct clk pwm1_clk = {
286 .name = "pwm1",
287 .parent = &pll1_aux_clk,
288 .lpsc = DAVINCI_LPSC_PWM1,
289 };
290
291 static struct clk pwm2_clk = {
292 .name = "pwm2",
293 .parent = &pll1_aux_clk,
294 .lpsc = DAVINCI_LPSC_PWM2,
295 };
296
297 static struct clk pwm3_clk = {
298 .name = "pwm3",
299 .parent = &pll1_aux_clk,
300 .lpsc = DM355_LPSC_PWM3,
301 };
302
303 static struct clk timer0_clk = {
304 .name = "timer0",
305 .parent = &pll1_aux_clk,
306 .lpsc = DAVINCI_LPSC_TIMER0,
307 };
308
309 static struct clk timer1_clk = {
310 .name = "timer1",
311 .parent = &pll1_aux_clk,
312 .lpsc = DAVINCI_LPSC_TIMER1,
313 };
314
315 static struct clk timer2_clk = {
316 .name = "timer2",
317 .parent = &pll1_aux_clk,
318 .lpsc = DAVINCI_LPSC_TIMER2,
319 .usecount = 1, /* REVISIT: why can't this be disabled? */
320 };
321
322 static struct clk timer3_clk = {
323 .name = "timer3",
324 .parent = &pll1_aux_clk,
325 .lpsc = DM355_LPSC_TIMER3,
326 };
327
328 static struct clk rto_clk = {
329 .name = "rto",
330 .parent = &pll1_aux_clk,
331 .lpsc = DM355_LPSC_RTO,
332 };
333
334 static struct clk usb_clk = {
335 .name = "usb",
336 .parent = &pll1_sysclk2,
337 .lpsc = DAVINCI_LPSC_USB,
338 };
339
340 static struct clk_lookup dm355_clks[] = {
341 CLK(NULL, "ref", &ref_clk),
342 CLK(NULL, "pll1", &pll1_clk),
343 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
344 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
345 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
346 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
347 CLK(NULL, "pll1_aux", &pll1_aux_clk),
348 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
349 CLK(NULL, "vpss_dac", &vpss_dac_clk),
350 CLK("vpss", "master", &vpss_master_clk),
351 CLK("vpss", "slave", &vpss_slave_clk),
352 CLK(NULL, "clkout1", &clkout1_clk),
353 CLK(NULL, "clkout2", &clkout2_clk),
354 CLK(NULL, "pll2", &pll2_clk),
355 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
356 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
357 CLK(NULL, "clkout3", &clkout3_clk),
358 CLK(NULL, "arm", &arm_clk),
359 CLK(NULL, "mjcp", &mjcp_clk),
360 CLK("serial8250.0", NULL, &uart0_clk),
361 CLK("serial8250.1", NULL, &uart1_clk),
362 CLK("serial8250.2", NULL, &uart2_clk),
363 CLK("i2c_davinci.1", NULL, &i2c_clk),
364 CLK("davinci-mcbsp.0", NULL, &asp0_clk),
365 CLK("davinci-mcbsp.1", NULL, &asp1_clk),
366 CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
367 CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
368 CLK("spi_davinci.0", NULL, &spi0_clk),
369 CLK("spi_davinci.1", NULL, &spi1_clk),
370 CLK("spi_davinci.2", NULL, &spi2_clk),
371 CLK(NULL, "gpio", &gpio_clk),
372 CLK(NULL, "aemif", &aemif_clk),
373 CLK(NULL, "pwm0", &pwm0_clk),
374 CLK(NULL, "pwm1", &pwm1_clk),
375 CLK(NULL, "pwm2", &pwm2_clk),
376 CLK(NULL, "pwm3", &pwm3_clk),
377 CLK(NULL, "timer0", &timer0_clk),
378 CLK(NULL, "timer1", &timer1_clk),
379 CLK("davinci-wdt", NULL, &timer2_clk),
380 CLK(NULL, "timer3", &timer3_clk),
381 CLK(NULL, "rto", &rto_clk),
382 CLK(NULL, "usb", &usb_clk),
383 CLK(NULL, NULL, NULL),
384 };
385
386 /*----------------------------------------------------------------------*/
387
388 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
389
390 static struct resource dm355_spi0_resources[] = {
391 {
392 .start = 0x01c66000,
393 .end = 0x01c667ff,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = IRQ_DM355_SPINT0_0,
398 .flags = IORESOURCE_IRQ,
399 },
400 };
401
402 static struct davinci_spi_platform_data dm355_spi0_pdata = {
403 .version = SPI_VERSION_1,
404 .num_chipselect = 2,
405 .cshold_bug = true,
406 .dma_event_q = EVENTQ_1,
407 .prescaler_limit = 1,
408 };
409 static struct platform_device dm355_spi0_device = {
410 .name = "spi_davinci",
411 .id = 0,
412 .dev = {
413 .dma_mask = &dm355_spi0_dma_mask,
414 .coherent_dma_mask = DMA_BIT_MASK(32),
415 .platform_data = &dm355_spi0_pdata,
416 },
417 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
418 .resource = dm355_spi0_resources,
419 };
420
dm355_init_spi0(unsigned chipselect_mask,const struct spi_board_info * info,unsigned len)421 void __init dm355_init_spi0(unsigned chipselect_mask,
422 const struct spi_board_info *info, unsigned len)
423 {
424 /* for now, assume we need MISO */
425 davinci_cfg_reg(DM355_SPI0_SDI);
426
427 /* not all slaves will be wired up */
428 if (chipselect_mask & BIT(0))
429 davinci_cfg_reg(DM355_SPI0_SDENA0);
430 if (chipselect_mask & BIT(1))
431 davinci_cfg_reg(DM355_SPI0_SDENA1);
432
433 spi_register_board_info(info, len);
434
435 platform_device_register(&dm355_spi0_device);
436 }
437
438 /*----------------------------------------------------------------------*/
439
440 #define INTMUX 0x18
441 #define EVTMUX 0x1c
442
443 /*
444 * Device specific mux setup
445 *
446 * soc description mux mode mode mux dbg
447 * reg offset mask mode
448 */
449 static const struct mux_config dm355_pins[] = {
450 #ifdef CONFIG_DAVINCI_MUX
451 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
452
453 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
454 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
455 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
456 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
457 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
458 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
459
460 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
461 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
462
463 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
464 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
465 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
466 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
467 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
468 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
469
470 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
471 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
472 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
473
474 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
475 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
476 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
477
478 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
479 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
480 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
481
482 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
483 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
484 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
485 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
486 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
487
488 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
489 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
490 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
491 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
492 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
493 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
494 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
495 #endif
496 };
497
498 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
499 [IRQ_DM355_CCDC_VDINT0] = 2,
500 [IRQ_DM355_CCDC_VDINT1] = 6,
501 [IRQ_DM355_CCDC_VDINT2] = 6,
502 [IRQ_DM355_IPIPE_HST] = 6,
503 [IRQ_DM355_H3AINT] = 6,
504 [IRQ_DM355_IPIPE_SDR] = 6,
505 [IRQ_DM355_IPIPEIFINT] = 6,
506 [IRQ_DM355_OSDINT] = 7,
507 [IRQ_DM355_VENCINT] = 6,
508 [IRQ_ASQINT] = 6,
509 [IRQ_IMXINT] = 6,
510 [IRQ_USBINT] = 4,
511 [IRQ_DM355_RTOINT] = 4,
512 [IRQ_DM355_UARTINT2] = 7,
513 [IRQ_DM355_TINT6] = 7,
514 [IRQ_CCINT0] = 5, /* dma */
515 [IRQ_CCERRINT] = 5, /* dma */
516 [IRQ_TCERRINT0] = 5, /* dma */
517 [IRQ_TCERRINT] = 5, /* dma */
518 [IRQ_DM355_SPINT2_1] = 7,
519 [IRQ_DM355_TINT7] = 4,
520 [IRQ_DM355_SDIOINT0] = 7,
521 [IRQ_MBXINT] = 7,
522 [IRQ_MBRINT] = 7,
523 [IRQ_MMCINT] = 7,
524 [IRQ_DM355_MMCINT1] = 7,
525 [IRQ_DM355_PWMINT3] = 7,
526 [IRQ_DDRINT] = 7,
527 [IRQ_AEMIFINT] = 7,
528 [IRQ_DM355_SDIOINT1] = 4,
529 [IRQ_TINT0_TINT12] = 2, /* clockevent */
530 [IRQ_TINT0_TINT34] = 2, /* clocksource */
531 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
532 [IRQ_TINT1_TINT34] = 7, /* system tick */
533 [IRQ_PWMINT0] = 7,
534 [IRQ_PWMINT1] = 7,
535 [IRQ_PWMINT2] = 7,
536 [IRQ_I2C] = 3,
537 [IRQ_UARTINT0] = 3,
538 [IRQ_UARTINT1] = 3,
539 [IRQ_DM355_SPINT0_0] = 3,
540 [IRQ_DM355_SPINT0_1] = 3,
541 [IRQ_DM355_GPIO0] = 3,
542 [IRQ_DM355_GPIO1] = 7,
543 [IRQ_DM355_GPIO2] = 4,
544 [IRQ_DM355_GPIO3] = 4,
545 [IRQ_DM355_GPIO4] = 7,
546 [IRQ_DM355_GPIO5] = 7,
547 [IRQ_DM355_GPIO6] = 7,
548 [IRQ_DM355_GPIO7] = 7,
549 [IRQ_DM355_GPIO8] = 7,
550 [IRQ_DM355_GPIO9] = 7,
551 [IRQ_DM355_GPIOBNK0] = 7,
552 [IRQ_DM355_GPIOBNK1] = 7,
553 [IRQ_DM355_GPIOBNK2] = 7,
554 [IRQ_DM355_GPIOBNK3] = 7,
555 [IRQ_DM355_GPIOBNK4] = 7,
556 [IRQ_DM355_GPIOBNK5] = 7,
557 [IRQ_DM355_GPIOBNK6] = 7,
558 [IRQ_COMMTX] = 7,
559 [IRQ_COMMRX] = 7,
560 [IRQ_EMUINT] = 7,
561 };
562
563 /*----------------------------------------------------------------------*/
564
565 static s8 queue_priority_mapping[][2] = {
566 /* {event queue no, Priority} */
567 {0, 3},
568 {1, 7},
569 {-1, -1},
570 };
571
572 static const struct dma_slave_map dm355_edma_map[] = {
573 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
574 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
575 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
576 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
577 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
578 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
579 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
580 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
581 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
582 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
583 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
584 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
585 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
586 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
587 };
588
589 static struct edma_soc_info dm355_edma_pdata = {
590 .queue_priority_mapping = queue_priority_mapping,
591 .default_queue = EVENTQ_1,
592 .slave_map = dm355_edma_map,
593 .slavecnt = ARRAY_SIZE(dm355_edma_map),
594 };
595
596 static struct resource edma_resources[] = {
597 {
598 .name = "edma3_cc",
599 .start = 0x01c00000,
600 .end = 0x01c00000 + SZ_64K - 1,
601 .flags = IORESOURCE_MEM,
602 },
603 {
604 .name = "edma3_tc0",
605 .start = 0x01c10000,
606 .end = 0x01c10000 + SZ_1K - 1,
607 .flags = IORESOURCE_MEM,
608 },
609 {
610 .name = "edma3_tc1",
611 .start = 0x01c10400,
612 .end = 0x01c10400 + SZ_1K - 1,
613 .flags = IORESOURCE_MEM,
614 },
615 {
616 .name = "edma3_ccint",
617 .start = IRQ_CCINT0,
618 .flags = IORESOURCE_IRQ,
619 },
620 {
621 .name = "edma3_ccerrint",
622 .start = IRQ_CCERRINT,
623 .flags = IORESOURCE_IRQ,
624 },
625 /* not using (or muxing) TC*_ERR */
626 };
627
628 static const struct platform_device_info dm355_edma_device __initconst = {
629 .name = "edma",
630 .id = 0,
631 .dma_mask = DMA_BIT_MASK(32),
632 .res = edma_resources,
633 .num_res = ARRAY_SIZE(edma_resources),
634 .data = &dm355_edma_pdata,
635 .size_data = sizeof(dm355_edma_pdata),
636 };
637
638 static struct resource dm355_asp1_resources[] = {
639 {
640 .name = "mpu",
641 .start = DAVINCI_ASP1_BASE,
642 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646 .start = DAVINCI_DMA_ASP1_TX,
647 .end = DAVINCI_DMA_ASP1_TX,
648 .flags = IORESOURCE_DMA,
649 },
650 {
651 .start = DAVINCI_DMA_ASP1_RX,
652 .end = DAVINCI_DMA_ASP1_RX,
653 .flags = IORESOURCE_DMA,
654 },
655 };
656
657 static struct platform_device dm355_asp1_device = {
658 .name = "davinci-mcbsp",
659 .id = 1,
660 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
661 .resource = dm355_asp1_resources,
662 };
663
dm355_ccdc_setup_pinmux(void)664 static void dm355_ccdc_setup_pinmux(void)
665 {
666 davinci_cfg_reg(DM355_VIN_PCLK);
667 davinci_cfg_reg(DM355_VIN_CAM_WEN);
668 davinci_cfg_reg(DM355_VIN_CAM_VD);
669 davinci_cfg_reg(DM355_VIN_CAM_HD);
670 davinci_cfg_reg(DM355_VIN_YIN_EN);
671 davinci_cfg_reg(DM355_VIN_CINL_EN);
672 davinci_cfg_reg(DM355_VIN_CINH_EN);
673 }
674
675 static struct resource dm355_vpss_resources[] = {
676 {
677 /* VPSS BL Base address */
678 .name = "vpss",
679 .start = 0x01c70800,
680 .end = 0x01c70800 + 0xff,
681 .flags = IORESOURCE_MEM,
682 },
683 {
684 /* VPSS CLK Base address */
685 .name = "vpss",
686 .start = 0x01c70000,
687 .end = 0x01c70000 + 0xf,
688 .flags = IORESOURCE_MEM,
689 },
690 };
691
692 static struct platform_device dm355_vpss_device = {
693 .name = "vpss",
694 .id = -1,
695 .dev.platform_data = "dm355_vpss",
696 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
697 .resource = dm355_vpss_resources,
698 };
699
700 static struct resource vpfe_resources[] = {
701 {
702 .start = IRQ_VDINT0,
703 .end = IRQ_VDINT0,
704 .flags = IORESOURCE_IRQ,
705 },
706 {
707 .start = IRQ_VDINT1,
708 .end = IRQ_VDINT1,
709 .flags = IORESOURCE_IRQ,
710 },
711 };
712
713 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
714 static struct resource dm355_ccdc_resource[] = {
715 /* CCDC Base address */
716 {
717 .flags = IORESOURCE_MEM,
718 .start = 0x01c70600,
719 .end = 0x01c70600 + 0x1ff,
720 },
721 };
722 static struct platform_device dm355_ccdc_dev = {
723 .name = "dm355_ccdc",
724 .id = -1,
725 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
726 .resource = dm355_ccdc_resource,
727 .dev = {
728 .dma_mask = &vpfe_capture_dma_mask,
729 .coherent_dma_mask = DMA_BIT_MASK(32),
730 .platform_data = dm355_ccdc_setup_pinmux,
731 },
732 };
733
734 static struct platform_device vpfe_capture_dev = {
735 .name = CAPTURE_DRV_NAME,
736 .id = -1,
737 .num_resources = ARRAY_SIZE(vpfe_resources),
738 .resource = vpfe_resources,
739 .dev = {
740 .dma_mask = &vpfe_capture_dma_mask,
741 .coherent_dma_mask = DMA_BIT_MASK(32),
742 },
743 };
744
745 static struct resource dm355_osd_resources[] = {
746 {
747 .start = DM355_OSD_BASE,
748 .end = DM355_OSD_BASE + 0x17f,
749 .flags = IORESOURCE_MEM,
750 },
751 };
752
753 static struct platform_device dm355_osd_dev = {
754 .name = DM355_VPBE_OSD_SUBDEV_NAME,
755 .id = -1,
756 .num_resources = ARRAY_SIZE(dm355_osd_resources),
757 .resource = dm355_osd_resources,
758 .dev = {
759 .dma_mask = &vpfe_capture_dma_mask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762 };
763
764 static struct resource dm355_venc_resources[] = {
765 {
766 .start = IRQ_VENCINT,
767 .end = IRQ_VENCINT,
768 .flags = IORESOURCE_IRQ,
769 },
770 /* venc registers io space */
771 {
772 .start = DM355_VENC_BASE,
773 .end = DM355_VENC_BASE + 0x17f,
774 .flags = IORESOURCE_MEM,
775 },
776 /* VDAC config register io space */
777 {
778 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
779 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
780 .flags = IORESOURCE_MEM,
781 },
782 };
783
784 static struct resource dm355_v4l2_disp_resources[] = {
785 {
786 .start = IRQ_VENCINT,
787 .end = IRQ_VENCINT,
788 .flags = IORESOURCE_IRQ,
789 },
790 /* venc registers io space */
791 {
792 .start = DM355_VENC_BASE,
793 .end = DM355_VENC_BASE + 0x17f,
794 .flags = IORESOURCE_MEM,
795 },
796 };
797
dm355_vpbe_setup_pinmux(u32 if_type,int field)798 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
799 {
800 switch (if_type) {
801 case MEDIA_BUS_FMT_SGRBG8_1X8:
802 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
803 break;
804 case MEDIA_BUS_FMT_YUYV10_1X20:
805 if (field)
806 davinci_cfg_reg(DM355_VOUT_FIELD);
807 else
808 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 davinci_cfg_reg(DM355_VOUT_COUTL_EN);
815 davinci_cfg_reg(DM355_VOUT_COUTH_EN);
816
817 return 0;
818 }
819
dm355_venc_setup_clock(enum vpbe_enc_timings_type type,unsigned int pclock)820 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
821 unsigned int pclock)
822 {
823 void __iomem *vpss_clk_ctrl_reg;
824
825 vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
826
827 switch (type) {
828 case VPBE_ENC_STD:
829 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
830 vpss_clk_ctrl_reg);
831 break;
832 case VPBE_ENC_DV_TIMINGS:
833 if (pclock > 27000000)
834 /*
835 * For HD, use external clock source since we cannot
836 * support HD mode with internal clocks.
837 */
838 writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 return 0;
845 }
846
847 static struct platform_device dm355_vpbe_display = {
848 .name = "vpbe-v4l2",
849 .id = -1,
850 .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
851 .resource = dm355_v4l2_disp_resources,
852 .dev = {
853 .dma_mask = &vpfe_capture_dma_mask,
854 .coherent_dma_mask = DMA_BIT_MASK(32),
855 },
856 };
857
858 static struct venc_platform_data dm355_venc_pdata = {
859 .setup_pinmux = dm355_vpbe_setup_pinmux,
860 .setup_clock = dm355_venc_setup_clock,
861 };
862
863 static struct platform_device dm355_venc_dev = {
864 .name = DM355_VPBE_VENC_SUBDEV_NAME,
865 .id = -1,
866 .num_resources = ARRAY_SIZE(dm355_venc_resources),
867 .resource = dm355_venc_resources,
868 .dev = {
869 .dma_mask = &vpfe_capture_dma_mask,
870 .coherent_dma_mask = DMA_BIT_MASK(32),
871 .platform_data = (void *)&dm355_venc_pdata,
872 },
873 };
874
875 static struct platform_device dm355_vpbe_dev = {
876 .name = "vpbe_controller",
877 .id = -1,
878 .dev = {
879 .dma_mask = &vpfe_capture_dma_mask,
880 .coherent_dma_mask = DMA_BIT_MASK(32),
881 },
882 };
883
884 static struct resource dm355_gpio_resources[] = {
885 { /* registers */
886 .start = DAVINCI_GPIO_BASE,
887 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
888 .flags = IORESOURCE_MEM,
889 },
890 { /* interrupt */
891 .start = IRQ_DM355_GPIOBNK0,
892 .end = IRQ_DM355_GPIOBNK6,
893 .flags = IORESOURCE_IRQ,
894 },
895 };
896
897 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
898 .ngpio = 104,
899 };
900
dm355_gpio_register(void)901 int __init dm355_gpio_register(void)
902 {
903 return davinci_gpio_register(dm355_gpio_resources,
904 ARRAY_SIZE(dm355_gpio_resources),
905 &dm355_gpio_platform_data);
906 }
907 /*----------------------------------------------------------------------*/
908
909 static struct map_desc dm355_io_desc[] = {
910 {
911 .virtual = IO_VIRT,
912 .pfn = __phys_to_pfn(IO_PHYS),
913 .length = IO_SIZE,
914 .type = MT_DEVICE
915 },
916 };
917
918 /* Contents of JTAG ID register used to identify exact cpu type */
919 static struct davinci_id dm355_ids[] = {
920 {
921 .variant = 0x0,
922 .part_no = 0xb73b,
923 .manufacturer = 0x00f,
924 .cpu_id = DAVINCI_CPU_ID_DM355,
925 .name = "dm355",
926 },
927 };
928
929 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
930
931 /*
932 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
933 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
934 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
935 * T1_TOP: Timer 1, top : <unused>
936 */
937 static struct davinci_timer_info dm355_timer_info = {
938 .timers = davinci_timer_instance,
939 .clockevent_id = T0_BOT,
940 .clocksource_id = T0_TOP,
941 };
942
943 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
944 {
945 .mapbase = DAVINCI_UART0_BASE,
946 .irq = IRQ_UARTINT0,
947 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
948 UPF_IOREMAP,
949 .iotype = UPIO_MEM,
950 .regshift = 2,
951 },
952 {
953 .flags = 0,
954 }
955 };
956 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
957 {
958 .mapbase = DAVINCI_UART1_BASE,
959 .irq = IRQ_UARTINT1,
960 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
961 UPF_IOREMAP,
962 .iotype = UPIO_MEM,
963 .regshift = 2,
964 },
965 {
966 .flags = 0,
967 }
968 };
969 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
970 {
971 .mapbase = DM355_UART2_BASE,
972 .irq = IRQ_DM355_UARTINT2,
973 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
974 UPF_IOREMAP,
975 .iotype = UPIO_MEM,
976 .regshift = 2,
977 },
978 {
979 .flags = 0,
980 }
981 };
982
983 struct platform_device dm355_serial_device[] = {
984 {
985 .name = "serial8250",
986 .id = PLAT8250_DEV_PLATFORM,
987 .dev = {
988 .platform_data = dm355_serial0_platform_data,
989 }
990 },
991 {
992 .name = "serial8250",
993 .id = PLAT8250_DEV_PLATFORM1,
994 .dev = {
995 .platform_data = dm355_serial1_platform_data,
996 }
997 },
998 {
999 .name = "serial8250",
1000 .id = PLAT8250_DEV_PLATFORM2,
1001 .dev = {
1002 .platform_data = dm355_serial2_platform_data,
1003 }
1004 },
1005 {
1006 }
1007 };
1008
1009 static struct davinci_soc_info davinci_soc_info_dm355 = {
1010 .io_desc = dm355_io_desc,
1011 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
1012 .jtag_id_reg = 0x01c40028,
1013 .ids = dm355_ids,
1014 .ids_num = ARRAY_SIZE(dm355_ids),
1015 .cpu_clks = dm355_clks,
1016 .psc_bases = dm355_psc_bases,
1017 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
1018 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1019 .pinmux_pins = dm355_pins,
1020 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
1021 .intc_base = DAVINCI_ARM_INTC_BASE,
1022 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1023 .intc_irq_prios = dm355_default_priorities,
1024 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1025 .timer_info = &dm355_timer_info,
1026 .sram_dma = 0x00010000,
1027 .sram_len = SZ_32K,
1028 };
1029
dm355_init_asp1(u32 evt_enable)1030 void __init dm355_init_asp1(u32 evt_enable)
1031 {
1032 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
1033 if (evt_enable & ASP1_TX_EVT_EN)
1034 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
1035
1036 if (evt_enable & ASP1_RX_EVT_EN)
1037 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
1038
1039 platform_device_register(&dm355_asp1_device);
1040 }
1041
dm355_init(void)1042 void __init dm355_init(void)
1043 {
1044 davinci_common_init(&davinci_soc_info_dm355);
1045 davinci_map_sysmod();
1046 davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
1047 }
1048
dm355_init_video(struct vpfe_config * vpfe_cfg,struct vpbe_config * vpbe_cfg)1049 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
1050 struct vpbe_config *vpbe_cfg)
1051 {
1052 if (vpfe_cfg || vpbe_cfg)
1053 platform_device_register(&dm355_vpss_device);
1054
1055 if (vpfe_cfg) {
1056 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1057 platform_device_register(&dm355_ccdc_dev);
1058 platform_device_register(&vpfe_capture_dev);
1059 }
1060
1061 if (vpbe_cfg) {
1062 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
1063 platform_device_register(&dm355_osd_dev);
1064 platform_device_register(&dm355_venc_dev);
1065 platform_device_register(&dm355_vpbe_dev);
1066 platform_device_register(&dm355_vpbe_display);
1067 }
1068
1069 return 0;
1070 }
1071
dm355_init_devices(void)1072 static int __init dm355_init_devices(void)
1073 {
1074 struct platform_device *edma_pdev;
1075 int ret = 0;
1076
1077 if (!cpu_is_davinci_dm355())
1078 return 0;
1079
1080 davinci_cfg_reg(DM355_INT_EDMA_CC);
1081 edma_pdev = platform_device_register_full(&dm355_edma_device);
1082 if (IS_ERR(edma_pdev)) {
1083 pr_warn("%s: Failed to register eDMA\n", __func__);
1084 return PTR_ERR(edma_pdev);
1085 }
1086
1087 ret = davinci_init_wdt();
1088 if (ret)
1089 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1090
1091 return ret;
1092 }
1093 postcore_initcall(dm355_init_devices);
1094