1 /*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * Common Codes for S3C64XX machines
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 /*
18 * NOTE: Code in this file is not used when booting with Device Tree support.
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_s3c.h>
28 #include <linux/platform_device.h>
29 #include <linux/reboot.h>
30 #include <linux/io.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/irq.h>
33 #include <linux/gpio.h>
34 #include <linux/irqchip/arm-vic.h>
35 #include <clocksource/samsung_pwm.h>
36
37 #include <asm/mach/arch.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_misc.h>
40
41 #include <mach/map.h>
42 #include <mach/irqs.h>
43 #include <mach/hardware.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/gpio-samsung.h>
46
47 #include <plat/cpu.h>
48 #include <plat/devs.h>
49 #include <plat/pm.h>
50 #include <plat/gpio-cfg.h>
51 #include <plat/pwm-core.h>
52 #include <plat/regs-irqtype.h>
53
54 #include "common.h"
55 #include "irq-uart.h"
56 #include "watchdog-reset.h"
57
58 /* External clock frequency */
59 static unsigned long xtal_f __ro_after_init = 12000000;
60 static unsigned long xusbxti_f __ro_after_init = 48000000;
61
s3c64xx_set_xtal_freq(unsigned long freq)62 void __init s3c64xx_set_xtal_freq(unsigned long freq)
63 {
64 xtal_f = freq;
65 }
66
s3c64xx_set_xusbxti_freq(unsigned long freq)67 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
68 {
69 xusbxti_f = freq;
70 }
71
72 /* uart registration process */
73
s3c64xx_init_uarts(struct s3c2410_uartcfg * cfg,int no)74 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
75 {
76 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
77 }
78
79 /* table of supported CPUs */
80
81 static const char name_s3c6400[] = "S3C6400";
82 static const char name_s3c6410[] = "S3C6410";
83
84 static struct cpu_table cpu_ids[] __initdata = {
85 {
86 .idcode = S3C6400_CPU_ID,
87 .idmask = S3C64XX_CPU_MASK,
88 .map_io = s3c6400_map_io,
89 .init_uarts = s3c64xx_init_uarts,
90 .init = s3c6400_init,
91 .name = name_s3c6400,
92 }, {
93 .idcode = S3C6410_CPU_ID,
94 .idmask = S3C64XX_CPU_MASK,
95 .map_io = s3c6410_map_io,
96 .init_uarts = s3c64xx_init_uarts,
97 .init = s3c6410_init,
98 .name = name_s3c6410,
99 },
100 };
101
102 /* minimal IO mapping */
103
104 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
105 #define UART_OFFS (S3C_PA_UART & 0xfffff)
106
107 static struct map_desc s3c_iodesc[] __initdata = {
108 {
109 .virtual = (unsigned long)S3C_VA_SYS,
110 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (unsigned long)S3C_VA_MEM,
115 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
120 .pfn = __phys_to_pfn(S3C_PA_UART),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = (unsigned long)VA_VIC0,
125 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
126 .length = SZ_16K,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = (unsigned long)VA_VIC1,
130 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
131 .length = SZ_16K,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = (unsigned long)S3C_VA_TIMER,
135 .pfn = __phys_to_pfn(S3C_PA_TIMER),
136 .length = SZ_16K,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (unsigned long)S3C64XX_VA_GPIO,
140 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
141 .length = SZ_4K,
142 .type = MT_DEVICE,
143 }, {
144 .virtual = (unsigned long)S3C64XX_VA_MODEM,
145 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
146 .length = SZ_4K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S3C_VA_WATCHDOG,
150 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
151 .length = SZ_4K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
155 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
156 .length = SZ_1K,
157 .type = MT_DEVICE,
158 },
159 };
160
161 static struct bus_type s3c64xx_subsys = {
162 .name = "s3c64xx-core",
163 .dev_name = "s3c64xx-core",
164 };
165
166 static struct device s3c64xx_dev = {
167 .bus = &s3c64xx_subsys,
168 };
169
170 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
171 .bits = 32,
172 .div_base = 0,
173 .has_tint_cstat = true,
174 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
175 };
176
samsung_set_timer_source(unsigned int event,unsigned int source)177 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
178 {
179 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
180 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
181 }
182
samsung_timer_init(void)183 void __init samsung_timer_init(void)
184 {
185 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
186 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
187 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
188 };
189
190 samsung_pwm_clocksource_init(S3C_VA_TIMER,
191 timer_irqs, &s3c64xx_pwm_variant);
192 }
193
194 /* read cpu identification code */
195
s3c64xx_init_io(struct map_desc * mach_desc,int size)196 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
197 {
198 /* initialise the io descriptors we need for initialisation */
199 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
200 iotable_init(mach_desc, size);
201
202 /* detect cpu id */
203 s3c64xx_init_cpu();
204
205 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
206
207 samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
208 }
209
s3c64xx_dev_init(void)210 static __init int s3c64xx_dev_init(void)
211 {
212 /* Not applicable when using DT. */
213 if (of_have_populated_dt() || !soc_is_s3c64xx())
214 return 0;
215
216 subsys_system_register(&s3c64xx_subsys, NULL);
217 return device_register(&s3c64xx_dev);
218 }
219 core_initcall(s3c64xx_dev_init);
220
221 /*
222 * setup the sources the vic should advertise resume
223 * for, even though it is not doing the wake
224 * (set_irq_wake needs to be valid)
225 */
226 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
227 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
228 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
229 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
230 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
231 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
232
s3c64xx_init_irq(u32 vic0_valid,u32 vic1_valid)233 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
234 {
235 /*
236 * FIXME: there is no better place to put this at the moment
237 * (s3c64xx_clk_init needs ioremap and must happen before init_time
238 * samsung_wdt_reset_init needs clocks)
239 */
240 s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
241 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
242
243 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
244
245 /* initialise the pair of VICs */
246 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
247 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
248 }
249
250 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
251 #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
252
s3c_irq_eint_mask(struct irq_data * data)253 static inline void s3c_irq_eint_mask(struct irq_data *data)
254 {
255 u32 mask;
256
257 mask = __raw_readl(S3C64XX_EINT0MASK);
258 mask |= (u32)data->chip_data;
259 __raw_writel(mask, S3C64XX_EINT0MASK);
260 }
261
s3c_irq_eint_unmask(struct irq_data * data)262 static void s3c_irq_eint_unmask(struct irq_data *data)
263 {
264 u32 mask;
265
266 mask = __raw_readl(S3C64XX_EINT0MASK);
267 mask &= ~((u32)data->chip_data);
268 __raw_writel(mask, S3C64XX_EINT0MASK);
269 }
270
s3c_irq_eint_ack(struct irq_data * data)271 static inline void s3c_irq_eint_ack(struct irq_data *data)
272 {
273 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
274 }
275
s3c_irq_eint_maskack(struct irq_data * data)276 static void s3c_irq_eint_maskack(struct irq_data *data)
277 {
278 /* compiler should in-line these */
279 s3c_irq_eint_mask(data);
280 s3c_irq_eint_ack(data);
281 }
282
s3c_irq_eint_set_type(struct irq_data * data,unsigned int type)283 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
284 {
285 int offs = eint_offset(data->irq);
286 int pin, pin_val;
287 int shift;
288 u32 ctrl, mask;
289 u32 newvalue = 0;
290 void __iomem *reg;
291
292 if (offs > 27)
293 return -EINVAL;
294
295 if (offs <= 15)
296 reg = S3C64XX_EINT0CON0;
297 else
298 reg = S3C64XX_EINT0CON1;
299
300 switch (type) {
301 case IRQ_TYPE_NONE:
302 printk(KERN_WARNING "No edge setting!\n");
303 break;
304
305 case IRQ_TYPE_EDGE_RISING:
306 newvalue = S3C2410_EXTINT_RISEEDGE;
307 break;
308
309 case IRQ_TYPE_EDGE_FALLING:
310 newvalue = S3C2410_EXTINT_FALLEDGE;
311 break;
312
313 case IRQ_TYPE_EDGE_BOTH:
314 newvalue = S3C2410_EXTINT_BOTHEDGE;
315 break;
316
317 case IRQ_TYPE_LEVEL_LOW:
318 newvalue = S3C2410_EXTINT_LOWLEV;
319 break;
320
321 case IRQ_TYPE_LEVEL_HIGH:
322 newvalue = S3C2410_EXTINT_HILEV;
323 break;
324
325 default:
326 printk(KERN_ERR "No such irq type %d", type);
327 return -1;
328 }
329
330 if (offs <= 15)
331 shift = (offs / 2) * 4;
332 else
333 shift = ((offs - 16) / 2) * 4;
334 mask = 0x7 << shift;
335
336 ctrl = __raw_readl(reg);
337 ctrl &= ~mask;
338 ctrl |= newvalue << shift;
339 __raw_writel(ctrl, reg);
340
341 /* set the GPIO pin appropriately */
342
343 if (offs < 16) {
344 pin = S3C64XX_GPN(offs);
345 pin_val = S3C_GPIO_SFN(2);
346 } else if (offs < 23) {
347 pin = S3C64XX_GPL(offs + 8 - 16);
348 pin_val = S3C_GPIO_SFN(3);
349 } else {
350 pin = S3C64XX_GPM(offs - 23);
351 pin_val = S3C_GPIO_SFN(3);
352 }
353
354 s3c_gpio_cfgpin(pin, pin_val);
355
356 return 0;
357 }
358
359 static struct irq_chip s3c_irq_eint = {
360 .name = "s3c-eint",
361 .irq_mask = s3c_irq_eint_mask,
362 .irq_unmask = s3c_irq_eint_unmask,
363 .irq_mask_ack = s3c_irq_eint_maskack,
364 .irq_ack = s3c_irq_eint_ack,
365 .irq_set_type = s3c_irq_eint_set_type,
366 .irq_set_wake = s3c_irqext_wake,
367 };
368
369 /* s3c_irq_demux_eint
370 *
371 * This function demuxes the IRQ from the group0 external interrupts,
372 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
373 * the specific handlers s3c_irq_demux_eintX_Y.
374 */
s3c_irq_demux_eint(unsigned int start,unsigned int end)375 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
376 {
377 u32 status = __raw_readl(S3C64XX_EINT0PEND);
378 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
379 unsigned int irq;
380
381 status &= ~mask;
382 status >>= start;
383 status &= (1 << (end - start + 1)) - 1;
384
385 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
386 if (status & 1)
387 generic_handle_irq(irq);
388
389 status >>= 1;
390 }
391 }
392
s3c_irq_demux_eint0_3(struct irq_desc * desc)393 static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
394 {
395 s3c_irq_demux_eint(0, 3);
396 }
397
s3c_irq_demux_eint4_11(struct irq_desc * desc)398 static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
399 {
400 s3c_irq_demux_eint(4, 11);
401 }
402
s3c_irq_demux_eint12_19(struct irq_desc * desc)403 static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
404 {
405 s3c_irq_demux_eint(12, 19);
406 }
407
s3c_irq_demux_eint20_27(struct irq_desc * desc)408 static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
409 {
410 s3c_irq_demux_eint(20, 27);
411 }
412
s3c64xx_init_irq_eint(void)413 static int __init s3c64xx_init_irq_eint(void)
414 {
415 int irq;
416
417 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
418 if (of_have_populated_dt() || !soc_is_s3c64xx())
419 return -ENODEV;
420
421 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
422 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
423 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
424 irq_clear_status_flags(irq, IRQ_NOREQUEST);
425 }
426
427 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
428 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
429 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
430 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
431
432 return 0;
433 }
434 arch_initcall(s3c64xx_init_irq_eint);
435
s3c64xx_restart(enum reboot_mode mode,const char * cmd)436 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
437 {
438 if (mode != REBOOT_SOFT)
439 samsung_wdt_reset();
440
441 /* if all else fails, or mode was for soft, jump to 0 */
442 soft_restart(0);
443 }
444