1/* 2 * Copyright (C) 2015 Marvell Technology Group Ltd. 3 * 4 * Author: Jisheng Zhang <jszhang@marvell.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPLv2 or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47/ { 48 compatible = "marvell,berlin4ct", "marvell,berlin"; 49 interrupt-parent = <&gic>; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 aliases { 54 serial0 = &uart0; 55 }; 56 57 psci { 58 compatible = "arm,psci-1.0", "arm,psci-0.2"; 59 method = "smc"; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 cpu0: cpu@0 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <0x0>; 70 enable-method = "psci"; 71 next-level-cache = <&l2>; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 }; 74 75 cpu1: cpu@1 { 76 compatible = "arm,cortex-a53", "arm,armv8"; 77 device_type = "cpu"; 78 reg = <0x1>; 79 enable-method = "psci"; 80 next-level-cache = <&l2>; 81 cpu-idle-states = <&CPU_SLEEP_0>; 82 }; 83 84 cpu2: cpu@2 { 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x2>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 cpu-idle-states = <&CPU_SLEEP_0>; 91 }; 92 93 cpu3: cpu@3 { 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <0x3>; 97 enable-method = "psci"; 98 next-level-cache = <&l2>; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 l2: cache { 103 compatible = "cache"; 104 }; 105 106 idle-states { 107 entry-method = "psci"; 108 CPU_SLEEP_0: cpu-sleep-0 { 109 compatible = "arm,idle-state"; 110 local-timer-stop; 111 arm,psci-suspend-param = <0x0010000>; 112 entry-latency-us = <75>; 113 exit-latency-us = <155>; 114 min-residency-us = <1000>; 115 }; 116 }; 117 }; 118 119 osc: osc { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <25000000>; 123 }; 124 125 pmu { 126 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 127 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&cpu0>, 132 <&cpu1>, 133 <&cpu2>, 134 <&cpu3>; 135 }; 136 137 timer { 138 compatible = "arm,armv8-timer"; 139 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 140 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 141 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 142 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 143 }; 144 145 soc@f7000000 { 146 compatible = "simple-bus"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 ranges = <0 0 0xf7000000 0x1000000>; 150 151 gic: interrupt-controller@901000 { 152 compatible = "arm,gic-400"; 153 #interrupt-cells = <3>; 154 interrupt-controller; 155 reg = <0x901000 0x1000>, 156 <0x902000 0x2000>, 157 <0x904000 0x2000>, 158 <0x906000 0x2000>; 159 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 160 }; 161 162 apb@e80000 { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 ranges = <0 0xe80000 0x10000>; 168 interrupt-parent = <&aic>; 169 170 gpio0: gpio@0400 { 171 compatible = "snps,dw-apb-gpio"; 172 reg = <0x0400 0x400>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 porta: gpio-port@0 { 177 compatible = "snps,dw-apb-gpio-port"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 snps,nr-gpios = <32>; 181 reg = <0>; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 interrupts = <0>; 185 }; 186 }; 187 188 gpio1: gpio@0800 { 189 compatible = "snps,dw-apb-gpio"; 190 reg = <0x0800 0x400>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 portb: gpio-port@1 { 195 compatible = "snps,dw-apb-gpio-port"; 196 gpio-controller; 197 #gpio-cells = <2>; 198 snps,nr-gpios = <32>; 199 reg = <0>; 200 interrupt-controller; 201 #interrupt-cells = <2>; 202 interrupts = <1>; 203 }; 204 }; 205 206 gpio2: gpio@0c00 { 207 compatible = "snps,dw-apb-gpio"; 208 reg = <0x0c00 0x400>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 portc: gpio-port@2 { 213 compatible = "snps,dw-apb-gpio-port"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 snps,nr-gpios = <32>; 217 reg = <0>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 interrupts = <2>; 221 }; 222 }; 223 224 gpio3: gpio@1000 { 225 compatible = "snps,dw-apb-gpio"; 226 reg = <0x1000 0x400>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 portd: gpio-port@3 { 231 compatible = "snps,dw-apb-gpio-port"; 232 gpio-controller; 233 #gpio-cells = <2>; 234 snps,nr-gpios = <32>; 235 reg = <0>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 interrupts = <3>; 239 }; 240 }; 241 242 aic: interrupt-controller@3800 { 243 compatible = "snps,dw-apb-ictl"; 244 reg = <0x3800 0x30>; 245 interrupt-controller; 246 #interrupt-cells = <1>; 247 interrupt-parent = <&gic>; 248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 249 }; 250 }; 251 252 soc_pinctrl: pin-controller@ea8000 { 253 compatible = "marvell,berlin4ct-soc-pinctrl"; 254 reg = <0xea8000 0x14>; 255 }; 256 257 avio_pinctrl: pin-controller@ea8400 { 258 compatible = "marvell,berlin4ct-avio-pinctrl"; 259 reg = <0xea8400 0x8>; 260 }; 261 262 apb@fc0000 { 263 compatible = "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges = <0 0xfc0000 0x10000>; 267 interrupt-parent = <&sic>; 268 269 sic: interrupt-controller@1000 { 270 compatible = "snps,dw-apb-ictl"; 271 reg = <0x1000 0x30>; 272 interrupt-controller; 273 #interrupt-cells = <1>; 274 interrupt-parent = <&gic>; 275 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 wdt0: watchdog@3000 { 279 compatible = "snps,dw-wdt"; 280 reg = <0x3000 0x100>; 281 clocks = <&osc>; 282 interrupts = <0>; 283 }; 284 285 wdt1: watchdog@4000 { 286 compatible = "snps,dw-wdt"; 287 reg = <0x4000 0x100>; 288 clocks = <&osc>; 289 interrupts = <1>; 290 }; 291 292 wdt2: watchdog@5000 { 293 compatible = "snps,dw-wdt"; 294 reg = <0x5000 0x100>; 295 clocks = <&osc>; 296 interrupts = <2>; 297 }; 298 299 sm_gpio0: gpio@8000 { 300 compatible = "snps,dw-apb-gpio"; 301 reg = <0x8000 0x400>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 porte: gpio-port@4 { 306 compatible = "snps,dw-apb-gpio-port"; 307 gpio-controller; 308 #gpio-cells = <2>; 309 snps,nr-gpios = <32>; 310 reg = <0>; 311 }; 312 }; 313 314 sm_gpio1: gpio@9000 { 315 compatible = "snps,dw-apb-gpio"; 316 reg = <0x9000 0x400>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 portf: gpio-port@5 { 321 compatible = "snps,dw-apb-gpio-port"; 322 gpio-controller; 323 #gpio-cells = <2>; 324 snps,nr-gpios = <32>; 325 reg = <0>; 326 }; 327 }; 328 329 uart0: uart@d000 { 330 compatible = "snps,dw-apb-uart"; 331 reg = <0xd000 0x100>; 332 interrupts = <8>; 333 clocks = <&osc>; 334 reg-shift = <2>; 335 status = "disabled"; 336 pinctrl-0 = <&uart0_pmux>; 337 pinctrl-names = "default"; 338 }; 339 }; 340 341 system_pinctrl: pin-controller@fe2200 { 342 compatible = "marvell,berlin4ct-system-pinctrl"; 343 reg = <0xfe2200 0xc>; 344 345 uart0_pmux: uart0-pmux { 346 groups = "SM_URT0_TXD", "SM_URT0_RXD"; 347 function = "uart0"; 348 }; 349 }; 350 }; 351}; 352