1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 32 cluster1 { 33 core0 { 34 cpu = <&cpu2>; 35 }; 36 core1 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 }; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72", "arm,armv8"; 45 reg = <0 0x000>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a72", "arm,armv8"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 32>; 56 enable-method = "psci"; 57 operating-points-v2 = <&cluster0_opp>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu2: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53", "arm,armv8"; 64 reg = <0 0x100>; 65 clocks = <&sys_clk 33>; 66 enable-method = "psci"; 67 operating-points-v2 = <&cluster1_opp>; 68 }; 69 70 cpu3: cpu@101 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0 0x101>; 74 clocks = <&sys_clk 33>; 75 enable-method = "psci"; 76 operating-points-v2 = <&cluster1_opp>; 77 #cooling-cells = <2>; 78 }; 79 }; 80 81 cluster0_opp: opp_table0 { 82 compatible = "operating-points-v2"; 83 opp-shared; 84 85 opp-250000000 { 86 opp-hz = /bits/ 64 <250000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-275000000 { 90 opp-hz = /bits/ 64 <275000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-500000000 { 94 opp-hz = /bits/ 64 <500000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-550000000 { 98 opp-hz = /bits/ 64 <550000000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-666667000 { 102 opp-hz = /bits/ 64 <666667000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-733334000 { 106 opp-hz = /bits/ 64 <733334000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-1000000000 { 110 opp-hz = /bits/ 64 <1000000000>; 111 clock-latency-ns = <300>; 112 }; 113 opp-1100000000 { 114 opp-hz = /bits/ 64 <1100000000>; 115 clock-latency-ns = <300>; 116 }; 117 }; 118 119 cluster1_opp: opp_table1 { 120 compatible = "operating-points-v2"; 121 opp-shared; 122 123 opp-250000000 { 124 opp-hz = /bits/ 64 <250000000>; 125 clock-latency-ns = <300>; 126 }; 127 opp-275000000 { 128 opp-hz = /bits/ 64 <275000000>; 129 clock-latency-ns = <300>; 130 }; 131 opp-500000000 { 132 opp-hz = /bits/ 64 <500000000>; 133 clock-latency-ns = <300>; 134 }; 135 opp-550000000 { 136 opp-hz = /bits/ 64 <550000000>; 137 clock-latency-ns = <300>; 138 }; 139 opp-666667000 { 140 opp-hz = /bits/ 64 <666667000>; 141 clock-latency-ns = <300>; 142 }; 143 opp-733334000 { 144 opp-hz = /bits/ 64 <733334000>; 145 clock-latency-ns = <300>; 146 }; 147 opp-1000000000 { 148 opp-hz = /bits/ 64 <1000000000>; 149 clock-latency-ns = <300>; 150 }; 151 opp-1100000000 { 152 opp-hz = /bits/ 64 <1100000000>; 153 clock-latency-ns = <300>; 154 }; 155 }; 156 157 psci { 158 compatible = "arm,psci-1.0"; 159 method = "smc"; 160 }; 161 162 clocks { 163 refclk: ref { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <25000000>; 167 }; 168 }; 169 170 timer { 171 compatible = "arm,armv8-timer"; 172 interrupts = <1 13 4>, 173 <1 14 4>, 174 <1 11 4>, 175 <1 10 4>; 176 }; 177 178 soc@0 { 179 compatible = "simple-bus"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges = <0 0 0 0xffffffff>; 183 184 serial0: serial@54006800 { 185 compatible = "socionext,uniphier-uart"; 186 status = "disabled"; 187 reg = <0x54006800 0x40>; 188 interrupts = <0 33 4>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_uart0>; 191 clocks = <&peri_clk 0>; 192 }; 193 194 serial1: serial@54006900 { 195 compatible = "socionext,uniphier-uart"; 196 status = "disabled"; 197 reg = <0x54006900 0x40>; 198 interrupts = <0 35 4>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_uart1>; 201 clocks = <&peri_clk 1>; 202 }; 203 204 serial2: serial@54006a00 { 205 compatible = "socionext,uniphier-uart"; 206 status = "disabled"; 207 reg = <0x54006a00 0x40>; 208 interrupts = <0 37 4>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_uart2>; 211 clocks = <&peri_clk 2>; 212 }; 213 214 serial3: serial@54006b00 { 215 compatible = "socionext,uniphier-uart"; 216 status = "disabled"; 217 reg = <0x54006b00 0x40>; 218 interrupts = <0 177 4>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_uart3>; 221 clocks = <&peri_clk 3>; 222 }; 223 224 adamv@57920000 { 225 compatible = "socionext,uniphier-ld20-adamv", 226 "simple-mfd", "syscon"; 227 reg = <0x57920000 0x1000>; 228 229 adamv_rst: reset { 230 compatible = "socionext,uniphier-ld20-adamv-reset"; 231 #reset-cells = <1>; 232 }; 233 }; 234 235 i2c0: i2c@58780000 { 236 compatible = "socionext,uniphier-fi2c"; 237 status = "disabled"; 238 reg = <0x58780000 0x80>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <0 41 4>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_i2c0>; 244 clocks = <&peri_clk 4>; 245 clock-frequency = <100000>; 246 }; 247 248 i2c1: i2c@58781000 { 249 compatible = "socionext,uniphier-fi2c"; 250 status = "disabled"; 251 reg = <0x58781000 0x80>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 interrupts = <0 42 4>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_i2c1>; 257 clocks = <&peri_clk 5>; 258 clock-frequency = <100000>; 259 }; 260 261 i2c2: i2c@58782000 { 262 compatible = "socionext,uniphier-fi2c"; 263 reg = <0x58782000 0x80>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 interrupts = <0 43 4>; 267 clocks = <&peri_clk 6>; 268 clock-frequency = <400000>; 269 }; 270 271 i2c3: i2c@58783000 { 272 compatible = "socionext,uniphier-fi2c"; 273 status = "disabled"; 274 reg = <0x58783000 0x80>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <0 44 4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_i2c3>; 280 clocks = <&peri_clk 7>; 281 clock-frequency = <100000>; 282 }; 283 284 i2c4: i2c@58784000 { 285 compatible = "socionext,uniphier-fi2c"; 286 status = "disabled"; 287 reg = <0x58784000 0x80>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 interrupts = <0 45 4>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_i2c4>; 293 clocks = <&peri_clk 8>; 294 clock-frequency = <100000>; 295 }; 296 297 i2c5: i2c@58785000 { 298 compatible = "socionext,uniphier-fi2c"; 299 reg = <0x58785000 0x80>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 interrupts = <0 25 4>; 303 clocks = <&peri_clk 9>; 304 clock-frequency = <400000>; 305 }; 306 307 system_bus: system-bus@58c00000 { 308 compatible = "socionext,uniphier-system-bus"; 309 status = "disabled"; 310 reg = <0x58c00000 0x400>; 311 #address-cells = <2>; 312 #size-cells = <1>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_system_bus>; 315 }; 316 317 smpctrl@59801000 { 318 compatible = "socionext,uniphier-smpctrl"; 319 reg = <0x59801000 0x400>; 320 }; 321 322 sdctrl@59810000 { 323 compatible = "socionext,uniphier-ld20-sdctrl", 324 "simple-mfd", "syscon"; 325 reg = <0x59810000 0x400>; 326 327 sd_clk: clock { 328 compatible = "socionext,uniphier-ld20-sd-clock"; 329 #clock-cells = <1>; 330 }; 331 332 sd_rst: reset { 333 compatible = "socionext,uniphier-ld20-sd-reset"; 334 #reset-cells = <1>; 335 }; 336 }; 337 338 perictrl@59820000 { 339 compatible = "socionext,uniphier-ld20-perictrl", 340 "simple-mfd", "syscon"; 341 reg = <0x59820000 0x200>; 342 343 peri_clk: clock { 344 compatible = "socionext,uniphier-ld20-peri-clock"; 345 #clock-cells = <1>; 346 }; 347 348 peri_rst: reset { 349 compatible = "socionext,uniphier-ld20-peri-reset"; 350 #reset-cells = <1>; 351 }; 352 }; 353 354 emmc: sdhc@5a000000 { 355 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 356 reg = <0x5a000000 0x400>; 357 interrupts = <0 78 4>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_emmc>; 360 clocks = <&sys_clk 4>; 361 bus-width = <8>; 362 mmc-ddr-1_8v; 363 mmc-hs200-1_8v; 364 cdns,phy-input-delay-legacy = <4>; 365 cdns,phy-input-delay-mmc-highspeed = <2>; 366 cdns,phy-input-delay-mmc-ddr = <3>; 367 cdns,phy-dll-delay-sdclk = <21>; 368 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 369 }; 370 371 soc-glue@5f800000 { 372 compatible = "socionext,uniphier-ld20-soc-glue", 373 "simple-mfd", "syscon"; 374 reg = <0x5f800000 0x2000>; 375 376 pinctrl: pinctrl { 377 compatible = "socionext,uniphier-ld20-pinctrl"; 378 }; 379 }; 380 381 aidet: aidet@5fc20000 { 382 compatible = "socionext,uniphier-ld20-aidet"; 383 reg = <0x5fc20000 0x200>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 }; 387 388 gic: interrupt-controller@5fe00000 { 389 compatible = "arm,gic-v3"; 390 reg = <0x5fe00000 0x10000>, /* GICD */ 391 <0x5fe80000 0x80000>; /* GICR */ 392 interrupt-controller; 393 #interrupt-cells = <3>; 394 interrupts = <1 9 4>; 395 }; 396 397 sysctrl@61840000 { 398 compatible = "socionext,uniphier-ld20-sysctrl", 399 "simple-mfd", "syscon"; 400 reg = <0x61840000 0x10000>; 401 402 sys_clk: clock { 403 compatible = "socionext,uniphier-ld20-clock"; 404 #clock-cells = <1>; 405 }; 406 407 sys_rst: reset { 408 compatible = "socionext,uniphier-ld20-reset"; 409 #reset-cells = <1>; 410 }; 411 412 watchdog { 413 compatible = "socionext,uniphier-wdt"; 414 }; 415 }; 416 417 nand: nand@68000000 { 418 compatible = "socionext,uniphier-denali-nand-v5b"; 419 status = "disabled"; 420 reg-names = "nand_data", "denali_reg"; 421 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 422 interrupts = <0 65 4>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_nand>; 425 clocks = <&sys_clk 2>; 426 }; 427 }; 428}; 429 430#include "uniphier-pinctrl.dtsi" 431